CN101853231B

CN101853231B - Mainboard, computer and storage device

Info

Publication number: CN101853231B
Application number: CN 200910081041
Authority: CN
Inventors: 党兆帅
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2009-03-31
Filing date: 2009-03-31
Publication date: 2013-01-16
Anticipated expiration: 2029-03-31
Also published as: CN101853231A

Abstract

The invention provides a mainboard, a computer and a storage device. The mainboard comprises a south bridge chip and an interface, wherein the south bridge chip comprises a universal serial bus (USB) input/output (IO) data pin and a serial advanced technology attachment (SATA) IO data pin; the interface comprises a power supply pin, a grounding pin and a data pin; the data pin comprises a first group of data pins connected with the USB IO data pin and a second group of data pins connected with the SATA IO data pin; when a USB type device is inserted into the interface, the power supply pin supplies power and the first group of data pins transmit data; and when a SATA type device is inserted into the interface, the power supply pin supplies power and the second group of data pins transmit data. A 3G card as well as a solid state disk (SSD) can be inserted into a PCI-e interface. Requirement and cost on a design space of a system are lowered; and a small-capacity SSD is compatible, so that coexistence of the SSD and a normal disk in a computer system can be realized.

Description

A kind of mainboard, computing machine and memory device

Technical field

The present invention relates to computer realm, relate in particular to a kind of mainboard, computing machine and memory device.

Background technology

Because SSD is (Solid State Disk, solid state hard disc) different with the interface standard of 3G card, SSD uses SATAII (Serial ATAII, serial ATA II) interface definition, and the 3G card uses the USB interface definition, so, at present on the general machine or design an interface that connects the 3G card, perhaps design an interface that meets SSD.

Present computing machine does not also have the interface that satisfies simultaneously SSD and 3G card.

Summary of the invention

The purpose of this invention is to provide a kind of mainboard, computing machine and memory device, to solve the card that present computer interface can't the compatible USB of use standard and to use the problem of the card of SATAII standard.Mainboard of the present invention comprises:

South Bridge chip comprises the data class pin of USB IO and the data class pin of SATA IO;

Interface, described interface comprises:

Power supply class pin;

Ground connection class pin;

The data class pin, described data class pin comprises:

First group of data pins is connected with the data class pin of described USB IO;

Second group of data pins is connected with the data class pin of described SATA IO;

Wherein, when inserting the USB kind equipment in the described interface, the pin by described power supply class is described USB kind equipment power supply, and by described first group of data pins the transmission of data; When inserting the SATA kind equipment in the described interface, the pin by described power supply class is described SATA kind equipment power supply, and by described second group of data pins the transmission of data.

Described interface is the PCI-e interface.

Described power supply class pin is connected with the power supply class pin of USB IO, perhaps is connected with the power supply class pin of SATA IO, perhaps simultaneously is connected power supply class pin with SATA IO with the power supply class pin of USB IO and is connected.

The present invention also provides a kind of computing machine, comprising:

Mainboard,

South Bridge chip is arranged on the described mainboard, comprises the data class pin of USB IO and the data class pin of SATA IO;

Interface is arranged on the described mainboard, and described interface comprises:

Power supply class pin;

Ground connection class pin;

The data class pin, described data class pin comprises:

Described interface is the PCI-e interface.

The present invention also provides a kind of memory device, comprising:

Memory bank is used for the storage data;

Circuit board;

First interface is connected with described memory bank by described circuit board, is used for being connected with the second interface of a data processing equipment, and described first interface comprises at least:

Power supply class pin is used for obtaining electric power;

Ground connection class pin;

The data class pin, described data class pin comprises:

First group of data pins is used for the first host-host protocol the transmission of data;

Second group of data pins is used for the second host-host protocol the transmission of data;

Wherein said the first host-host protocol is different from the second host-host protocol.

Described first interface also comprises: reserved pin.

Described the second interface is the interface identical with described first interface, perhaps for using the interface of the first host-host protocol the transmission of data, perhaps for using the interface of the second host-host protocol the transmission of data.

Compared with prior art, the present invention has following beneficial effect:

The present invention has changed conventional P CI-e (Peripheral Component Interconnection-Express, the high-speed peripheral assembly interconnect) interface of card and the mode of connection of computer motherboard south bridge, make in the interface pin of PCI-e card, except be connected respectively to USB IO and the SATA IO of south bridge by common power pin, in the pin of the transmission of data, a part is connected with the USB IO of south bridge, and another part pin that is not connected with USB IO then is connected with the SATA IO of south bridge.Re-start definition by this interface pin to conventional P CI-e card, so that under the prerequisite of the interface structure that does not change conventional P CI-e card, in the interface of a PCI-e card, can either insert the 3G card, can insert SSD again.Thereby requirement and the cost in system space have significantly been reduced; And by compatible low capacity SSD, exist simultaneously so that computer system can realize SSD and normal hard disk, utilize the high speed of SSD and the characteristics of life-span length, operating system installation in SSD, has significantly been promoted the competitive power of product.

Description of drawings

Fig. 1 is the compatibility interface of mainboard of the present invention and the wiring schematic diagram of south bridge;

Fig. 2 is the interface of the 3G card of existing mainboard and the wiring schematic diagram of south bridge;

Fig. 3 is the pin of compatibility interface of the present invention and the mode of connection synoptic diagram of South Bridge chip pin;

Fig. 4 is the structural representation that compatibility interface of the present invention is applied to memory device.

Embodiment

The embodiment of the invention has newly designed an interface on notebook or desktop computer, make it to satisfy the SATA interface standard, can satisfy standard usb interface again.The equipment of SATA class (for example, SATA hard disk, E-SATA hard disk etc.) can carry out data transmission by this interface like this, and the equipment of USB class (for example, USB flash disk, 3G card etc.) also can carry out data transmission by this interface.Thereby saved the space, two interfaces (for example, SATA interface and USB interface) of different pieces of information host-host protocol need to be installed in notebook or in the desktop computer.

An alternative embodiment of the invention has newly designed a memory device, and the data class pin in the interface of described memory device has the data pins of two groups of different pieces of information host-host protocols (being first data transmission agreement and the second Data Transport Protocol).So that can either being inserted into, described memory device carries out data transmission in the data processing equipment with first host-host protocol interface, also can be inserted into and carry out data transmission in the data processing equipment with second host-host protocol interface, can also be inserted into simultaneously in the interface data treatment facility with two kinds of Data Transport Protocols with two kinds of Data Transport Protocols while the transmission of datas.

In conjunction with embodiment, for example by having redesigned the PCI-e interface on notebook or the desktop computer, make it to satisfy the SATAII interface standard that SSD uses, can satisfy again the standard usb interface that the 3G card uses, that is to say, this interface can be inserted SSD, can insert the 3G card again, can guarantee that again they can both work simultaneously.Further, owing to be to have redesigned the PCI-e interface, so this interface can also the equipment of Supporting connectivity on the PCI-e interface, for example, WiMax, Wlan, WWAN, GPS etc.

Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.

Present embodiment is take the SSD that has respectively 52 pins and 3G card as example, how to realize working after specifying the PCI-e interface that SSD and 3G card insert redesign.The PCI-e interface of present embodiment (being compatibility interface) is arranged on the mainboard.

With reference to figure 1, Fig. 1 is the compatibility interface of mainboard of the present invention and the wiring schematic diagram of south bridge, comprising: compatibility interface (PCI-e interface) and South Bridge chip.The structure of compatibility interface is exactly the interface structure of existing Mini PCI-e card.Comprise on the South Bridge chip: the pin of the pin of USB IO and SATA IO.The present invention is connected to the pin of the USB IO of south bridge with the pin of use usb protocol the transmission of data (for example 3G card) on the PCI-e interface of redesign by data line, and will use the pin of SATA protocol transmission data (for example SSD) to be connected to the pin of the SATA IO of south bridge by data line.With reference to shown in Figure 2, Fig. 2 is the interface pin of the 3G card of existing mainboard and the wiring schematic diagram of south bridge, and the interface pin of 3G card is connected to the USB IO of South Bridge chip by data line.

Shown in the interface pin definition reference table 1 of existing 3G card:

Table 1

Pin	The USB definition	Pin	The USB definition
				1	Wake#	2	+3.3V
3	No Connect	4	GND
				5	No Connect	6	+1.5V

7	No Connect	8	UIM Pwr
				9	GND	10	UIM Data
11	No Connect	12	UIM Clk
				13	No Connect	14	UIM Reset
15	GND	16	UIM Vpp
				17	No Connect	18	GND
19	No Connect	20	W DISABLE#
				21	GND	22	No Connect
23	No Connect	24	+3.3V
				25	No Connect	26	GND
27	GND	28	+1.5V
				29	GND	30	No Connect
31	No Connect	32	No Connect
				33	No Connect	34	GND
35	GND	36	USB D-
				37	GND	38	USB D+
39	+3.3V	40	GND
				41	+3.3V	42	LED WWAN
43	GND	44	No Connect
				45	No Connect	46	No Connect
47	No Connect	48	+1.5V
				49	No Connect	50	GND
51	No Connect	52	+3.3V

Shown in the interface pin definition reference table 2 of existing SSD:

Table 2

Pin	Definition	Pin	Definition
				1	No Connect	2	+3.3V
3	No Connect	4	GND
				5	No Connect	6	+1.5V
7	No Connect	8	No Connect
				9	GND	10	No Connect
11	No Connect	12	No Connect
				13	No Connect	14	No Connect
15	GND	16	No Connect
				17	No Connect	18	GND
19	No Connect	20	Presence Detect
				21	GND	22	No Connect
23	+B	24	+3.3V
				25	-B	26	GND

27	GND	28	+1.5V
				29	GND	30	DA/DSS
31	-A	32	No Connect
				33	+A	34	GND
35	GND	36	No Connect
				37	GND	38	No Connect
39	+3.3V	40	GND
				41	+3.3V	42	No Connect
43	GND	44	No Connect
				45	No Connect	46	Vendor
47	No Connect	48	+1.5V
				49	No Connect	50	GND
51	No Connect	52	+3.3V

Contrast table 1 and table 2 are as can be known, the pin that is used for power supply in table 1 and the table 2 all is one to one, for example, be used in the table 1 power supply pin two (+3.3V) corresponding to table 2 be used for power supply pin two (+3.3V), be used in the table 1 power supply pin 6 (+1.5V) corresponding to table 2 be used for power supply pin 6 (+1.5V).

Ground pin in table 1 and the table 2 also all is one to one, and the pin of ground connection (GND) corresponds respectively to the pin (GND) of ground connection in the table 2 in the table 1.

Some reserved pin is corresponding to the reserved pin in the table 2 in the table 1, and for example, the

3,5,7,11,13,17,19,22,44,45,46,47 in table 1 and the table 2,49 and 51 all is reserved pin.

Except being used for pin, ground pin and the common reserved pin of power supply, the remaining pin that is used for the transmission of data of table 1 and table 2.

The pin that is used for the transmission of data in the table 1 is pin one, 8,10,12,14,16,20,36,38,42, and corresponding pin one, 8,10,12,14,16,20,36,38,42 all is to reserve (not connecting) pin in the table 2.

The pin that is used for the transmission of data in the table 2 is pin two 3,25,30,31,33,46, and corresponding pin two 3,25,30,31,33,46 all is to reserve (not connecting) pin in the table 1.

The above-mentioned rule that exists based on the pin feature of table 1 and table 2, because the pin of 3G card the transmission of data is connected with USB IO, and the pin of SSD the transmission of data is connected with SATA IO, therefore, mutual conflict can not occur in the pin of the two the transmission of data, can design a compatibility interface, can either insert the 3G card, can insert SSD again, and can work.

The below describes the pin definitions of the compatibility interface of present embodiment, shown in the reference table 3:

Table 3

Pin	The USB definition	Pin	The USB definition
				1	Wake#	2	+3.3V
3	No Connect	4	GND
				5	No Connect	6	+1.5V
7	No Connect	8	UIM Pwr
				9	GND	10	UIM Data
11	No Connect	12	UIM Clk
				13	No Connect	14	UIM Reset
15	GND	16	UIM Vpp
				17	No Connect	18	GND
19	No Connect	20	W DISABLE#
				21	GND	22	No Connect
23	+B	24	+3.3V
				25	-B	26	GND
27	GND	28	+1.5V
				29	GND	30	DA/DSS
31	-A	32	Presence Detect
				33	+A	34	GND
35	GND	36	USB D-
				37	GND	38	USB D+
39	+3.3V	40	GND
				41	+3.3V	42	LED WWAN
43	GND	44	No Connect
				45	No Connect	46	No Connect
47	No Connect	48	+1.5V
				49	No Connect	50	GND
51	No Connect	52	+3.3V

Can find that by contrast table 1, table 2 and table 3 rule of each pin definitions of the compatibility interface of table 3 is:

The first, power supply class pin, the power supply class pin definitions that is connected with power supply is constant, still with table 1 and table 2 in define identical.For example, table 1 with during table is connected with pin that power supply is connected in, 2,24,39,41,52 all are defined as+3.3V, corresponding pin also all is defined as+3.3V in the table 3; Table 1 with during table is connected with pin that power supply is connected in, 6,28,48 all are defined as+1.5V, corresponding pin also all is defined as+1.5V in the table 3.The pin of this power supply class pin for sharing, no matter this interface connection is equipment or the USB kind equipment of SATA class, this power supply class pin all is the power devices that is connected on the interface.

The second, ground connection class pin, the definition of this ground connection class pin is constant, and the pin 4,9,15,18,21,26,27,29,34,35,37,40,43,50 in table 1 and the table 2 all is defined as GND, and corresponding pin also all is defined as GND in the table 3.This ground connection class pin is the pin for sharing also, no matter this interface connection is equipment or the USB kind equipment of SATA class, this power supply class pin all is the equipment ground that is connected on the interface.

The 3rd, corresponding common reserved pin in table 1 and the table 2 also is reserved pin corresponding to the respective pin in the table 3.For example, the

3,5,7,11,13,17,19,22,44,45,46,47 in table 1 and the table 2,49 and 51 all is reserved pin, also is reserved pin corresponding to the respective pin in the table 3.This class reserved pin is the pin for sharing also.

The 4th, except the pin in the above-mentioned the first to the 3rd, what table 1 and table 2 were remaining is the data class pin, is used for the transmission of data.Data class pin in the table 1 has identical definition with corresponding data class pin in the table 3, the data class pin in the table 2 also with table 3 in corresponding data class pin have identical definition.For example, the pin one in the table 1 is defined as Wake#, and the pin one in the table 3 is defined as Wake# so; Pin 8 in the table 1 is defined as UIM Pwr, and the pin in the table 38 is defined as UIM Pwr so.Pin 30 in the table 2 is defined as DA/DSS, and the pin in the table 3 30 is defined as DA/DSS so.

According to the definition of table 3, the mainboard that embodiments of the invention provide comprises: South Bridge chip and interface, this South Bridge chip comprise the data class pin of USB IO and the data class pin of SATA IO.

This interface comprises: power supply class pin; Ground connection class pin; The data class pin, this data class pin comprises: first group of data pins is connected with the data class pin of USB IO; Second group of data pins is connected with the data class pin of SATA IO; Wherein, when inserting the USB kind equipment in the interface, the pin by the power supply class is the power supply of USB kind equipment, and by first group of data pins the transmission of data; When inserting the SATA kind equipment in the interface, the pin by the power supply class is the power supply of SATA kind equipment, and by second group of data pins the transmission of data.

This interface also comprises: reserved pin is not defined as connection.

Wherein, power supply class pin, ground connection class pin, reserved pin all are the pin that shares.No matter what this interface connected is equipment or the USB kind equipment of SATA class, these pins that share all provide corresponding function for the equipment that is connected on this interface.

Power supply class pin in the above-mentioned interface is connected with the power supply class pin of USB IO, perhaps is connected with the power supply class pin of SATA IO, perhaps simultaneously is connected power supply class pin with SATA IO with the power supply class pin of USB IO and is connected.

More than the definition of pin be actually be connected to realize by data line between pin and the south bridge:

Common reserved pin neither with south bridge on corresponding USB IO connect, also not with south bridge on corresponding SATA IO connection.

In the data class pin, the data transmission pin of corresponding USB IO connects on the data transmission pin of the USB interface of table 1 and the south bridge, the data transmission pin connection of corresponding SATAIO on the data transmission pin of the SATA interface of table 2 and the south bridge.

The connected mode that above-mentioned power supply class pin is connected with power supply can comprise following several:

The first, power supply class pin is connected with embedded controller (EC) on the mainboard, by embedded controller to corresponding power pin provide required+3.3V or+1.5V electric power.

The second, power supply class pin is connected with power pin on the SATA IO with USB IO respectively, perhaps only be connected with power pin on the USB IO, perhaps be connected with power pin on the SATA IO.So no matter insert the interface of any type at mainboard, can obtain required electric power supply.

After carrying out being connected of pin and south bridge by above-mentioned connected mode, when inserting the equipment (for example 3G card) that uses the USB class, data transmission pin on the 3G card all is connected to USB IO by data line, does not therefore have signal and exports from the data line that is connected with SATA IO.

When inserting the equipment (for example SSD) that uses SATA IO, the data transmission pin on the SSD all is connected to SATA IO by data line, therefore, does not have signal and exports from the data line that is connected with USB IO.

The pin of the compatibility interface of present embodiment (PCI-e interface) and the mode of connection synoptic diagram of South Bridge chip pin are with reference to shown in Figure 3.The definition of the pin shown in Fig. 3 middle table 3 that sees above.

Pin one is defined as WAKE# in table 1, belong to data transmission class pin, is used for using USB host-host protocol the transmission of data, and therefore, pin one is connected with corresponding data class pin on the USB IO.

Pin two all is defined as in table 1 and table 2+3.3V, belongs to power supply class pin, respectively with USBIO on power pin and the power pin on the SATA IO be connected.

Pin 3 table 1 with all be defined as not connecting during table is connected, belong to reserved pin, neither be connected with USB IO, be not connected with SATA IO yet.

Pin 4 all is defined as GND (ground connection) in table 1 and table 2, belong to ground pin, is connected with SATA IO with USB IO respectively.

Pin 5 table 1 with all be defined as not connecting during table is connected, belong to reserved pin, neither be connected with USB IO, be not connected with SATA IO yet.

Pin 6 all is defined as in table 1 and table 2+1.5V, belongs to power supply class pin, is connected with power pin on the SATA IO with power pin on the USBIO respectively.

Pin 7 table 1 with all be defined as not connecting during table is connected, belong to reserved pin,, neither be connected with USBIO, be not connected with SATA IO yet.

Pin 8 is defined as UIM_PWR in table 1, belong to data transmission class pin, is used for using USB host-host protocol the transmission of data, and therefore, pin 8 is connected with corresponding data class pin on the USB IO.

Pin 30 is defined as DA/DSS in table 2, belong to data transmission class pin, is used for using SATA host-host protocol the transmission of data, and therefore, pin 30 is connected with corresponding data class pin on the SATA IO.

Remaining pin also all is the connection of carrying out in the manner described above, describes no longer one by one here.

The compatibility interface that is arranged on the mainboard of present embodiment is applicable to the Mini PCI-e card of any use usb data transmission line and the equipment such as SSD of use SATA data line.

Above-mentioned interface is the PCI-e interface, the PCI-e interface except the equipment of the equipment that can support the USB class and SATA class, equipment that can also the other types of Supporting connectivity on the PCI-e interface, for example, WiMax, Wlan, WWAN, GPS etc.Each pin definitions of PCI-e interface and description references table 4.

Table 4

Pin	The PCI-e+USB+SATA definition	The PCI-e explanation
			1	WAKE#	Request system to return from sleep/suspend
2	+3.3V	3.3V Source
			3	COEX1	For wireless coexistence solutions
4	GND	Return Current Path
			5	COEX2	For wireless coexistence solutions
6	+1.5V	1.5V Source
			7	CLKREQ#	Reference clock signal request
8	UIM_PWR	Power source for the UIM(User Identity Module)
			9	GND	Return Current Path
10	UIM_DATA	UIM data signal
			11	REFLCK-	PCI Express differential reference clock

12	UIM_CLK	Clock signal for UIM card
			13	REFLCK+	PCI Express differential reference clock
14	UIM_RESET	Reset for UIM card
			15	GND	Return Current Path
16	UIM_VPP	Variable supply voltage for UIM.
			17	Reserved*(UIM C8)
18	GND	Return Current Path
			19	Reserved*(UIM_C4)
20	W_DISABLE#	Used to disable radio operations
			21	GND	Return Current Path
22	PERST#	Function reset of the card
			23	PERn0	Differential receive for PCIe x 1data interface
24	+3.3V	3.3V Source
			25	PERp0	Differential receive for PCIe x l data interface
26	GND	Return Current Path
			27	GND	Return Current Path
28	+1.5V	1.5V Source
			29	GND	Return Current Path
30	SMB_CLK	SMBus clock signal
			31	PETn0	Differential transmit for PCIe x 1data interface
32	SMB_DATA	SMBus data signal
			33	PETp0	Differential transmit for PCIe x 1data interface
34	GND	Return Current Path
			35	GND	Return Current Path
36	USB_D-	USB serial data interface(USB 2.0)
			37	GND	Return Current Path
38	USB_D+	USB serial data interface(USB 2.0)
			39	+3.3V	3.3V Source
40	GND	Return Current Path
			41	+3.3V	3.3V Source
42	LED_WWAN#	LED status indicator
			43	GND	Return Current Path
44	LED_WLAN#	LED status indicator
			45	-A(port 1)	SATA Differential
46	LED_WPAN#	LED status indicator
			47	+A(port 1)	SATA Differential
48	+1.5V	1.5V Source
			49	+B(port 1)	SATA Differential
50	GND	Return Current Path

51	-B(port 1)	SATA Differential
			52	+3.3V	3.3V Source

Embodiments of the invention also provide a kind of computing machine, comprising:

Mainboard,

South Bridge chip is arranged on the described mainboard, comprises the data class pin and the data class pin that comprises SATA IO of USB IO;

Interface is arranged on the mainboard, and described interface comprises:

Power supply class pin;

Ground connection class pin;

The data class pin, described data class pin comprises:

Wherein, when inserting the USB kind equipment in the interface, the pin by the power supply class is the power supply of USB kind equipment, and by first group of data pins the transmission of data; When inserting the SATA kind equipment in the interface, the pin by the power supply class is the power supply of SATA kind equipment, and by second group of data pins the transmission of data.

The see above description of middle his-and-hers watches 1～3 of the concrete connected mode of the concrete connected mode of first group of data pins and the first data class pin and second group of data pins and the second data class pin repeats no more here.

Below among embodiment, compatibility interface is applied on the memory device (for example USB flash disk), with reference to shown in Figure 4, Fig. 4 is the structural representation that compatibility interface of the present invention is applied to memory device, and the memory device of embodiments of the invention comprises: memory bank, circuit board and first interface.The compatibility interface that first interface is namely above described.First interface is connected with memory bank by circuit board.This memory device can be connected to the second interface on the data processing equipment (for example computing machine) by first interface, is used for the transmission of data.

First interface comprises:

Power supply class pin is used for obtaining electric power;

Ground connection class pin;

The data class pin comprises:

Wherein the first host-host protocol is different from the second host-host protocol, and host-host protocol can adopt USB host-host protocol, SATA host-host protocol, e-SATA host-host protocol etc.

Above-mentioned the second interface can be to use the interface of USB standard or the interface of use SATAII standard or the USB standard of both can using of above describing also can use the SATAII standard to carry out the compatibility interface of data transmission.Shown in Figure 4 is that the second interface was for both can use the USB standard also can use the SATAII standard to carry out the situation of the compatibility interface of data transmission, the pin of the second interface is connected respectively to USB IO and the SATA IO on the mainboard south bridge, connected mode above is described, and repeats no more here.

If the second interface is the interface that uses the USB standard, then the line between the second interface and the SATA IO does not exist among Fig. 4, is connected in existing mode between the second interface and the USB IO.

If the second interface is the interface that uses the SATAII standard, then the line between the second interface and the USB IO does not exist among Fig. 4, and the connected mode between the second interface and the SATA IO is described above, and repeats no more here.

When the second interface is when using the interface of USB standard, the pin of the second interface is connected with USB IO by data line, after memory device inserted the second interface, the pin of the first interface on the memory device also all is connected to USB IO by data line, and the data line corresponding with the SATA interface all do not connect, therefore do not have signal and export from the data line that is connected with SATA IO, use USB host-host protocol the transmission of data this moment.

When the second interface is when using the interface of SATAII standard, the pin of the second interface is connected with SATA IO by data line, after memory device inserted the second interface, the pin of the first interface on the memory device also all is connected to SATA IO by data line, and the data line corresponding with USB interface all do not connect, therefore do not have signal and export from the data line that is connected with USB IO, use SATA host-host protocol the transmission of data this moment.

When the second interface is the interface identical with first interface, namely, in the time of not only can having used the USB standard but also can use the interface of SATAII standard transmission data, after memory device inserted the second interface, the pin of the first interface on the memory device both can be connected to USB IO by data line, also can be connected to SATA IO by data line, at this moment, can use simultaneously USB host-host protocol and SATA host-host protocol the transmission of data.The speed of the transmission of data just can be greatly improved like this.But, use simultaneously USB host-host protocol and SATA host-host protocol the transmission of data to be applicable to the larger file of transmitted data amount.If the data volume of transmission hour, does not need to use simultaneously USB host-host protocol and SATA host-host protocol the transmission of data, get final product and only need to select suitable host-host protocol carry out data transmission according to the size of the data volume of transmission.

How the below illustrates with several concrete examples and use dissimilar host-host protocols in the situation of transmission different pieces of information amount.

Behind the second interface on the first interface insertion computing machine of memory device, if transmit the movie file of a 64G to memory device from the D dish of computing machine, system's meeting automatic decision goes out the size of the file that will transmit so, size and a preset range value of the current file that will transmit are compared, for example, the preset range value is 2～60G, and the movie file of current transmission is 64G, maximal value than preset range is also large, at this moment, use simultaneously USB host-host protocol and SATA host-host protocol the transmission of data.

If the current word document that will transmit a 128k, system judges 128k less than the minimum value 2G of preset range, therefore, comes the transmission of data with the USB host-host protocol.

If the current film that will transmit a 50G size, system judges 50G in preset range, therefore, comes the transmission of data with the SATA host-host protocol.

The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. a mainboard is characterized in that, comprising:

Interface, described interface are that the PCI-e interface comprises:

Power supply class pin;

Ground connection class pin;

The data class pin, described data class pin comprises:

2. mainboard as claimed in claim 1 is characterized in that, described power supply class pin is connected with the power supply class pin of USB IO, perhaps is connected with the power supply class pin of SATA IO, perhaps simultaneously is connected power supply class pin with SATA IO with the power supply class pin of USB IO and is connected.

3. computing machine comprises:

Mainboard,

Interface is arranged on the described mainboard, and described interface is that the PCI-e interface comprises:

Power supply class pin;

Ground connection class pin;

The data class pin, described data class pin comprises:

4. computing machine as claimed in claim 3, it is characterized in that, described power supply class pin is connected with the power supply class pin of USB IO, perhaps is connected with the power supply class pin of SATA IO, perhaps simultaneously is connected power supply class pin with SATA IO with the power supply class pin of USB IO and is connected.

5. a memory device is characterized in that, comprising:

Memory bank is used for the storage data;

Circuit board;

First interface is connected with described memory bank by described circuit board, is used for being connected with the second interface of a data processing equipment, and described first interface is that the PCI-e interface comprises at least:

Power supply class pin is used for obtaining electric power;

Ground connection class pin;

The data class pin, described data class pin comprises:

First group of data pins is used for the first host-host protocol the transmission of data, and the first host-host protocol is the USB host-host protocol;

Second group of data pins is used for the second host-host protocol the transmission of data, and the second host-host protocol is SATA host-host protocol or e-SATA host-host protocol;

6. memory device as claimed in claim 5 is characterized in that, described first interface also comprises: reserved pin.

7. memory device as claimed in claim 6 is characterized in that, described the second interface is the interface identical with described first interface, perhaps for using the interface of the first host-host protocol the transmission of data, perhaps for using the interface of the second host-host protocol the transmission of data.