CN112306952A

CN112306952A - Mainboard and server

Info

Publication number: CN112306952A
Application number: CN202011342495.8A
Authority: CN
Inventors: 柳胜杰; 杨晓君; 李晶晶; 张腾; 孙瑛琪
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-11-25
Filing date: 2020-11-25
Publication date: 2021-02-02

Abstract

The embodiment of the invention discloses a mainboard and a server, and relates to the technical field of computers. The system comprises a printed circuit board, wherein a processor socket, a memory slot and a first speed interface assembly are arranged on the printed circuit board, the processor socket is used for mounting a processor, and the first speed interface assembly comprises a plurality of PCIE slots, an OCP connector, an SATA connector and an M.2 connector; the processor socket is respectively and electrically connected with the plurality of memory slots, the PCIE slot, the OCP connector, the SATA connector and the M.2 connector, and each memory slot supports installation of any one of the UDIMM, the RDIMM and the LRDIMM. The first speed interface component adopted by the main board can support high-speed signal transmission, so that the transmission of high-speed signals is facilitated. The invention is suitable for the development of electronic devices or equipment such as a mainboard, a computer, an industrial personal computer, a server and the like, and OEM and chip test scenes.

Description

Mainboard and server

Technical Field

The invention relates to the technical field of computers, in particular to a mainboard and a server.

Background

The main board, also called main board (main board), system board (system board) or motherboard (motherboard), is an important component of the computer, and determines the functions and performance characteristics of the computer system.

At present, motherboards in the market are usually designed according to the requirements of specific application systems, and the IO (Input/Output) signal transmission rate of some motherboards is limited by the type of IO (Input/Output) interfaces (mainly referring to the type of adopted communication standard), which is not convenient for realizing the transmission of high-speed signals.

Disclosure of Invention

In view of this, embodiments of the present invention provide a motherboard and a server, which are convenient for implementing transmission of high-speed signals.

In order to achieve the purpose of the invention, the following technical scheme is adopted:

in a first aspect, the motherboard provided in the embodiments of the present invention includes a printed circuit board, where a processor socket, a memory slot, and a first speed interface component are disposed on the printed circuit board, the processor socket is used to mount a processor, and the first speed interface component includes a plurality of PCIE slots, an OCP connector, an SATA connector, and an m.2 connector;

the processor socket is respectively and electrically connected with the plurality of memory slots, the PCIE slot, the OCP connector, the SATA connector and the M.2 connector, and each memory slot supports installation of any one of the UDIMM, the RDIMM and the LRDIMM.

Optionally, the processor socket is configured to mount a processor, and support 8 channel memory slots, where the memory slot of each channel supports mounting two memory modules.

Optionally, the PCIE slot includes a first PCIE slot, a second PCIE slot, a third PCIE slot, a fourth PCIE slot, and a fifth PCIE slot, the first PCIE slot is connected to a first input/output interface on the processor socket corresponding to the first group of signal paths of the processor, the second PCIE slot is connected to a second input/output interface on the processor socket corresponding to the second group of signal paths of the processor, the third PCIE slot is connected to a third input/output interface on the processor socket corresponding to the third group of signal paths of the processor, the fourth PCIE slot is connected to a fourth input/output interface on the processor socket corresponding to the fourth group of signal paths of the processor, and the fifth PCIE slot is connected to a fifth input/output interface on the processor socket corresponding to the fifth group of signal paths of the processor;

the first PCIE slot at least supports a PCIE standard card x8/x4/x2/x1, and the second PCIE slot, the third PCIE slot, the fourth PCIE slot, and the fifth PCIE slot respectively support a PCIE standard card x16/x8/x4/x2/x 1.

Optionally, the seventh set of signal paths includes at least 6 paths, and the SATA connector includes:

the MiniSAS HD connectors are provided with 4 groups or 6 groups, each group is provided with 4 SATA interfaces, and at least two groups of MiniSAS HD connectors are connected with the sixth input/output interface through the first signal switcher;

7-pin SATA interface; the 7-pin SATA interface is provided with 2 groups which are respectively connected with the seventh input/output interface and are used for being connected with 2 paths in a seventh group of signal paths;

and the optical disk connector of the SATA interface supports connection with an optical disk drive or a solid state disk.

Optionally, the processor socket has a seventh input/output interface corresponding to a seventh group of signal paths of the processor, where the seventh group of signal paths includes at least 5 paths, and 5 paths transmitted by the seventh input/output interface are connected to the m.2 connector through a second signal switcher, where 4 paths are configured to be PCIE signals, 1 path is configured to be SATA signals, and the second signal switcher is configured to switch between one path of the 4 paths of PCIE signals and the 1 path of SATA signals.

Optionally, a substrate management controller and a second speed interface component are further disposed on the printed circuit board, a signal transmission rate of the second speed interface component is less than a transmission rate of the first speed interface component, one end of the substrate management controller is electrically connected to the processor mounting base through a printed circuit, and the other end of the substrate management controller is electrically connected to the second speed interface component, so that the motherboard supports remote task management.

Optionally, the second rate interface component includes a UART interface, a JTAG interface, an SPI interface, an LPC interface, an I2C interface, and an APML interface.

In a second aspect, an embodiment of the present invention provides a server, including the motherboard according to any one of the first aspects, wherein a processor is installed in a processor socket on the motherboard.

According to the mainboard and the server provided by the embodiment of the invention, the structure is improved, a processor socket, a memory slot and a first speed interface component are arranged on the printed circuit board, the processor socket is used for installing a processor, and the first speed interface component comprises a plurality of PCIE slots, an OCP connector, an SATA connector and an M.2 connector; the processor socket is respectively and electrically connected with the plurality of memory slots, the PCIE slot, the OCP connector, the SATA connector and the M.2 connector, and each memory slot supports installation of any one of the UDIMM, the RDIMM and the LRDIMM. Because the first speed interface components adopted by the mainboard, such as a PCIE slot, a SATA connector, and the like, have a higher bandwidth, they can support high-speed signal transmission. In addition, multiple (i.e., commonly referred to as multi-channel) memory sockets, such as any of the UDIMM, RDIMM, and LRDIMM, may be employed to support higher frequency memory modules. In conclusion, the mainboard formed by the hardware and the topological structure thereof is convenient for realizing the transmission of high-speed signals.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic block diagram of a motherboard according to an embodiment of the present invention;

FIG. 2 is a schematic block diagram of another embodiment of a motherboard according to the present invention;

FIG. 3 is a block diagram of an embodiment of a CPU supported by a motherboard according to the present invention;

FIG. 4 is a schematic block diagram of another embodiment of a motherboard according to the present invention;

FIG. 5 is a schematic block diagram of another embodiment of a motherboard according to the present invention;

FIGS. 6 to 8 are schematic block diagrams of the structure of an embodiment of the main board with JTAG interface function circuit of the present invention;

FIG. 9 is a schematic block diagram of an embodiment of a circuit having an SPI interface function on a motherboard according to the present invention;

FIG. 10 is a schematic block diagram illustrating a functional circuit of a motherboard having a BMC according to an embodiment of the invention;

FIG. 11 is a schematic diagram of a circuit for remotely implementing the power-on, power-off, and power-on of a motherboard via a BMC port;

FIG. 12 is a block diagram of a motherboard with a temperature control system interface function according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be apparent that numerous technical details are set forth in the following specific examples in order to provide a more thorough description of the present invention, and it should be apparent to one skilled in the art that the present invention may be practiced without some of these details. In addition, some methods, means, components and applications thereof known to those skilled in the art are not described in detail in order to highlight the gist of the present invention, but the implementation of the present invention is not affected. The embodiments described herein are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 is a block diagram of a motherboard according to an embodiment of the present invention; referring to fig. 1, a motherboard (main board), generally called a system board (system board) or a motherboard (motherboard), according to an embodiment of the present invention is provided; the device is suitable for various electronic devices such as personal computers, industrial personal computers and servers. The motherboard comprises a Printed circuit board (Printed circuit boards), commonly known as a PCB; the printed circuit board is provided with a Processor Socket for mounting a Processor (CPU), which is also called a Processor Socket and mainly includes a Socket and a Slot.

In one embodiment, the CPU is a processor of the hakuri 7100 or hakuri 7200 series, which is attached to an X86 CPU, and 1 SP 34094 package Socket is designed on a printed circuit board of a motherboard for mounting a hakuri 7100/7200 CPU; the Hai Guang 7100/7200 CPU chip is a high-performance chip with rich IO interfaces, wherein a part of pins are function configurable interfaces.

A memory slot; referring to fig. 3, the glad 7100/7200 CPU supports 8 channels of memory slots (DDR channels in english), and as shown in fig. 2, the channels are respectively identified as: A. b, C, D, E, F, G and H, each Channel memory slot supports 2 dual In-line memory modules (DIMMs) and supports 16 DDR4-2667 rate UDIMM/RDIMM/LRDIMMs.

A first rate interface component; it includes several PCIE (peripheral component interconnect Express, which is a high speed serial computer expansion bus standard) slots, OCP connector, SATA connector and M.2 connector.

The OCP connector supports OCP card, the SATA connector supports standard SATA hard disk, and the M.2 connector supports M.2SSD. Here, PCIE, OCP, SATA and m.2 are terms in the field of communications technology, and can be simply understood as a communication transmission standard of an interface.

The structure of the mainboard provided by the embodiment of the invention is improved, and the first speed interface components adopted by the mainboard, such as PCIE slots, SATA connectors and the like, have higher bandwidth, so that the mainboard can support high-speed signal transmission. In addition, multiple (i.e., commonly referred to as multi-channel) memory sockets, such as any of the UDIMM, RDIMM, and LRDIMM, may be employed to support higher frequency memory modules. In conclusion, the mainboard formed by the hardware and the topological structure thereof is convenient for realizing the transmission of high-speed signals.

The PCIE slot is used for connecting PCIE equipment; in some embodiments, the PCIE slots include a first PCIE Slot, a second PCIE Slot, a third PCIE Slot, a fourth PCIE Slot, and a fifth PCIE Slot, and correspond to the slots 0/1/2/3/4 of the 5 PCIE x16 in sequence in fig. 1 and fig. 2. The first PCIE slot is connected to a processor socket and a first set of signal paths (Lane) G3[ 15: 8] and the second PCIE slot is connected to the processor socket and connected to a second group of signal paths P2[ 15: 0], the third PCIE slot is connected to the processor socket and connected to a third set of signal paths P3[ 15: 0] and a fourth PCIE slot is connected to the processor socket and connected to a fourth set of signal paths G0[ 15: 0] and a fifth PCIE slot is connected to the processor socket and connected to a fifth group of signal paths G1[ 15: 0] corresponding fifth input/output interface.

As shown in fig. 2, Slot 0: for x8 PCIE connectors, CPU connected G3[ 15: 8] signal, of course, Slot0 may also optionally support x 16. Slot 1-2: are all x16 PCIE connectors, and are respectively connected with P2/P3[ 15: 0] signal; slot 3: support x16 PCIE signals, CPU connected G0[ 15: 0] signal; slot 4: support x16 PCIE signals, CPU connected G1[ 15: 0] signal.

The x16, x8, x4, x2 and x1 respectively represent the number of transmission channels (i.e. the aforementioned channels, Lane), for example, x16 represents 16 channels.

In this embodiment, the PCIE slots are PCIE 3.0 slots, and five slots are provided, where 3 slots are Vertical slots (Vertical slots), 1 Slot is a cross Slot (Straddle Slot), and the other 1 Slot is a Right Angle Slot (Right Angle Slot).

The PCIE Slot can be arranged at different positions on the PCB board according to the actual application requirement to selectively support the built-in card or the rear I/O card, and also can support the design of a horizontal card or a vertical card. The Slot-4 can support a PCIE standard card x16/x8/x4/x2/x1, can support 1 PCIE x16 or 2 x8 slots or 1 x8+2 x4 PCIE slots by inserting different adapter boards, can support a PCIE standard card x8/x4/x2/x1 by inserting the Slot0, and can support 2 x4 PCIE slots by inserting different adapter boards.

In this embodiment, a central processing unit installation position is reserved for the motherboard when the motherboard leaves the factory, and a specific installation position may be provided with the processor socket, or a processor welding point may be provided at the installation position, so that manufacturers or users such as OEMs and servers can select and match the motherboard by themselves.

With continued reference to fig. 1, in some embodiments, the OCP Connector (Connector) has a first interface, a second interface and a third interface, and the OCP Connector with these three interfaces is commonly referred to as Connector a + B + C, where the first interface corresponds to the a interface, the second interface corresponds to the B interface, and the third interface corresponds to the C interface. The processor socket is provided with a sixth input/output interface corresponding to a sixth group of signal paths of the processor, the sixth group of signal paths comprises 16 paths, and the sixth input/output interface transmits an 8-path P1[ 15: 8] is connected to a first interface for configuring another 8-way P1[ 7: 0] is connected with a first signal switcher (not shown), the output end of the first signal switcher is respectively connected with the second interface and the M.2 connector, and the second interface is used for being configured into SATA protocol or is used for being configured into 16-path PCIE protocol together with the first interface.

The processor socket is provided with a seventh input/output interface corresponding to a seventh group of signal paths of the processor, the seventh group of signal paths at least comprises 4 paths, and 4 paths of the seventh input/output interface transmit P0[ 7: 4] is connected with a third interface, and the third interface is used for configuring a KR protocol.

With continued reference to FIG. 2, in another embodiment, the SATA connector comprises: the MiniSAS HD connector is provided with 4 groups or 6 groups, each group is provided with 4 SATA interfaces, and 16 groups or 24 groups of SATA interfaces are provided; wherein, at least two groups of MiniSAS HD connectors are connected with the sixth input/output interface through the first signal switcher; that is, the first signal switch switches the signals of P1[ 7: 0] the connected connectors are switched to make the SATA signal select to be connected to two sets of MiniSAS HD 6-7 or the second interface of the OCP connector.

The Mini-SAS HD (High reliability) connector is a new generation SAS interface, meets the channel bandwidth requirements of 6Gb/s to 12Gb/s and 14Gb/s, and meets or exceeds the SAS 2.1 specification and the SAS 3.0 recommended execution specification. The Mini-SAS HD product has a higher port density than the existing Mini-SAS 2.0 product.

When the MiniSAS HD 6-7 and OCP B connector are selectively connected, when P1[ 7: 0] when SATA devices are connected, i.e., 24 sets of SATA interfaces are supported, when P1[ 7: 0] when the second interface of the OCP connector is connected, 16 groups of SATA signals are supported.

In particular, the signal switching between the MiniSAS HD connector and the OCP connector may be intelligently switched by a signal switcher, such as a Multiplexer (MUX); p1[ 7: 0 manual selection is performed by selecting a mode of sharing the components (Co-layout) on the main board, so that the cost and the wiring space of the PCB can be saved.

7-pin SATA interface; the 7-pin SATA interface is provided with 2 groups, which are respectively connected to the seventh input/output interface, and the seventh group of signal paths at least includes 6 paths, where 4 paths P0[ 7: and 4, besides the connection with the third interface of the OCP connector, the other 2 paths of P0[3] and P0[2] are respectively connected with the 2 groups of 7-pin SATA interfaces in a one-to-one correspondence mode.

And an optical disk connector of the SATA interface, which supports connection of an Optical Disk Drive (ODD) or a solid state Disk (DOM). The solid state disk is a DOM of the SATA interface.

Referring to fig. 4, in some embodiments, the processor socket has a seventh input/output interface thereon corresponding to a seventh set of signal paths of the processor, the seventh set of signal paths including at least 5 paths, and 5 paths of the seventh input/output interface are connected to the m.2 connector through a second signal switch, wherein 4 paths P0[ 11: 8] is used for configuring PCIE signals and can support PCIE M.2 discs; the 1 path is used for configuring SATA signals, and the second signal switcher is used for switching between P0[8] and 1 path P0[1] SATA signals in 4 paths of PCIE signals. The method specifically comprises the following steps: when the SEL pin is at high level, the pin A and pin C of the second signal switcher are communicated, the signal is switched to LanEP0[8 ]; when the SEL pin is low, pin A and pin B of the second signal switch are connected, and the signal is switched to Lane P0[1 ].

With continued reference to fig. 4, specifically, the second signal switch is a MUX chip, the 1P 0[1] SATA signal is connected to the Lane0 port of the m.2 connector, the SEL PIN (level signal PIN) of the second signal switch is provided with a pull-up resistor, when PCIE m.2 is inserted, since 69PIN on m.2 is NC (indicating that the connection terminal is floating, which indicates in the digital logic circuit that the PIN is not connected with any signal and is neither connected with high level nor connected with low level), under the action of the pull-up resistor, SEL is at high level, the PCIE signal is connected to the m.2 connector through MUX, when SATA m.2 is inserted, since 69PIN on m.2 hard disk is grounded, SEL is pulled down by 69PIN on m.2 hard disk, SATA signal is connected to m.2 connector through MUX, thereby implementing automatic identification connection between PCIE and SATA m.2.

In addition to the occasion of high-speed communication, the motherboard needs to adapt to the occasion of low-speed communication, for example, in a debugging scene, the motherboard needs to have some interfaces for low-speed communication, so as to facilitate debugging and remote monitoring management. Therefore, referring to fig. 4, in some embodiments, a board management controller and a second rate interface component are further disposed on the printed circuit board, a signal transmission rate of the second rate interface component is lower than a signal transmission rate of the first rate interface component, one end of the board management controller is electrically connected to the processor mounting base through a printed circuit, and the other end of the board management controller is electrically connected to the second rate interface component, so that the motherboard supports remote task management.

Wherein, remote task management includes: debugging, burning and updating BIOS, starting and shutting down the mainboard, and adjusting the CPU heat dissipation strategy.

The second rate interface component comprises UART (Universal Asynchronous Receiver/Transmitter) interface, JTAG (Joint Test Action group) interface, SPI (Serial Peripheral interface) interface, LPC (Low pin count) interface, I2C (Inter-Integrated Circuit) interface and APML (advanced Platform Management Link) interface.

Referring to fig. 5, a UART interface functional circuit topology is shown, in which after a CPU is inserted into a processor socket, the CPU is connected to a Baseboard Management Controller (BMC) through a UART interface, a first pin connector (Header)1 and a second pin connector Header 2 are disposed on a motherboard, a node between the CPU and the BMC is connected to the first pin connector Header1 through a cable, and the second pin connector Header 2 is connected to the BMC through an RS232 interface. The interface function circuit can realize a Local (Local) UART debugging mode.

In other embodiments, the BMC is provided with a network port, and the network port and the BMC may implement a sol (serial over lan) debugging function, that is, the network port is used to remotely connect, log in, and view debugging information, specifically: after the serial port information of the CPU is sent to the BMC, the SOL function is realized through BMC firmware, and the serial port information of the CPU can be seen when a web page of the BMC is logged in and an SOL interface is opened, so that the function of remote debugging is realized.

Referring to fig. 6 to 8, a circuit topology with JTAG interface function is shown, which can implement local JTAG debugging or remote JTAG debugging through BMC, and the JTAG interface generally has three types, i.e., 10pin, 14pin, and 20 pin.

In addition, the BMC may also burn a Complex Programmable Logic Device (CPLD) program, which is hereinafter referred to as CPLD program for convenience of description. HDT (Hygon Debug tool) is local JTAG debugger. Referring to fig. 6, the implementation principle is as follows: TCK (test Clock input)/TMS (test Mode Selection input) signals of the BMC pass through a switching chip Switch with a selector Switch and can be divided into two paths, wherein one path is connected to the CPLD and a Header3 of the third pin connector; here, the Header3 is a JTAG recording Header of the CPLD, the JTAG recording Header3 has VCC (power supply)/tdo (test Data Output)/tdi (test Data input)/TMS (test Mode Selection input)/GND (power ground)/TCK signal), the other path is connected to the CPU through a transmission gate with a control end OE (Output Enable, generally, an Output Enable signal), and the TCK/TMS of the HDT is connected to the CPU through a transmission gate with a control end. Both the HDT and the BMC can be used as debuggers to debug the CPU, so that enabling control ends HDT _ OE and BMC _ OE of the two debuggers are reversed to ensure that only one debugging is started at the same time, namely either the HDT or the TCK/TMS of the BMC is connected with the CPU, wherein OE is controlled by the BMC. Referring to fig. 7, trst (test Reset input)/DBREQ signals of HDT and BMC are respectively interconnected via a transmission gate with a control terminal OE followed by a CPU, and an inverter is added between HDT _ OE and BMC _ OE signals of the two transmission gates to ensure that the two transmission gates are not opened simultaneously and OE is controlled by BMC. Fig. 8 illustrates the switching control principle of TDI and TDO of HDT and BMC, which can be referred to as the above-mentioned switching principle of TCK/TMS signals, and thus is not described again.

Referring to fig. 9, a functional circuit topology with an SPI interface is shown, an SPI0(DI/DO/HOLD _ L/WP _ L/CS0) interface of the CPU and the BMC is switched by a MUX chip, a MUX path selects the CPU connection by default, after the motherboard is powered on and started, the CPU reads firmware information from a BIOS ROM to initialize the motherboard, and when the motherboard CPU does not need to start the BIOS, the BMC can control the MUX to switch the SPI path to the BMC connection through a GPIO (general-purpose input/output, which means a general i/o port in chinese), so as to remotely burn the BIOS ROM. And after the BMC burning is finished, controlling the GPIO to switch the BIOS ROM to be connected to the CPU. After the mainboard is restarted, the CPU starts the mainboard from the BIOS ROM, so that the function of remotely burning the BIOS by the BMC is realized. Meanwhile, the SPI1(DI/DO/HOLD _ L/WP _ L/CS1) interface of the CPU is connected with the TCM/TPM module, so that the mainboard supports the function of the security module.

Referring to fig. 10, a functional circuit topology with a BMC is shown, where a ASPEED AST2500 BMC chip is used as a management system for a motherboard to perform startup, shutdown, and restart control, firmware burning, and monitoring of system errors, alarms, temperature, voltage, etc., and the BMC may receive external control commands through a network. The AST2500 is connected with the CPU, and the periphery of the AST2500 is also connected with other control circuits including a fan, a memory card, a key, a UART interface, a network card chip, and the like, as shown in fig. 10.

As shown in fig. 11, the PWR BTN and RST BTN signals of the CPU are controlled by the BMC network to power on, power off, and Reset control of the motherboard.

It can be understood that the CPU will generate heat during operation, and in order to monitor and control the temperature of the CPU, a tube temperature control system interface is further provided on the motherboard. As shown in fig. 12, the specific working principle is as follows: the CPU connects temperature signals related to temperature, such as Thermaltpip (the Thermaltpip is a pin of the CPU, when the temperature of the chip reaches a set value, the chip can pull down the pin, after the external circuit monitors that the pin is pulled down, the power supply on the main board is cut off to achieve protection) and Tdie (core temperature) and Tmin (core temperature) transmitted by the AMPL interface and the temperature of Tmin (the Tdie is a temperature sensing diode in the chip and used for sensing the temperature in the chip) transmitted by the AMPL interface to a fourth pin connector Header4, a fifth pin connector Header5 and a BMC (baseboard management controller) respectively, and a temperature control module or the BMC of the test system senses the temperature signals, so that a heat dissipation module of the CPU is controlled to adjust according to different strategies.

As can be seen from the above description, the motherboard provided in the embodiment of the present invention employs the CPLD to perform power-on and power-off control on the power regulator (VR), and the power-on and power-off timings of the power regulator VR (voltage regulator) and the signal input to the CPU can be flexibly adjusted by the logic code, and the remote BMC management system is supported to perform remote control, debugging and monitoring on the motherboard, so that the manageability of the entire system of the motherboard can be improved.

The invention is suitable for the development of electronic devices or equipment such as a mainboard, a computer, an industrial personal computer, a server and the like, and OEM and chip test scenes.

In addition, an embodiment of the present invention further provides a server, including a chassis, in which the motherboard according to any one of the foregoing embodiments is disposed, a processor is installed in a central processing unit socket on the motherboard, and the processor is electrically connected to an input end of the signal switch.

Wherein, the processor is a central processing unit. Specifically, the processor is a sea light processor, the models are 7100 and 7200, and the processor supports a multi-channel memory.

The performance of the server of the embodiment can be optimized to a certain extent due to the convenience in realizing the transmission of high-speed signals.

It is noted that, herein, the terms "upper", "lower", and the like, indicate orientations or positional relationships and are used for convenience in describing the present invention and for simplicity in description, but do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; may be directly connected or indirectly connected through an intermediate. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group of processes, methods, articles, or devices that include the element. As will be appreciated by one of ordinary skill in the art, the situation may be specified.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A mainboard is characterized by comprising a printed circuit board, wherein a processor socket, a memory slot and a first speed interface component are arranged on the printed circuit board, the processor socket is used for installing a processor, and the first speed interface component comprises a plurality of PCIE slots, an OCP connector, an SATA connector and an M.2 connector;

2. The motherboard of claim 1 wherein the processor socket is configured to mount a processor and supports 8 channel memory slots, each channel memory slot supporting two memory modules.

3. The motherboard of claim 1 or 2 wherein the PCIE slots include a first PCIE slot, a second PCIE slot, a third PCIE slot, a fourth PCIE slot and a fifth PCIE slot, the first PCIE slot is connected with a first input/output interface which is arranged on the processor socket and corresponds to a first group of signal paths of the processor, the second PCIE slot is connected with a second input/output interface which is arranged on the processor socket and corresponds to a second group of signal paths of the processor, the third PCIE slot is connected with a third input/output interface which is arranged on the processor socket and corresponds to a third group of signal paths of the processor, the fourth PCIE slot is connected with a fourth input/output interface which is arranged on the processor socket and corresponds to a fourth group of signal paths of the processor, the fifth PCIE slot is connected with a fifth input/output interface which is arranged on the processor socket and corresponds to a fifth group of signal paths of the processor;

4. The motherboard of claim 1, wherein the OCP connector has a first interface, a second interface, and a third interface, the processor socket has a sixth input/output interface corresponding to a sixth set of signal paths of the processor, the sixth set of signal paths includes 16 paths, one 8 paths of the sixth input/output interface transmission are connected to the first interface, the first interface is configured to be a PCIE protocol, the other 8 paths of the transmission are connected to the first signal switcher, the output end of the first signal switcher is respectively connected to the second interface and the m.2 connector, the second interface is configured to be a SATA protocol or configured to be a 16-path PCIE protocol together with the first interface;

the processor socket is provided with a seventh input/output interface corresponding to a seventh group of signal paths of the processor, the seventh group of signal paths at least comprises 4 paths, 4 paths of the seventh input/output interface are connected with a third interface, and the third interface is used for being configured into a KR protocol.

5. The motherboard of claim 4, wherein the seventh set of signal paths comprises at least 6 paths, and the SATA connector comprises:

6. The motherboard of claim 1 wherein the processor socket has a seventh input/output interface corresponding to a seventh set of signal paths of the processor, the seventh set of signal paths including at least 5 paths, and 5 of the paths transmitted by the seventh input/output interface are connected to the m.2 connector through a second signal switch, wherein 4 paths are configured as PCIE signals, 1 path is configured as SATA signals, and the second signal switch is configured to switch between one path of the 4 paths of PCIE signals and 1 path of SATA signals.

7. The motherboard of claim 1 further comprising a board management controller and a second rate interface module, wherein the second rate interface module has a signal transmission rate less than that of the first rate interface module, and one end of the board management controller is electrically connected to the processor mounting socket via a printed circuit and the other end of the board management controller is electrically connected to the second rate interface module for enabling the motherboard to support remote task management.

8. The host board of claim 7, wherein the second rate interface component includes a UART interface, a JTAG interface, an SPI interface, an LPC interface, an I2C interface, and an APML interface.

9. A server comprising a housing, a motherboard according to any one of claims 1 to 8 disposed in the housing, and a processor mounted in a processor socket on the motherboard.