CN115509985A

CN115509985A - I/O controller of processor

Info

Publication number: CN115509985A
Application number: CN202211212452.7A
Authority: CN
Inventors: 义日贵; 白秀杨
Original assignee: Inspur Power Commercial Systems Co Ltd
Current assignee: Inspur Power Commercial Systems Co Ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2022-12-23

Abstract

The application discloses an I/O controller of a processor, which is applied to the technical field of servers. An upstream port of the PCIe Switch IP is connected to the processor through a pin of the FPGA so as to be convenient for communicating with the processor; the PCIe Switch IP is also connected with an internal interconnection bus of the FPGA; the internal interconnection bus also connects the remaining hardware devices to facilitate communication between each hardware device and the processor. The application provides compatible and higher I/O controller and system that integrates based on FPGA and the available IP core of FPGA, through PCIe Switch IP realize with the communication between the treater, replace original I/O controller chip with the IP core, simplified the I/O controller that is used for the I/O interface of extended processor, the circuit is simple, it is little to occupy the mainboard area, mainboard design is simple.

Description

I/O controller of processor

Technical Field

The present application relates to the field of server technologies, and in particular, to an I/O controller for a processor.

Background

The processor may provide a limited number and type of Input/Output (I/O) interfaces, and a general processor may provide a PCIe interface with a limited number of lanes. While the server often needs to support devices such as Serial Advanced Technology Attachment hard Disk (SATA hard Disk), nonvolatile memory host controller interface specification (NVM Express, NVMe) solid state Disk, universal Serial Bus (USB) storage medium, gigabit network interface, gigabit ethernet card, video card, and RAID (Redundant array of Independent Disks) card, all of which cannot be directly connected to the processor. Each device needs to be extended by a separate I/O controller, such as: a SATA controller is required to support SATA disks, a USB controller is required to support USB disks, a gigabit ethernet controller is required to support gigabit ethernet, and the like. These I/O controllers all need to be connected to the processor through a PCIe bus.

Because the PCIe channel of the processor is very limited, the processor may also be connected to high-speed devices such as a Graphics Processing Unit (GPU) and a 100G network card, and thus, in the current scheme, the number of I/O controller chips on the motherboard is large, peripheral circuits of the I/O controller are complex, the area of the motherboard occupied is large, and the design of a Printed Circuit Board (PCB) is relatively complex.

Therefore, how to simplify an I/O controller for extending an I/O interface of a processor is an urgent problem to be solved by those skilled in the art.

Disclosure of Invention

An object of the present application is to provide an I/O controller of a processor to simplify the structure of the I/O controller itself.

To solve the above technical problem, the present application provides an I/O controller of a processor, including: an FPGA with an IP core; the IP core at least comprises: PCIe Switch IP;

the PCIe Switch IP uplink port is connected to the processor PCIe downlink port through the FPGA pin, so that the PCIe Switch IP and the processor can communicate conveniently;

the PCIe Switch IP is also connected with an internal interconnection bus of the FPGA, and the internal interconnection bus is connected with other hardware equipment except the PCIe Switch IP so as to facilitate the communication between the other hardware equipment and the processor; wherein the hardware device comprises the IP core.

Preferably, the IP core in the hardware device further includes: SATA controller IP; and the SATA controller IP is connected with the internal interconnection bus and is used for connecting SATA equipment.

Preferably, the IP core in the hardware device further includes: gigabit Ethernet IP; the gigabit Ethernet IP is connected with the internal interconnection bus, and the gigabit Ethernet IP is used for connecting the gigabit Ethernet PHY chip.

Preferably, the IP core in the hardware device further includes: USB IP; the USB IP is connected with the internal interconnection bus and is used for connecting a USB PHY chip.

Preferably, the hardware device further comprises: a logic control module; and the logic control module is connected with the internal interconnection bus.

Preferably, the hardware device further comprises: an SPI interface; and the SPI interface is connected with the internal interconnection bus.

Preferably, the downstream port of the PCIe Switch IP is connected to the GTx pin of the FPGA, and is used to connect downstream PCIe devices.

Preferably, the model of the FPGA is selected according to the type and/or amount of hardware on the FPGA.

Preferably, the model of the FPGA is selected according to hardware parameters and a hardware quantity corresponding to a hardware type on the FPGA, and the hardware parameters include: number of LUTs, BRAM, GTx.

Preferably, the PCIe Switch IP upstream port is connected to the PCIe downstream port of the processor through the GTx pin of the FPGA.

The I/O controller of the processor is specifically an FPGA provided with an IP core; the IP core at least comprises: PCIe Switch IP; the PCIe Switch IP uplink port is connected to the processor PCIe downlink port through the FPGA pin, so that the PCIe Switch IP and the processor can communicate conveniently; the PCIe Switch IP is also connected with an internal interconnection bus of the FPGA; the internal interconnection bus is connected with other hardware devices except the PCIe Switch IP, so that the other hardware devices can communicate with the processor conveniently. Aiming at the problems that the design of mainboard hardware is complex, a plurality of controllers or I/O expansion bridge chips are required to be used for limiting functions and different platforms are incompatible when I/O of an expansion processor is carried out in the current scheme, the application provides an integrated I/O controller and a system which are high in compatibility and integration degree and based on an FPGA and an available IP core of the FPGA.

Drawings

In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.

Fig. 1 is a block diagram of an I/O controller according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.

The core of the application is to provide an I/O controller of a processor to simplify the structure of the I/O controller itself.

In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.

Besides a processor with high computing performance and a memory with high storage bandwidth, a server mainboard needs to have rich I/O resources, and can meet the use requirements of different users only by supporting I/O interfaces of different types. However, the processor has limited external interface resources and cannot support all interface types, and in this case, it is often necessary to extend the I/O interface by means of various dedicated I/O controller chips. Therefore, a plurality of I/O controller chips are often required to be designed on one motherboard to meet user requirements, which results in complex hardware design and occupies a lot of board card space, and each I/O controller chip requires a peripheral flash chip and other nonvolatile memories to store configuration information, thus involving more firmware and having complex board card firmware upgrade maintenance steps. Some processor platforms have a dedicated I/O bridge, but only one processor platform, which is less flexible and has some design deficiencies. In order to solve the above problem, the present application provides an I/O controller for a processor, which improves the integration level of a common I/O interface of an extended server, and improves the flexibility and application scenario of the integrated I/O controller.

Intellectual Property cores (IP cores), also called Intellectual Property modules, design some of the functional blocks that are commonly used in digital circuits, but are more complex, into modules that can modify parameters. The electronic system is designed by using the IP core, so that the reference is convenient, and the functions of the basic elements are easy to modify. The Field Programmable Gate Array (FPGA) is a product of further development on the basis of Programmable devices such as Programmable Array logic, general Array logic and the like, and appears as a semi-custom circuit in the Field of application-specific integrated circuits, thereby not only solving the defects of the custom circuit, but also overcoming the defect of limited Gate circuits of the original Programmable devices. The number of Look-Up Table units (Look Up tables, LUTs), block Random Access Memory (BRAM), and Gigabit transceivers (GTx) affects the model selection of the FPGA of the present application. The low-speed I/O controller chips or IPs such as SATA, USB, gigabit Ethernet and the like cannot be directly connected to the processor, but are connected to a PCIe Switch IP, and the PCIe Switch IP is connected to a PCIe interface of the processor. PCIe Switch can expand the number of PCIe lanes, and besides being able to connect controllers such as USB, SATA and gigabit ethernet, it can also support standard PCIe devices, such as: NVMe SSD, RAID cards, terabyte network cards, video cards, and the like.

The embodiment of the application provides an I/O controller of a processor, which comprises an FPGA provided with an IP core; the IP core at least comprises: PCIe Switch IP; the PCIe Switch IP uplink port is connected to the processor PCIe downlink port through the FPGA pin, so that the PCIe Switch IP and the processor can communicate conveniently; the PCIe Switch IP is also connected with an internal interconnection bus of the FPGA, and the internal interconnection bus is connected with other hardware equipment except the PCIe Switch IP so as to facilitate the communication between the other hardware equipment and the processor; wherein the hardware device comprises an IP core.

According to the embodiment of the application, the multi-interface I/O controller and the system based on the FPGA are realized by utilizing rich IP resources and logic resources in the FPGA and combining the existing IP core and redesigned architecture. In this embodiment, PCIe Switch IP is used to implement PCIe bus expansion, an uplink port of PCIe Switch IP is connected to a PCIe downlink port of the processor through a GTx pin of the FPGA, and PCIe Gen4 x16 interconnection bandwidth is implemented between the FPGA and the processor. The downstream port of the PCIe Switch IP is connected to a GTx pin of the FPGA, and may be connected to downstream PCIe devices such as an NVMe Solid State Disk (SSD), a RAID card, a 10G network card, a Baseboard Management Controller (BMC card), and a video card through a motherboard according to an actual application requirement. The downlink PCIe channel can support 1 PCIe Gen4 x16, and can be split into 2 x8 or 4 x4 or 8 x2 or 16 x1 according to requirements. In addition, the PCIe Switch IP is further connected to an internal interconnection bus of the FPGA, and is configured to load configuration of the PCIe Switch IP itself and provide an uplink channel for other hardware devices, so as to meet a requirement that an IP core corresponding to a device such as an SATA, a USB, a network, and the like communicates with the processor through the PCIe Switch IP and the uplink PCIe channel. The IP core in the hardware device according to the embodiment of the present application may include a USB IP, where the USB IP is connected to the internal interconnection bus, and the USB IP is used to connect to the USB PHY chip to provide a USB interface to the processor. The hardware device may further include a Serial Peripheral Interface (SPI) and a logic control module. It should be noted that the scheme provided in the embodiment of the present application is only one of the schemes in the present application, and does not limit other schemes in the present application.

Fig. 1 is a block diagram of an I/O controller according to an embodiment of the present disclosure; as shown in fig. 1, the system comprises a processor 1 and an FPGA2, the PCIe Switch IP is used to implement the extension of the PCIe bus, an upstream port of the PCIe Switch IP is connected to a PCIe downstream port of the processor 1 through a GTx pin of the FPGA2, and an interconnection bandwidth of PCIe Gen4 x16 is implemented between the FPGA2 and the processor 1. The FPGA2 is integrated with a PCIe Switch IP, an SATA controller IP, a gigabit Ethernet IP, a USB IP, a logic control module and an SPI interface; the downstream port of the PCIe Switch IP is connected to the GTx pin of the FPGA2, and can be connected to downstream PCIe devices such as an NVMe SSD, an RAID card, a 10G network card, a BMC card and a display card through a mainboard according to the actual application requirement. The SATA controller IP may specifically provide a downstream SATA3.0 interface, and is connected to a motherboard through a GTx pin of the FPGA2, and then connected to a SATA device, such as a SATA HDD or a SATA SSD, through the motherboard. The SATA controller IP is also connected to an internal interconnection bus of the FPGA2 and can communicate with the processor 1 through the internal interconnection bus, the PCIe Switch IP and an uplink PCIe bus. The gigabit Ethernet IP realizes the function of a data link layer in an OSI model, provides a downlink RGMII interface, is connected to a mainboard through a network signal pin special for the FPGA2, and is connected with a gigabit Ethernet PHY chip through the mainboard to realize the establishment of a physical layer. The gigabit ethernet IP is also connected to the internal interconnect bus of the FPGA2, and is connected to the processor 1 via the PCIe Switch IP and the upstream PCIe bus. The USB IP is used for connecting the USB PHY chip so as to be accessed to the USB equipment. The logic control module is used for realizing user interaction functions such as power-on/power-off control, temperature/voltage monitoring, key detection/LED control and hot plug control, the logic control module is externally connected with the power-on/power-off control circuit, the temperature/voltage monitoring circuit, the user interaction circuit and the hot plug control circuit, the independent logic control module is moved into an I/O controller of the FPGA2 and is connected to an internal interconnection bus of the FPGA2, the logic control module of the independent FPGA chip needs independent clock input, the logic control module integrated in the I/O controller can use unified clock control on the internal interconnection bus of the FPGA2, and the design of the high-speed synchronous clock is more beneficial to synchronous control of an external hardware circuit. A FLASH memory (FLASH) chip for configuring the FPGA2 is connected to an SPI interface of the FPGA2 through an SPI bus, and the SPI interface is also connected to an internal interconnection bus of the FPGA. The FLASH chip stores all IP core configuration information, pin configuration information and the like of the FPGA, so that the IP of the I/O controller, the logic control module and the like can be loaded and configured from the same FLASH chip, and the configuration chip does not need to be designed independently for each controller.

Aiming at the problems that in the prior art, when the processor I/O is expanded, the design of main board hardware is complex, a plurality of controllers or I/O expansion bridge chips are required to be used, the functions are limited, and different platforms are incompatible, the embodiment of the application provides an integrated I/O controller and a system which are high in compatibility and integration level and based on an FPGA and an available IP of the FPGA. The integrated I/O expansion framework suitable for the server mainboard, which is provided by the embodiment of the application, can support common downlink interfaces such as PCIe, USB, SATA, gigabit Ethernet and the like, and can also support an uplink PCIe interface, and the PCIe interface is a high-speed serial interface which can be commonly used by all processors on the market. Because the hardware logic control function is generally designed by using a single CPLD/FPGA on the mainboard, the functions of the mainboard can be integrated in the I/O controller, so that the integration level of the I/O controller is improved, and the number of chips on the mainboard is further reduced. The logic control module and the PCIe Switch IP can be connected through an internal interconnection bus of the FPGA, and the information synchronization efficiency is improved. The embodiment of the application can also be realized by three key parameters: the quantity of LUTs, BRAM, GTx designs a simple and easy FPGA chip to select the guide to this scheme. According to the embodiment of the application, only one Flash chip can be selected for configuration burning, and the firmware development difficulty and the firmware upgrading maintenance difficulty of the mainboard are reduced. It should be noted that the above solutions are specific examples of the present application, and the present application is not limited to a specific solution, and the model of each device is selected according to the actual situation.

The I/O controller of the processor provided by the embodiment of the application is specifically an FPGA provided with an IP core; the IP core at least comprises: PCIe Switch IP; the PCIe Switch IP uplink port is connected to the processor PCIe downlink port through the FPGA pin, so that the PCIe Switch IP and the processor can communicate conveniently; the PCIe Switch IP is also connected with an internal interconnection bus of the FPGA; the internal interconnection bus is connected with other hardware devices except the PCIe Switch IP, so that the other hardware devices can communicate with the processor conveniently. Aiming at the problems that the design of hardware of a main board is complex, a plurality of controllers or I/O expansion bridge pieces are required to be used for limiting functions and different platforms are incompatible when I/O of an expansion processor is carried out in the current scheme, the embodiment of the application provides an integrated I/O controller and a system which are high in compatibility and integration level and based on an FPGA and an available IP core of the FPGA.

In the solution provided in the embodiment of the present application, the IP core in the hardware device further includes an SATA controller IP; and the SATA controller IP is connected with the internal interconnection bus and is used for connecting SATA equipment. The SATA controller IP may specifically provide a downlink SATA3.0 interface, and is connected to a motherboard through a GTx pin of the FPGA, and then connected to a SATA device, such as a SATA HDD or a SATA SSD, through the motherboard. The SATA controller IP is also connected to the FPGA internal interconnection bus and can communicate with the processor through the internal interconnection bus, the PCIe Switch IP and the uplink PCIe bus. Hard Disk Drive (HDD) is the most basic computer memory

The IP core in the hardware device of the embodiment of the present application further includes: gigabit Ethernet IP; the gigabit Ethernet IP is connected with the internal interconnection bus and is used for connecting the gigabit Ethernet PHY chip. The gigabit Ethernet IP realizes the function of a data link layer in an OSI model, provides a downlink RGMII interface, is connected to a mainboard through a network signal pin special for FPGA, and is connected with a gigabit Ethernet PHY chip through the mainboard to realize the establishment of a physical layer. The gigabit Ethernet IP is also connected to the internal interconnection bus of the FPGA and is connected to the processor through the PCIe Switch IP and the upstream PCIe bus. After the server user installs the operating system, the operating system and the upper software realize the establishment of a transmission layer, a network layer and an application layer.

In the current solution, a special digital integrated Circuit (CPLD) or FPGA chip is required to implement a Logic control module for controlling power on/off, temperature/voltage monitoring, key detection/LED control, hot plug control, and the like. Because hardware circuits such as up/down control, hot plug control, user interaction interfaces such as keys/LED indicator lights and voltage/temperature monitoring on the mainboard generally need a logic control chip to realize specific control functions, and because I/O controllers on the board cards are all special chips, the logic control functions customized by mainboard developers cannot be realized, an independent CPLD/FPGA is needed to realize the control functions. According to the FPGA-based I/O controller, the function of the I/O controller is realized by the FPGA, and a lot of logic resources and low-speed I/O resources are available in the FPGA, so that an independent logic control module is moved into the FPGA-based I/O controller and is hung on an internal interconnection bus of the FPGA. The logic control module of the independent FPGA chip needs independent clock input, the logic control module integrated on the I/O controller can use the unified clock control on the internal interconnection bus of the FPGA, and the design of the high-speed synchronous clock is more beneficial to the synchronous control of an external hardware circuit. Such as: when the PCIe hard disk is subjected to hot plug, hot plug detection, power supply control, LED (Light-Emitting Diode) lamp control and the like are required to be realized by the logic control module, PCIe bus state negotiation and data storage are required to be realized by the PCIe Switch IP, when the logic control module detects the PCIe hot plug prediction, the PCIe Switch IP can be informed more quickly, the PCIe Switch IP can also transmit the PCIe bus state to the logic control module in real time, and the logic control module can finish power supply control at a more accurate time point. Meanwhile, the design of integrating the FPGA on the same FPGA also reduces the design of a single FPGA logic control module.

The FLASH chip for configuring the FPGA is connected to an SPI interface of the FPGA through an SPI bus, and the SPI interface is also connected to an internal interconnection bus of the FPGA. The FLASH chip stores all IP core configuration information, pin configuration information and the like of the FPGA, so that the IP of the I/O controller, the logic control module and the like can be loaded and configured from the same FLASH chip, and the configuration chip does not need to be designed independently for each controller.

It is also important to select a proper FPGA chip when designing the highly integrated I/O controller based on the FPGA using the techniques of the above embodiments, the FPGA of too low end may have insufficient resources and insufficient high speed I/O, whereas the FPGA of too high end may have high price and large occupied area. The embodiment of the application provides a specific scheme, and the model of the FPGA is selected according to the type and/or the quantity of hardware on the FPGA. Specifically, the hardware parameters are selected according to hardware parameters and the number of hardware corresponding to the hardware type on the FPGA, and the hardware parameters include: number of LUTs, BRAM, GTx. For example, if an Xilinx FPGA and its supported IP core resources are used, an XpressSWITCH hard core PCIe Switch (occupying less LUT resources), a Design Gateway SATA3.0 IP (capable of supporting RAID function of SATA controller group), a Coriin USB3.1 IP and a soft core GbE IP are selected. Table 1 lists the resource lists required for the above specific scheme.

TABLE 1 resource List

The FPGA needs to meet the requirement that the number of LUT resources is more than 557000, the number of BRAMs is more than 1026, namely each BRAM is 36Kb, the capacity of the BRAM needs to be more than 1026 × 36/1024=36Mb, the number of GTx I/O is more than 36 pairs, and the FPGA which can meet the above conditions can select the Xilinx VU9P model, but is not limited to the model.

Aiming at the problems that in the prior art, when the processor I/O is expanded, the hardware design of a main board is complex, the functions of a plurality of controllers or I/O expansion bridge chips are limited, and different platforms are incompatible, the application provides an integrated I/O controller and a system based on FPGA and FPGA available IP with higher compatibility and integration level. The application provides an integrated I/O expansion framework suitable for a server mainboard, can support downlink interfaces such as common PCIe, USB, SATA, gigabit Ethernet and the like, and also can support uplink PCIe interfaces, wherein the PCIe interfaces are high-speed serial interfaces which can be used universally by all processors on the market. Because the hardware logic control function is generally designed by using a single CPLD/FPGA on the mainboard, the function of the CPLD/FPGA is integrated in the I/O controller, so that the integration level of the I/O controller is improved, and the number of chips on the mainboard is further reduced. According to the method and the device, the logic control module and the PCIe Switch IP are connected through the FPGA internal interconnection bus, so that the information synchronization efficiency is improved, the hot plug stability of the PCIe device is further improved, and the data loss probability and the hardware error probability are reduced. The application is based on three key parameters: the quantity of LUTs, BRAM and GTx provides a simple FPGA chip selection guide for the scheme. The I/O controller provided by the application realizes the control function of various interfaces, but only one Flash chip is needed to carry out configuration burning, so that the firmware development difficulty and the firmware upgrading maintenance difficulty of the mainboard are reduced. The I/O controller provided by the application is based on the FPGA chip design with repeated flexible configuration, so that the configuration can be flexibly changed, for example, the PCIe 4.0Switch can be upgraded to the PCIe 5.0Switch, and at the moment, the I/O controller can be reconfigured to support the PCIe 5.0 only by burning the configuration file again. It should be noted that the above solutions are specific examples of the present application, and the present application is not limited to a specific solution, and the model of each device is selected according to the actual situation.

The I/O controller of a processor provided by the present application is described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the same element.

Claims

1. An I/O controller of a processor, comprising: an FPGA provided with an IP core; the IP core at least comprises: PCIe SwitchIP;

the PCIe switchIP uplink port is connected to the processor PCIe downlink port through the FPGA pin, so that the PCIe switchIP can communicate with the processor conveniently;

the PCIe switchIP is also connected with an internal interconnection bus of the FPGA, and the internal interconnection bus is connected with other hardware equipment except the PCIe switchIP so as to facilitate the communication between the other hardware equipment and the processor; wherein the hardware device comprises the IP core.

2. The I/O controller of processor of claim 1, wherein said IP core in said hardware device further comprises: SATA controller IP; the SATA controller IP is connected with the internal interconnection bus and used for being connected with SATA equipment.

3. The I/O controller of processor of claim 2, wherein said IP core in said hardware device further comprises: gigabit Ethernet IP; the gigabit Ethernet IP is connected with the internal interconnection bus and is used for connecting the gigabit Ethernet PHY chip.

4. The I/O controller of a processor of claim 3, wherein the IP core in the hardware device further comprises: USBIP; the USBIP is connected with the internal interconnection bus and used for being connected with a USB PHY chip.

5. The I/O controller of a processor of claim 4, wherein the hardware device further comprises: a logic control module; and the logic control module is connected with the internal interconnection bus.

6. The I/O controller of a processor of claim 5, wherein the hardware device further comprises: an SPI interface; and the SPI interface is connected with the internal interconnection bus.

7. The processor I/O controller of claim 1, wherein said downstream port for PCIe Switch IPs is coupled to a GTx pin of said FPGA for coupling downstream PCIe devices.

8. The I/O controller of a processor of claim 1, wherein a model of the FPGA is selected according to a type of hardware and/or an amount of hardware on the FPGA.

9. The I/O controller of a processor of claim 8, wherein the model of the FPGA is selected according to hardware parameters and a hardware quantity corresponding to a hardware type on the FPGA, and the hardware parameters comprise: number of LUTs, BRAM, GTx.

10. The I/O controller of claim 1, wherein said PCIe Switch IP upstream port is coupled to said processor PCIe downstream port through said FPGA GTx pin.