CN106970890A - A kind of multistage I2C bus control methods - Google Patents
A kind of multistage I2C bus control methods Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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Abstract
The invention discloses a kind of multistage I2C bus control methods, it will close the operating delay of bus, gate bus to before access bus.The present invention can be effectively improved to the intelligent of I2C bus marcos, convenience, accuracy, high efficiency, can be widely used in various multistage I2C bus topolopies.
Description
Technical field
The present invention relates to microelectronics Control on Communication field, and in particular to standard I2C bus control technologys.
Background technology
I2C (Inter-Integrated Circuit) bus is that the twin wire developed by PHILIPS companies is serially total
Line, for connecting microcontroller and its ancillary equipment, the addressing to each node is soft addressing system, saves chip select line, mark
Accurate addressing byte SLAM is 7, can address 127 units.
But the bus address of majority I2C slave units is quite fixed, such as the SFP commonly used in a communications device, its I2C bus
Address is fixed as 0x50, when needing to use multiple this equipment, then needs to use I2C bus-extending technologies, while I2C buses
Topology will be complicated, and challenge is proposed to software controlling technique.
I2c-mux in existing control mode, such as linux, this I2C buses can be recorded in the form of a tree and are opened up
Flutter, one I2C bus of each node on behalf of tree and the set membership reflected between bus, i2c-mux provides a kind of intelligence and visited
The mode of every bus in this topology is asked, but access is all subjected to gate bus, accesses bus, closes bus 3 every time
Step, to ensure that whole topology can be accessed correctly, although this mode is relatively easy in logic, access efficiency is very low
Under.
The content of the invention
For defect of the existing I2C bus marcos scheme on access efficiency, it is an object of the invention to provide a kind of energy
Enough effectively improve the I2C bus marco schemes of access efficiency.
In order to achieve the above object, originally adopt the following technical scheme that：
A kind of multistage I2C bus control methods, the control method will close bus, the operating delay of gate bus is visited
Before asking bus.
It is preferred that, the handoff delay of I2C multi channel selecting passages is selected to the same multichannel of subsequent operation in the control method
Just carried out during logical other I2C buses；By its of the closing delay of I2C multi channel selecting passages to the same higher level's bus of subsequent operation
Just carried out during subordinate's bus of its multi channel selecting.
It is preferred that, the control method is indexed according to known I2C buses, gates I2C buses.
It is preferred that, the control method gating I2C buses comprise the following steps：
1) higher level's I2C buses are then first gated if there is higher level I2C buses, turned (3)；
2) if higher level I2C buses have certain other subordinates bus and are not turned off, close under higher level's I2C buses
This subordinate's bus；And select the closing delay of I2C multi channel selecting passages to other multichannels of the same higher level's bus of subsequent operation
Just carried out during logical subordinate's bus；
If 3) the unselected general rule of the multi channel selecting of this I2C bus is selected with the multi channel selecting method of this I2C bus
It is logical；And will just be carried out during other I2C buses of the handoff delay of I2C multi channel selecting passages to the same multi channel selecting of subsequent operation.
The multistage I2C bus control methods that the present invention is provided can be effectively improved to the intelligent, convenient of I2C bus marcos
Property, accuracy, high efficiency, can be widely used in various multistage I2C bus topolopies.
Brief description of the drawings
The present invention is further illustrated below in conjunction with the drawings and specific embodiments.
Fig. 1 is I2C bus control system block diagrams in the present invention program；
Fig. 2 is I2C bus topology figures in the present invention program；
Fig. 3 is I2C bus topology figures in present example；
Fig. 4 is registration I2C bus flow charts in present example；
Fig. 5 is closing I2C bus flow charts in present example；
Fig. 6 is gating I2C bus flow charts in present example；
Fig. 7 is access I2C bus flow charts in present example.
Embodiment
In order that the technical means, the inventive features, the objects and the advantages of the present invention are easy to understand, tie below
Conjunction is specifically illustrating, and the present invention is expanded on further.
Referring to Fig. 1, the I2C bus control systems 100 in this programme mainly include I2C bus control modules 110 and I2C is total
The two parts of line operate interface 120.
Wherein, I2C bus control modules 110 are connected with corresponding application data, and pass through I2C bus operation interfaces
120 are connected to corresponding I2C main equipments 130, and I2C main equipments 130 be connected to by corresponding I2C bus topologies 140 it is some
I2C slave units 150.
Referring to Fig. 2, I2C bus topologies 140 here are multistage I2C buses, and I2C main equipments 130 are connected by one-level bus
It is connected to I2C multi channel selectings equipment 141,142 and I2C slave units 151.The passage a of I2C multi channel selectings equipment 141 passes through two grades
Bus is connected to I2C slave units 152, and the passage b of I2C multi channel selectings equipment 141 is connected to I2C slave units by secondary bus
153.The passage a of I2C multi channel selectings equipment 142 is connected to I2C multi channel selectings equipment 143, I2C multi channel selectings by secondary bus
The passage b of equipment 142 is connected to I2C slave units 154 by secondary bus.The passage b of I2C multi channel selectings equipment 143 passes through three
Level bus is connected to I2C slave units 155.
In the control system, I2C bus control modules 110 are responsible for I2C topologys, and provide intelligence to application module
The efficient method for accessing I2C slave units.
I2C bus control modules are specifically included with lower unit：
(1) bus unit is registered, for known higher level I2C buses (or root bus), multi channel selecting equipment and gating method,
This I2C bus is registered to I2C bus topologies, and obtains I2C buses index.
The registration bus unit is registered an I2C bus and comprised the following steps：
1) to I2C bus topology log-on data structures.
2) this I2C bus is closed.
3) index of this I2C bus is obtained.
(2) bus unit is closed, for known I2C buses index, this I2C bus is closed.
The closing bus unit is closed an I2C bus and comprised the following steps：
1) higher level's I2C buses are then first gated if there is higher level I2C buses, turned (3).
2) closed if the multi channel selecting of this I2C bus is not turned off with the multi channel selecting method of this I2C bus
Close.
(3) gate bus unit, for known I2C buses index, gates this I2C bus.
One I2C bus of the gate bus one-cell switching comprises the following steps：
1) higher level's I2C buses are then first gated if there is higher level I2C buses, turned (3).
2) if higher level I2C buses have certain other subordinates bus and are not turned off, close under higher level's I2C buses
This subordinate's bus.
This step arrives the closing delay of I2C multi channel selecting passages other multi channel selectings of the same higher level's bus of subsequent operation
Just carried out during subordinate's bus.
If 3) the unselected general rule of the multi channel selecting of this I2C bus is selected with the multi channel selecting method of this I2C bus
It is logical.
When this walks other I2C buses by the handoff delay of I2C multi channel selecting passages to the same multi channel selecting of subsequent operation
Just carry out.
(4) access slave unit, for known I2C buses index, accesses the slave unit in this I2C bus.
Slave unit in one I2C bus of the access slave unit access comprises the following steps：
1) this I2C bus is gated, is turned (1).
2) I2C bus operation interface access slaves are called.
It is (such as following to answer by predefined interface between each functional unit in the I2C bus control modules 110 constituted accordingly
With the interface i2c_mux_select of the gating I2C buses in example) interact, realize the items of I2C bus control modules
Function.
In the control system, I2C bus operations interface 120 is used to I2C drive the regular backward I2C of provided interface
Interface after bus control module offer is regular.Interface after regular includes read access of the I2C main equipments to slave unit and operates, writes
Access operation, combined access operation etc..
On this basis, ensureing that I2C bus topologies can be correct by using delay channel switching technology in this programme
On the premise of access, by bus-off, bus strobe operating delay to access bus before, and only it is necessory to situation
It is lower just to operate.
For such scheme, below by taking the I2C bus topologies shown in Fig. 3 as an example, the tool of this control program is further illustrated
Body implementation process, it is specific as follows：
1st, each data structure is as follows in I2C bus topologies in this example：
(1) I2C bus operations interface
(2) I2C multi channel selectings device data structure is as follows in this example：
(3) I2C bus data structures are as follows in this example：
2nd, based on above-mentioned scheme, in this example an I2C gating device is registered to comprise the following steps：
int i2c_mux_dev_register(int*dev_index,i2c_mux_dev_t*dev)；
I2c_mux_dev_register is the interface of registration I2C gating devices.
(1) register and preserve the data structure of this I2C gating device.
(2) index of this I2C gating device is obtained.
3rd, register an I2C bus in this example to comprise the following steps, as shown in Figure 4：
int i2c_mux_register(int*mux_index,i2c_mux_t*i2c_mux)；
I2c_mux_register is the interface of registration I2C buses.
(1) to I2C bus topology log-on data structures.
Index=find_free_index ()；
I2c_mux_table [index]=i2c_mux；
(2) this I2C bus is closed.
_i2c_mux_close(index)；
(3) this I2C bus index is obtained.
* mux_index=index.
4th, close an I2C bus in this example to comprise the following steps, as shown in Figure 5：
(1) higher level I2C buses are determined whether there is and then first gate higher level's I2C buses, if there is no being transferred to step (3)；
If in the presence of being transferred to step (2)；
(2) higher level's I2C buses are first gated；
(3) determine whether the multi channel selecting of this I2C buses closes, if closing, be transferred to step (5), if being not turned off, turn
Enter step (4)；
(4) closed with the multi channel selecting method of this I2C bus；
(5) terminate.
Accordingly, the specific implementation process that an I2C bus is closed in this example is as follows：
static int_i2c_mux_close(int mux_index)；
_ i2c_mux_close is the interface for closing I2C buses.
(1) higher level's I2C buses are then first gated if there is higher level I2C buses.
I2c_mux=i2c_mux_table [mux_index]；
if(temp->parent_index！=-1)
_i2c_mux_select(temp->parent_index)；
(2) closed if the multi channel selecting of this I2C bus is not turned off with the multi channel selecting method of this I2C bus
Close.
5th, gate an I2C bus in this example to comprise the following steps, as shown in Figure 6：
(1) higher level's I2C buses are judged whether, if in the presence of being transferred to step (2)；If being not present and being transferred to step (3)；
(2) preferential gating higher level's I2C buses；
(3) judge that higher level I2C buses whether there is other level bus and be not turned off；If other level bus-off, is transferred to step
(5)；If having other level bus to be not turned off, step (4) is transferred to；
Here other level bus refers to subordinate's bus under the non-same multi channel selecting equipment of same higher level's bus.
(4) this subordinate's bus closed under higher level's I2C buses；
(5) judge whether the multi channel selecting of this I2C bus gates；If gating, is transferred to step (7)；If not gating, turn
Enter step (6)；
(6) gated with the multi channel selecting method of this I2C bus；
(7) terminate.
Accordingly, the specific implementation process that an I2C bus is gated in this example is as follows：
static int_i2c_mux_select(int current_index)；
_ i2c_mux_select is the interface of gating I2C buses.
(1) higher level's I2C buses are then first gated if there is higher level I2C buses；
Current=i2c_mux_table [current_index]；
if(current->parent_index！=-1)
_i2c_mux_select(current->parent_index)；
(2) if subordinate's bus that higher level I2C buses have other multi channel selecting equipment is not turned off, higher level is closed
This subordinate's bus under I2C buses；
(3) if the unselected general rule of the multi channel selecting of this I2C bus is selected with the multi channel selecting method of this I2C bus
It is logical；
6th, access an I2C bus in this example to comprise the following steps, as shown in Figure 7：
int i2c_mux_read(int mux_index,uint32 addr,uint8*buf,int len)；
int i2c_mux_write(int mux_index,uint32 addr,uint8*buf,int len)；
int i2c_mux_combine(int mux_index,uint32 addr,uint8*tx_data,int tx_
len,uint8*rx_data,int rx_len)；
I2c_mux_xxx is the interface for accessing I2C buses.
(1) this I2C bus is gated；
_i2c_mux_select(mux_index)；
(2) standard I2C bus operation interface access slaves are called；
I2c_mux=i2c_mux_table [mux_index]；
i2c_mux->bus->i2c_xxx(addr,......)。
7th, I2C bus topology steps are registered in this example as follows：
(1) registration one-level bus bus 0；
I2c_simulate_host is the interface of simulation I2C controller operator trunks.
Bus0.bus=i2c_simulate_host；
Bus0.parent_index=-1；
Bus0.dev_index=-1；
i2c_mux_register_new(&bus0_index,&bus0)；
(2) I2C multi channel selecting equipment is registered；
Pca9547_select is PCA9547 gating method, acquiescence gating passage 0.
Mux0.select=pca9547_select；
Mux0.current=0；
Mux0.arg=0x70；
i2c_mux_dev_register(&mux0_index,&mux0)；
Mux1.select=pca9547_select；
Mux1.current=0；
Mux1.arg=0x71；
i2c_mux_dev_register(&mux1_index,&mux1)；
(3) registration secondary bus bus 1-4；
Bus1.parent_index=bus0_index；
Bus1.dev_index=mux0_index；
Bus1.dev_channel=0；
i2c_mux_register_new(&bus1_index,&bus1)；
Bus2.parent_index=bus0_index；
Bus2.dev_index=mux0_index；
Bus2.dev_channel=1；
i2c_mux_register_new(&bus2_index,&bus2)；
Bus3.parent_index=bus0_index；
Bus3.dev_index=mux1_index；
Bus3.dev_channel=0；
i2c_mux_register_new(&bus3_index,&bus3)；
Bus4.parent_index=bus0_index；
Bus4.dev_index=mux1_index；
Bus4.dev_channel=1；
i2c_mux_register_new(&bus4_index,&bus4)。
8th, I2C bus examples are accessed in this example as follows：
(1) equipment under one-level bus is accessed；
i2c_mux_xxx(bus0_index,0x4C,...)；
(2) equipment under secondary bus is accessed；
i2c_mux_xxx(bus1_index,0x50,...)；
i2c_mux_xxx(bus2_index,0x50,...)；
i2c_mux_xxx(bus3_index,0x50,...)；
i2c_mux_xxx(bus4_index,0x50,...)。
From the foregoing, it will be observed that the switching of I2C multi channel selectings passage is delayed by the same multi channel selecting of subsequent operation in this example
Just carried out during other I2C buses, the closings of I2C multi channel selecting passages be delayed by the same higher level's bus of subsequent operation other are more
Just carried out during subordinate's bus of road gating, above technology is referred to as delay switching technology, effectively increases access efficiency.It is total with two-stage
Exemplified by line, maximum can reduce by 2/3 invalid operation during two-stage bus, and maximum can reduce (2n-2)/(2n-1) nothing during n grades of buses
Effect operation, effectively improves access efficiency.
Furthermore based on examples detailed above scheme, it can realize to all types of I2C main equipments, slave unit, multi channel selecting equipment
The efficient access of the I2C bus topologies of any number of stages of composition, its principle is not all as described above, be repeated here herein.
General principle, principal character and the advantages of the present invention of the present invention has been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the simply explanation described in above-described embodiment and specification is originally
The principle of invention, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these changes
Change and improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention by appended claims and its
Equivalent thereof.
Claims (4)
1. a kind of multistage I2C bus control methods, it is characterised in that the control method will close the behaviour of bus, gate bus
It is deferred to before access bus.
2. a kind of multistage I2C bus control methods according to claim 1, it is characterised in that will in the control method
The handoff delay of I2C multi channel selecting passages to the same multi channel selecting of subsequent operation other I2C buses when just carry out；I2C is more
Just carried out during the subordinate's bus for other multi channel selectings that the same higher level's bus of subsequent operation is arrived in the closing delay of road gating passage.
3. a kind of multistage I2C bus control methods according to claim 2, it is characterised in that the control method according to
Known I2C buses index, gates I2C buses.
4. a kind of multistage I2C bus control methods according to Claims 2 or 3, it is characterised in that the control method choosing
Logical I2C buses comprise the following steps：
1) higher level's I2C buses are then first gated if there is higher level I2C buses, turned (3)；
If 2) higher level I2C buses have certain other subordinates bus and are not turned off, this under higher level's I2C buses is closed
Subordinate's bus；And the closing delay of I2C multi channel selecting passages is arrived to other multi channel selectings of the same higher level's bus of subsequent operation
Just carried out during subordinate's bus；
If 3) the unselected general rule of the multi channel selecting of this I2C bus is gated with the multi channel selecting method of this I2C bus；And
To just it be carried out during other I2C buses of the handoff delay of I2C multi channel selecting passages to the same multi channel selecting of subsequent operation.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109933557A (en) * | 2019-03-21 | 2019-06-25 | 浪潮商用机器有限公司 | A kind of generation method and device of I2C topological diagram |
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