CN107391403A - Communication means and device in a kind of storage device between multiplexer (MUX - Google Patents
Communication means and device in a kind of storage device between multiplexer (MUX Download PDFInfo
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- CN107391403A CN107391403A CN201710632607.5A CN201710632607A CN107391403A CN 107391403 A CN107391403 A CN 107391403A CN 201710632607 A CN201710632607 A CN 201710632607A CN 107391403 A CN107391403 A CN 107391403A
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- interchanger
- mux
- multiplexer
- cpu
- dma engine
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The invention discloses the communication means between multiplexer (MUX in a kind of storage device, including open the Enable Pin of CPU on each multiplexer (MUX；In storage device after electricity, the interchanger on each multiplexer (MUX is enumerated, and respective memory space is distributed for each interchanger；Judge whether interchanger carries DMA engine, be interchanger carry DMA engine corresponding with target CPU if it is not, then according to target NTB ports and target CPU corresponding relation.Therefore, this method can be interchanger carry DMA engine, realize the data transfer between CPU on each multiplexer (MUX, improve message transmission rate according to NTB ports and CPU corresponding relation；In addition, when changing different hardware platforms, it is only necessary to be DMA engine corresponding to interchanger carry, avoid the problem of software development cycle is long.In addition, the invention also discloses the communicator between multiplexer (MUX in a kind of storage device, effect is as above.
Description
Technical field
The present invention relates to communication technical field, communication means in more particularly to a kind of storage device between multiplexer (MUX and
Device.
Background technology
With the development of science and technology, the extending transversely of multiplexer (MUX becomes more and more popular in various storage devices, many producers
Exactly product is upgraded using this method extending transversely.It is extending transversely to refer to add newly more in storage device
Road controller, worked together with original multiplexer (MUX.There are many methods to realize this extending transversely, for example, traditional
Network, InfinBand, PCIE etc..It is especially most widely used with PCIE technologies, realize too busy to get away PCIE extending transversely with PCIE technologies
Interchanger, interchanger mentioned here mainly include PCIE chips, multiple PCIE bridges, carry non-transparent bridge, and some also carries DMA
Function, and various configurations are supported, the configuration of PCIE chips is flexible, and management is convenient.
In the multiplexer (MUX of storage device, multiple CPU are included on each multiplexer (MUX, and between CPU
Communicated typically by QPI.But in QPI communication process, data transmission efficiency is low between multiplexer (MUX, change different
Software development cycle is grown during hardware platform.
As can be seen here, how to overcome QPI communication band come data transmission efficiency it is low the problem of be those skilled in the art urgently
The problem of to be solved.
The content of the invention
The embodiment of the present application provides the communication means and device between multiplexer (MUX in a kind of storage device, existing to solve
There is the problem of data transmission efficiency is low in technology.
In order to solve the above technical problems, the invention provides the communication means between multiplexer (MUX in a kind of storage device,
Including：
Open the Enable Pin of the CPU in the storage device on each multiplexer (MUX；
In the storage device after electricity, the interchanger on each multiplexer (MUX is enumerated, and is each friendship
Change planes and distribute respective memory space；
Judge whether the interchanger carries DMA engine, if it is not, then corresponding with target CPU according to target NTB ports
Relation, it is interchanger carry DMA engine corresponding with the target CPU.
Preferably, the interchanger is PCIE interchangers.
Preferably, the working method of the DMA engine is specially：Worked by way of descriptor.
Preferably, the descriptor includes source address, destination address and data length.
Preferably, the CPU Enable Pins are opened especially by BIOS.
In order to solve the above technical problems, the present invention also provides the communicator in a kind of storage device between multiplexer (MUX,
Including：
Opening unit, for opening the Enable Pin of the CPU in the storage device on each multiplexer (MUX；
Memory Allocation unit, it is each for interchanger distribution after enumerating the interchanger on the multiplexer (MUX
From memory space；
Judging unit, for judging whether the interchanger carries DMA engine, if it is not, then triggering carry unit；
The carry unit, for for interchanger carry DMA engine corresponding with the target CPU.
Preferably, the interchanger is PCIE interchangers.
Preferably, the working method of the DMA engine is specially：Worked by way of descriptor.
Preferably, the descriptor includes source address, destination address and data length.
Preferably, the CPU Enable Pins are opened especially by BIOS.
Relative to prior art, communication means and device in storage device provided by the present invention between multiplexer (MUX,
When the interchanger on the multiplexer (MUX enumerated in itself without DMA engine when, will be according to target NTB ports and target CPU
Corresponding relation, for DMA engine corresponding to corresponding interchanger carry target CPU.As can be seen here, on the one hand, the interchanger can
By the DMA engine of carry, the data transfer between CPU on each multiplexer (MUX is realized, and no longer as needing in the prior art
The data transfer between CPU is realized by QPI, and then improves message transmission rate；On the other hand, by interchanger is hung
The DMA engine of load is obtained according to the CPU corresponding with NTB ports DMA engine, therefore, it is possible to realize NTB ports with
CPU correspondence, further improves message transmission rate.In addition, when changing different hardware platforms, it is only necessary to be interchanger carry
Adaptable DMA engine, therefore avoid the problem of software development cycle is long.
Brief description of the drawings
The technical scheme implemented in order to illustrate more clearly of the present invention, below by the required accompanying drawing used in embodiment
It is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, general for this area
For logical technical staff, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the communication means between multiplexer (MUX in a kind of storage device provided in an embodiment of the present invention；
Fig. 2 is the hardware schematic for carrying out NTB communications in storage device of the embodiment of the present invention between multiplexer (MUX；
Fig. 3 is the cut-away view of a multiplexer (MUX；
Fig. 4 is the communicator composition signal between multiplexer (MUX in a kind of storage device provided in an embodiment of the present invention
Figure.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The core of the present invention is to provide in a kind of storage device communication means and device between multiplexer (MUX, can improve
Data transmission efficiency between multiplexer (MUX, reduce the cycle of software development when changing different hardware platforms.
In order that those skilled in the art more fully understand the present invention program, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.
Fig. 1 is the communication means flow chart between multiplexer (MUX in storage device of the embodiment of the present invention, as shown in figure 1, bag
Include following steps：
Step S101：Open the Enable Pin of the CPU in storage device on each multiplexer (MUX；
CPU Enable Pins are opened by BIOS, are only opened on multiplexer (MUX after CPU Enable Pins, system kernel can just make
With the DMA engine of the CPU.
Step S102：In storage device after electricity, the interchanger on each multiplexer (MUX is enumerated, and is each interchanger
Distribute respective memory space；
In storage device, typically there is more than one multiplexer (MUX, there is interchanger, system on each multiplexer (MUX
When needing to realize on multiplexer (MUX the data transfer between CPU, corresponding interchanger is just enumerated, and to enumerate
Interchanger distribute respective memory space.
Such as, it is now desired to the data transfer between CPU on the first multiplexer (MUX and the second multiplexer (MUX is realized, is
System kernel just automatically enumerates the interchanger corresponding with the first multiplexer (MUX and the second multiplexer (MUX, and to enumerate
Interchanger distribution memory space.Described interchanger is PICE interchangers in the embodiment of the present application, it is of course also possible to be it
Its satisfactory interchanger, the type of interchanger have no effect on the realization of the embodiment of the present application.
Step S103：Judge whether the interchanger that enumerates carries DMA engine, if it is not, then into step S104；
Step S104：According to target NTB ports and target CPU corresponding relation, for the interchanger carry and mesh enumerated
Mark DMA engine corresponding to CPU.
Some interchangers itself carry DMA engine, and some interchangers itself are without DMA engine, when interchanger itself
The DMA engine just carried during with DMA engine using interchanger, according to exchange if interchanger itself is without DMA engine
The descending NTB ports of machine search out corresponding uplink port, and the uplink port and descending NTB ports are on same interchanger, root
Connected CPU, and carry CPU DMA automatically are scanned for according to BUS, DEVICE, FUNCTION of uplink port
Engine.NTB ports carry out transceiving data by using corresponding CPU DMA engine, realize CPU between each multiplexer (MUX
Data transfer.
DMA engine is carried out by way of descriptor in fact, and many information are included in descriptor, for example, source address,
Destination address, data length, generally, these descriptors form a queue and used for DMA engine.
In the embodiment of the present application, when the interchanger on the multiplexer (MUX enumerated in itself without DMA engine when, system
Automatically according to target NTB ports and target CPU corresponding relation, draw for DMA corresponding to corresponding interchanger carry target CPU
Hold up.The data transfer between CPU on each multiplexer (MUX is realized, and no longer as needing to realize CPU by QPI in the prior art
Between data transfer, and then improve message transmission rate.
As shown in Figure 2 and Figure 3, Fig. 2 is to carry out the hard of NTB communications in storage device of the embodiment of the present invention between multiplexer (MUX
Part schematic diagram；Fig. 3 is the cut-away view of a multiplexer (MUX.
In one storage device 201, comprising multiplexer (MUX 202, it is of course also possible to be single channel controller, either singly
Road controller or multiplexer (MUX have no effect on the realization of the embodiment of the present application.Have on one multiplexer (MUX 202 multiple
It can carry out data transmission between CPU, multiple CPU on a multiplexer (MUX 202, the CPU on each multiplexer (MUX 202
Between can also carry out data transmission, i.e., can carry out data transmission between each multiplexer (MUX 202.
As shown in figure 3, a multiplexer (MUX 202 includes CPU0, CPU1, interchanger PCIE switch, interchanger PCIE
Switch can carry out the data transfer between multiple ports pair in synchronization, have on interchanger PCIE switch up going port and
Down going port NBT0, NBT1.CPU0, CPU1 and NTB0, NTB1 are only depicted in figure 3, are hereafter referred to as CPU and NTB, CPU and NTB
Number be not necessarily two or multiple, how much their number has no effect on the realization of the embodiment of the present application.NTB
Port is also referred to as non-transparent bridge port, and up going port can be connected with CPU port, NTB mouths can with carry out data transmission it is another
The corresponding NTB mouths connection of interchanger on one multiplexer (MUX 202, data are to carry out forwarding transmission by NTB mouths.It is first
First, NTB kernel states processing event host process is created, for managing whole NTB communication process.It is right after cpu reset, system electrification
Interchanger PCIE switch are enumerated, and after interchanger PCIE switch are enumerated successfully, system identification goes out interchanger PCIE
Transparent bridge on switch initializes with non-transparent bridge NBT, CPU to the interchanger PCIE switch enumerated, and is phase
The interchanger PCIE switch distribution memory spaces answered.Then, system kernel software can record corresponding interchanger PCIE simultaneously
Switch attaching information, according to interchanger PCIE switch attaching information, find corresponding interchanger PCIE
Switch uplink port, and record interchanger PCIE switch numberings.When the interchanger PCIE switch enumerated from
When body carries DMA engine, with regard to carrying out the data transfer between CPU using the DMA engine carried, if the interchanger enumerated
PCIE switch itself, then according to the interchanger PCIE switch NBT and CPU corresponding relation, are without DMA engine
Interchanger PCIE switch carry CPU DMA engines, during carry CPU DMA engine, it is not based on CPU concrete model
Searched, but retrieved according to the numbering of the interchanger of uplink port, finally realize the number between multiplexer (MUX 202
According to transmission.
In the corresponding CPU of carry DMA engine, searched according to CPU concrete model, but according to upstream ends
The numbering of the interchanger of mouth is retrieved, so when needing the hardware platform more renewed, for example, changing CPU models, kernel is soft
Part remains to Automatic-searching to corresponding DMA engine without modification and used for interchanger carry, avoids software development cycle length
The problem of.
It is described in detail above for the embodiment of the communication means between multiplexer (MUX in storage device, this hair
Bright embodiment additionally provides the communicator between multiplexer (MUX in a kind of storage device corresponding with this method.Due to device portion
The embodiment and the embodiment of method part divided are mutually corresponding, therefore the embodiment of device part refer to the implementation of method part
Example description, is repeated no more here.
Fig. 4 is the device composition schematic diagram, as shown in figure 4, including：Opening unit 401, Memory Allocation unit 402, judge
Unit 403, carry unit 404；
Opening unit 401, for opening the Enable Pin of the CPU in storage device on each multiplexer (MUX；
Memory Allocation unit 402, after enumerating the interchanger on multiplexer (MUX, and it is respective for interchanger distribution
Memory space；
Whether judging unit 403, the interchanger for judging to enumerate carry DMA engine, if it is not, then triggering carry list
Member；
Carry unit 404, for the interchanger carry DMA engine corresponding with target CPU to enumerate.
Communicator in the storage device that the present embodiment provides between multiplexer (MUX, is first turned on each more in storage device
The Enable Pin of CPU on the controller of road；Then machine is carried out to the exchange on multiplexer (MUX to enumerate, and the interchanger to enumerate
Distribute respective memory space；Finally, whether the interchanger that system automatic decision enumerates carries DMA engine, if it is not, then touching
It is the interchanger carry enumerated DMA engine corresponding with target CPU to send out carry unit.
As can be seen here, it is the interchanger carry DMA engine corresponding with target CPU enumerated, realizes multiplexer (MUX
Between data transfer, be no longer that data transfer is realized by QPI, improve data transmission efficiency.
Preferably embodiment, interchanger are PCIE interchangers.
Preferably embodiment, the working method of DMA engine are specially：Worked by way of descriptor.
Preferably embodiment, descriptor include source address, destination address and data length.
Preferably embodiment, CPU Enable Pins are opened especially by BIOS.
The communication means multiplexer (MUX in storage device provided by the present invention and device have been carried out in detail above
Introduce.The principle and embodiment of the present invention are set forth with several examples herein, the explanation of above example, only
It is the method and its core concept for being used to help understand the present invention；Meanwhile for those of ordinary skill in the art, according to this hair
Bright thought, there will be changes in specific embodiments and applications, in summary, this specification content should not manage
Solve as limitation of the present invention, those skilled in the art, on the premise of no creative work, repaiied to what the present invention was made
Change, equivalent substitution, improvement etc., should be included in the application.
Claims (10)
- A kind of 1. communication means in storage device between multiplexer (MUX, it is characterised in that including：Open the Enable Pin of the CPU in the storage device on each multiplexer (MUX；In the storage device after electricity, the interchanger on each multiplexer (MUX is enumerated, and is each interchanger Distribute respective memory space；Judge whether the interchanger carries DMA engine, if it is not, then being closed according to target NTB ports are corresponding with target CPU System, is interchanger carry DMA engine corresponding with the target CPU.
- 2. according to the method for claim 1, it is characterised in that the interchanger is PCIE interchangers.
- 3. according to the method for claim 3, it is characterised in that the working method of the DMA engine is specially：Pass through description The mode of symbol works.
- 4. according to the method for claim 4, it is characterised in that the descriptor includes source address, destination address and number According to length.
- 5. according to the method described in claim 1-4 any one, it is characterised in that the CPU Enable Pins are especially by BIOS Open.
- A kind of 6. communicator in storage device between multiplexer (MUX, it is characterised in that including：Opening unit, for opening the Enable Pin of the CPU in the storage device on each multiplexer (MUX；Memory Allocation unit, after enumerating the interchanger on the multiplexer (MUX, distributed for the interchanger respective Memory space；Judging unit, for judging whether the interchanger carries DMA engine, if it is not, then triggering carry unit；The carry unit, for for interchanger carry DMA engine corresponding with the target CPU.
- 7. device according to claim 6, it is characterised in that the interchanger is PCIE interchangers.
- 8. device according to claim 6, it is characterised in that the working method of the DMA engine is specially：Pass through description The mode of symbol works.
- 9. device according to claim 8, it is characterised in that the descriptor includes source address, destination address and number According to length.
- 10. according to the device described in claim 6-9 any one, it is characterised in that the CPU Enable Pins are especially by BIOS Open.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710632607.5A CN107391403A (en) | 2017-07-28 | 2017-07-28 | Communication means and device in a kind of storage device between multiplexer (MUX |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710632607.5A CN107391403A (en) | 2017-07-28 | 2017-07-28 | Communication means and device in a kind of storage device between multiplexer (MUX |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109189699A (en) * | 2018-09-21 | 2019-01-11 | 郑州云海信息技术有限公司 | Multipath server communication means, system, middle controller and readable storage medium storing program for executing |
| TWI759772B (en) * | 2020-06-19 | 2022-04-01 | 英業達股份有限公司 | Pcie data transmission control system |
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| JPH0836542A (en) * | 1994-07-26 | 1996-02-06 | Nec Eng Ltd | Dma controller |
| CN101539902A (en) * | 2009-05-05 | 2009-09-23 | 中国科学院计算技术研究所 | DMA device for nodes in multi-computer system and communication method |
| CN101710314A (en) * | 2009-11-17 | 2010-05-19 | 中兴通讯股份有限公司 | High-speed peripheral component interconnection switching controller and realizing method thereof |
| CN102508786A (en) * | 2011-11-02 | 2012-06-20 | 盛科网络（苏州）有限公司 | Chip design method for optimizing space utilization rate and chip thereof |
| CN103559156A (en) * | 2013-11-11 | 2014-02-05 | 北京大学 | Communication system between FPGA (field programmable gate array) and computer |
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2017
- 2017-07-28 CN CN201710632607.5A patent/CN107391403A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0836542A (en) * | 1994-07-26 | 1996-02-06 | Nec Eng Ltd | Dma controller |
| CN101539902A (en) * | 2009-05-05 | 2009-09-23 | 中国科学院计算技术研究所 | DMA device for nodes in multi-computer system and communication method |
| CN101710314A (en) * | 2009-11-17 | 2010-05-19 | 中兴通讯股份有限公司 | High-speed peripheral component interconnection switching controller and realizing method thereof |
| CN102508786A (en) * | 2011-11-02 | 2012-06-20 | 盛科网络（苏州）有限公司 | Chip design method for optimizing space utilization rate and chip thereof |
| CN103559156A (en) * | 2013-11-11 | 2014-02-05 | 北京大学 | Communication system between FPGA (field programmable gate array) and computer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109189699A (en) * | 2018-09-21 | 2019-01-11 | 郑州云海信息技术有限公司 | Multipath server communication means, system, middle controller and readable storage medium storing program for executing |
| CN109189699B (en) * | 2018-09-21 | 2022-03-22 | 郑州云海信息技术有限公司 | Multi-server communication method, system, intermediate controller and readable storage medium |
| TWI759772B (en) * | 2020-06-19 | 2022-04-01 | 英業達股份有限公司 | Pcie data transmission control system |
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