CN110489361B - I3C interface circuit compatible with SRAM bus - Google Patents
I3C interface circuit compatible with SRAM bus Download PDFInfo
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- CN110489361B CN110489361B CN201910703449.7A CN201910703449A CN110489361B CN 110489361 B CN110489361 B CN 110489361B CN 201910703449 A CN201910703449 A CN 201910703449A CN 110489361 B CN110489361 B CN 110489361B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
Abstract
The invention discloses an I3C interface circuit compatible with an SRAM bus. The I3C interface circuit includes: the operation layer circuit is connected with the I3C communication controller and comprises N configuration registers which are connected with the I3C communication controller and used for realizing a custom function, and each configuration register corresponds to a register interface and is used for communicating with the I3C communication controller; and the bus packing layer circuit is connected with the N configuration registers on the operation layer circuit, is connected with the SRAM bus, and is used for packing the register interfaces corresponding to the configuration registers into the SRAM bus interfaces so as to realize communication with the SRAM bus. The I3C interface circuit can pack the register interface corresponding to the configuration register connected with the I3C communication controller into an SRAM bus interface to realize connection with an SRAM bus, simplify the connection between the I3C communication controller and a host system, and provide a universal and flexible bus connection mode, so that the I3C bus equipment has wider compatibility.
Description
Technical Field
The invention relates to the technical field of integrated circuit IP core design, in particular to an I3C interface circuit compatible with an SRAM bus.
Background
The IP Core is a fully-known Intellectual Property Core (Intellectual Property Core) and refers to a chip design module provided by a certain party. Designers can design logic of an application specific integrated circuit or a Field Programmable Gate Array (FPGA) based on an IP core to shorten a design period and improve design quality and efficiency.
With the rapid development of technologies such as 4G/5G, the Internet of things and the like, the sensor is more and more regarded as an entrance for data information acquisition and the heart of the Internet of things. The I2C bus is widely used due to its advantages of simplicity, less resource consumption, more slaves, low power consumption, etc., however, with the development trend of sensor intelligence and miniaturization, the limitation of the sensor on the I2C interface is gradually highlighted. To solve this problem, the MIPI alliance proposed an I3C interface specification, which is an upgraded version of I2C, having advantages of low power consumption, high data rate, support for in-band interrupt handling, etc.
Due to the complexity of the I3C communication protocol, the I3C communication controller must have complex supporting functions, and in order to realize flexible control of the I3C communication controller, the I3C communication controller can adopt a custom interface. The current custom interface of the I3C communication controller usually exposes a CSR Register (Control Status Register) and a data buffer Register (SRAM Cache Register) of each function to a user, so as to complete the interactive Control between the user and the I3C communication controller. The method is quite effective under the conditions of relatively simple functions and relatively small control scale, and the efficiency is quite high. However, since the I3C communication controller has rich functions, a large number of parameters to be controlled and flexible applications, the connection between the communication controller and the host system becomes complicated in a scene with a large control scale, thereby affecting the efficiency of I3C communication.
Disclosure of Invention
The invention provides an I3C interface circuit compatible with an SRAM bus, which aims to solve the problem that the connection between a communication controller and a host system is complicated and the communication efficiency of I3C is influenced.
The invention provides an I3C interface circuit compatible with an SRAM bus, comprising:
the operation layer circuit is connected with the I3C communication controller and comprises N configuration registers which are connected with the I3C communication controller and used for realizing a custom function, and each configuration register corresponds to a register interface and is used for communicating with the I3C communication controller;
and the bus packing layer circuit is connected with the N configuration registers on the operation layer circuit, is connected with the SRAM bus, and is used for packing the register interfaces corresponding to the configuration registers into the SRAM bus interfaces so as to realize communication with the SRAM bus.
Preferably, the bus packaging layer circuit includes an address decoder for implementing an address decoding function and a read/write controller for implementing a data read/write function, and both the address decoder and the read/write controller are connected to the configuration register.
Preferably, the operation layer circuit comprises 1 base register for obtaining a start address, N-k-1 CSR registers for implementing a control function, and k data buffer registers for implementing a data buffer function.
Preferably, the CSR registers include a base configuration register, a call configuration register, a presorting register, an SDR message length register, a DDR message length register, a static address register, a byte transfer counter, a word transfer counter, an SDR call address register, a DDR call address register, a read-write buffer pointer register, a buffer pointer reset register, a status register, and an interrupt identification register.
Preferably, the input end of the base address register is connected to a data input bus, and the output end of the base address register is connected to the address decoder and the read/write controller, and is configured to obtain a start address of a current device on the data input bus, and send the start address to the address decoder and the read/write controller;
the input ends of the CSR register and the data buffer register are connected with the address decoder, and the output ends of the CSR register and the data buffer register are connected with the read-write controller, so that the address decoder obtains the actual addresses of the CSR register and the data buffer register, and the read-write controller performs read-write control based on the actual addresses.
Preferably, the address decoder includes 1 base address logic gate, N-1 decoding adders and N-1 decoding logic gates, and each decoding adder is connected to one decoding logic gate;
the base address logic gate is connected with the base address register to cooperate with the base address register to obtain the initial address;
the input end of each current decoding adder is connected with the base address register or the previous decoding adder, and the output end of each current decoding adder is connected with a current decoding logic gate or the current decoding logic gate and the next decoding adder, and is used for acquiring a current register actual address corresponding to the CSR register or the data buffer register connected with the current decoding logic gate according to the starting address or the previous register actual address, and inputting the current register actual address to the current decoding logic gate or the current decoding logic gate and the next decoding adder.
Preferably, a first input terminal of the current decoding adder is connected to an output terminal of the base register or an output terminal of the previous decoding adder, and is configured to receive a start address or a previous register real address; a second input terminal is connected to the I3C communication controller, and is configured to receive an offset increment corresponding to the CSR register or the data buffer register connected to the current decoding logic gate; the addition output end is connected with the current decoding logic gate or the current decoding logic gate and the next decoding adder and is used for outputting the current register actual address obtained based on the initial address or the previous register actual address and the offset increment;
the input end of the current decoding logic gate is connected with the address bus, the write enable bus and the current decoding adder; and the output end of the register is connected with the CSR register or the data buffer register and is used for controlling the CSR register or the data buffer register according to the comparison result of the target address input by the address bus and the actual address of the current register.
Preferably, the read-write controller comprises a control subtracter, a control logic gate, a data selector and a data output register; the control subtracter is connected with the base register and the data selector and used for acquiring a current offset according to an initial address output by the base register and sending the current offset to the data selector; the control logic gate is connected with an SRAM bus, the base address register and the data output register and is used for acquiring a target enabling signal according to a signal input by the SRAM bus and the initial address and sending the target enabling signal to the data output register; the data selector is connected with the configuration register, the control subtracter and the data output register and is used for outputting a selection signal to the data output register according to the register output of the configuration register and the current offset; the data output register is connected with the SRAM bus, the data selector and the control logic gate and is used for performing read-write control according to the selection signal and the target enabling signal.
Preferably, a first input terminal of the control subtractor is connected to the address bus, and is configured to receive a target address input by the address bus; the second input end is connected with the base address register and used for receiving the starting address; the subtraction output end is connected with the data selector and used for obtaining the current offset according to the target address and the starting address and sending the current offset to the data selector;
the input end of the control logic gate is connected with the address bus, the write enable bus and the base address register, and the output end of the control logic gate is connected with the data output register, and is used for acquiring a target enable signal according to the target address, a write enable signal input by the write enable bus and the initial address, and sending the target enable signal to the data output register;
a first input end of the data selector is connected with output ends of the N configuration registers, a second input end of the data selector is connected with a subtraction output end of the control subtracter, and the subtraction output end of the data selector is connected with the data output register and used for acquiring a selection signal according to the current offset and sending the selection signal to the data output register;
the input end of the data output register is connected with the data selector and the control logic gate, and the output end of the data output register is connected with the data output bus and used for carrying out data read-write control with the data output bus according to a selection signal input by the data selector and a target enabling signal input by the control logic gate.
Preferably, the input ends of the configuration register and the data output register are further connected with a system clock bus; and the input ends of the CSR register and the data buffer register are also connected with a system reset bus.
In the above I3C interface circuit compatible with SRAM bus, N configuration registers connected to the I3C communication controller are provided on the operation layer circuit, and the register interface corresponding to each configuration register is connected to the bus packaging layer circuit, so that the bus packaging layer circuit packages the register interfaces into an SRAM bus interface, so as to connect to the SRAM bus through the SRAM bus interface, so that the I3C communication controller can communicate with the host system through the SRAM bus, on the premise of ensuring the flexibility of the I3C communication controller, the connection between the I3C communication controller and the host system is simplified, a universal and flexible bus connection mode is provided, and thus the I3C bus device has wider compatibility.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of an SRAM bus compatible I3C interface circuit according to an embodiment of the present invention;
FIG. 2 is another schematic diagram of an SRAM bus compatible I3C interface circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of an SRAM bus compatible I3C interface circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic diagram of an SRAM bus compatible I3C interface circuit in an embodiment of the present invention. As shown in fig. 1, the I3C interface circuit compatible with the SRAM bus is disposed between the I3C communication controller and the SRAM bus, and is used to package the custom interface of the I3C communication controller into an SRAM bus interface, so that the I3C communication controller can be conveniently mounted on a host system such as a Central Processing Unit (CPU) or a Microcontroller (MCU) system through the SRAM bus, and the connection between the I3C communication controller and the host system such as the CPU and the MCU can be simplified without reducing the flexibility of the I3C communication controller, thereby providing a universal and flexible bus connection mode and improving the adaptability of the I3C bus device.
And the operation layer circuit is connected with the I3C communication controller and comprises N configuration registers which are connected with the I3C communication controller and used for realizing a custom function, and each configuration register corresponds to a register interface and is used for communicating with the I3C communication controller.
And the bus packing layer circuit is connected with the N configuration registers on the operation layer circuit, is connected with the SRAM bus, and is used for packing the register interfaces corresponding to the configuration registers into the SRAM bus interfaces so as to realize communication with the SRAM bus.
The I3C communication controller is a controller for realizing communication based on the I3C communication protocol. Configuration registers are a collective term for all registers that are set up in custom configuration on the operating layer circuitry. The number of the configuration registers is N, and the configuration registers need a base address register, a CSR register and a data buffer register, so that the number of the configuration registers is at least three, namely N is more than or equal to 3. The register interface is a custom interface based on the I3C communication protocol and arranged on the configuration register. The register interface can be understood as an interface connected with a bus packaging layer circuit, so that the register interface can be packaged into an SRAM bus interface by the bus packaging layer circuit to achieve the purpose of communicating with an SRAM bus, the I3C communication controller can be conveniently mounted on a host system such as a Central Processing Unit (CPU) or a Microcontroller (MCU) system through the SRAM bus, and the connection between the I3C communication controller and the host system is simplified.
Generally, when an I3C communication controller is to be mounted on a host system such as a Central Processing Unit (CPU) or a Microcontroller (MCU) system, the communication mode generally defines a set of CSR registers (Control Status Register for short) for solving the problem of workflow Control; and a set of data buffer registers (such as SRAMCache registers) is set for solving the data exchange problem. Therefore, in order to mount the I3C communication controller to the host system to implement its communication function, configuration registers such as a CSR register and a data buffer register need to be configured on the operation layer circuit, so that each configuration register can implement the custom function corresponding to the I3C communication controller. That is, the configuration registers on the operation layer circuit include a CSR register and a data buffer register, wherein the CSR register includes a control register and a status register.
Specifically, the operation layer circuit is connected with the I3C communication controller downwards and is connected with the bus packing layer circuit upwards, and the functions of all configuration registers in the operation layer circuit can be configured in a customized mode according to the operation characteristics of the I3C communication controller. For example, the control register can be customized according to the signals needing to be controlled extracted from the I3C communication controller; according to the signals needing to be monitored are extracted from the I3C communication controller, a state register is defined; and configure the data buffer registers in the operation layer circuitry. The data buffer register can adopt an SRAM Cache register, the SRAM is mainly used for second-level fast Cache, and a transistor is used for storing data; compared with DRAM, SRAM has fast speed and simple control, but the capacity of SRAM is smaller than that of other types of memory in the same area, and the SRAM is just suitable for data caching application of communication controller.
Correspondingly, the bus packaging layer circuit is connected with the operation layer circuit downwards and is connected with the SRAM bus upwards, and the bus packaging layer circuit is used for packaging the register interface corresponding to the configuration register into the SRAM bus interface so as to realize communication with the SRAM bus. The bus packing layer circuit can pack custom interfaces corresponding to all configuration registers in the operation layer circuit into a universal and standard SRAM bus interface, and the SRAM bus interface can be accessed to an SRAM bus so that all configuration register interfaces in the operation layer circuit can communicate with the SRAM bus, so that an I3C communication controller can be hung on a host system such as a Central Processing Unit (CPU) or a Microcontroller (MCU) system through the SRAM bus, and the connection between the I3C communication controller and the host system is simplified on the premise of ensuring the flexibility of the I3C communication controller, and a universal and flexible bus connection mode is provided. It can be understood that when the bus packaging layer circuit packages the register interface into the SRAM bus interface, the bus packaging layer circuit needs to complete the functions of base address configuration, address decoding, read-write control, data storage, interrupt control, etc. to ensure that the control function of the I3C communication controller can be realized.
In the I3C interface circuit compatible with the SRAM bus provided in this embodiment, N configuration registers connected to the I3C communication controller are provided on the operation layer circuit, and a register interface corresponding to each configuration register is connected to the bus packaging layer circuit, so that the bus packaging layer circuit packages the register interfaces into an SRAM bus interface, so as to connect to the SRAM bus through the SRAM bus interface, so that the I3C communication controller can communicate with the host system through the SRAM bus, and on the premise of ensuring the flexibility of the I3C communication controller, the connection between the I3C communication controller and the host system is simplified, and a universal and flexible bus connection manner is provided, so that the I3C bus device has wider compatibility.
In one embodiment, as shown in fig. 2, the bus packet layer circuit includes an address decoder for implementing an address decoding function and a read/write controller for implementing a data read/write function, and both the address decoder and the read/write controller are connected to the configuration register.
The address decoder is a circuit arranged on the bus packaging layer circuit and used for completing an address decoding function so as to obtain the address of the current device connected to the SRAM bus. The address decoder is connected with each configuration register in the operation layer circuit, so that the address decoder can know the address of each configuration register, and the corresponding configuration register can be controlled correspondingly in the following process. The read-write controller is a circuit which is arranged on a bus packaging layer circuit and is used for being matched with a configuration register so as to realize the functions of read-write control, data storage, interrupt control and the like.
In this embodiment, the actual address of each configuration register is determined by the address decoder, and the register interfaces corresponding to each configuration register in the operation layer circuit are packaged into the SRAM bus interface capable of communicating with the SRAM bus by the read-write control of the read-write controller, so as to ensure that the I3C communication controller can communicate with the SRAM bus, simplify the connection between the I3C communication controller and the host system on the premise of ensuring the flexibility of the I3C communication controller, and provide a universal and flexible bus connection mode.
In one embodiment, as shown in FIG. 2, the operation layer circuitry includes a CSR register set for addressing workflow control issues and a data buffer register set for addressing data exchange issues. In this embodiment, the CSR register group includes 1 base register for obtaining a start address and N-k-1 CSR registers for implementing a control function, and the data buffer register group includes k data buffer registers for implementing a data buffer function. In this embodiment, the base address register may be understood as a CSR register dedicated to acquiring the start address of the current device for solving the workflow control. Since the operation layer circuit comprises at least one data buffer register, k ≧ 1.
In one embodiment, the CSR registers include a base configuration register, a call configuration register, a presorting register, an SDR message length register, a DDR message length register, a static address register, a byte transfer counter, a word transfer counter, an SDR call address register, a DDR call address register, a read-write buffer pointer register, a buffer pointer reset register, a status register, and an interrupt identification register. Specifically, the names, offsets and functions of each custom configuration register in the operation layer circuit are shown in the following table one:
table-register information table
As shown in table one, in the operation layer circuit, the following configuration registers and their corresponding functions are set as follows:
a first basic control register connected with the I3C communication controller is arranged and used for configuring a system clock of the I3C bus.
A second basic control register connected with the I3C communication controller is provided for configuring the speed of the I3C bus.
A call control register connected to the I3C communication controller is provided for initiating an I3C communication.
A hang-up control register connected to the I3C communication controller is provided for terminating the I3C communication.
A prescaler register connected to the I3C communication controller is provided for configuring the frequency of the SCL on the I3C bus.
An SDR message length register and a DDR message length register which are connected with the I3C communication controller are arranged and used for determining the length of the SDR message and the DDR message in one communication.
A static address register is provided in communication with the I3C communication controller for configuring the static address of the I3C communication controller.
A Byte transmission counter connected to the I3C communication controller is provided for obtaining the number of SDR bytes (bytes) that the I3C bus has transmitted.
A word transfer counter connected to the I3C communication controller is provided for obtaining the number of DDR words (Double bytes) that have been transferred over the I3C bus.
And an SDR calling address register and a DDR calling address register which are connected with the I3C communication controller are arranged and used for respectively configuring the addresses of target equipment in the SDR and DDR communication processes.
And setting a read-write buffer pointer register (namely register groups such as Cache _ wptrL, Cache _ wptrH, Cache _ rptrL, Cache _ rptrH, Cache pointer register and the like in the table I) for determining the state of speed data buffer and matching with the number of bytes or words transmitted to obtain the exact position of a to-be-transmitted/cached in the data buffer register.
A status register connected to the I3C communication controller is provided for obtaining the current status of the I3C communication controller.
And a first interrupt identification register and a second interrupt identification register which are connected with the I3C communication controller are arranged and used for acquiring interrupt events generated on the I3C bus.
In this embodiment, by configuring the CSR registers capable of implementing different functions connected to the I3C communication controller, the I3C communication controller can implement corresponding functions through different CSR registers, so that the I3C communication controller has richer functions, and the application range of the I3C bus device is improved.
In order to illustrate how the CSR register in the operation layer circuit performs the control process of the I3C communication controller, the following description will take the I3C communication controller to implement dynamic address allocation as an example, and the implementation process includes the following steps:
s101: initializing and setting an operation layer circuit;
s102: setting operation when no response exists;
s103: reading the current value of the cache _ rptr corresponding to the read buffer pointer in the read-write buffer pointer register, and specifically reading the current values of the cache _ rptrL and the cache _ rptrH;
s104: determining whether the current value of the read buffer pointer needs to be reset according to the user requirement; if yes, resetting the read buffer pointer and acquiring an updated current value; if not, executing step S105;
s105: configuring SDR byte number;
s106: filling a public broadcast command address header, an ENTDAA command and a pre-allocated dynamic address;
s107: initiating an I3C communication through a call control register based on the pre-assigned dynamic address;
s108: judging an interrupt state based on the interrupt identifier register so that the I3C communication controller processes the interrupt according to the interrupt state;
s109: after receiving the interrupt completion notification, reading a cache _ wptr current value corresponding to a write buffer pointer in a read-write buffer pointer register, and specifically reading current values of a cache _ wptrL and a cache _ wptrH;
s110: reading the value of a byte transmission counter;
s111: acquiring an initial address, wherein the initial address is the current value of cache _ wptr and the value of a byte transmission counter;
s112: and reading data from the data buffer register, and acquiring a 64-bit ID sent by the device Slave to realize the purpose of dynamically allocating addresses to the device Slave.
As shown in fig. 3, the SARM bus in the present embodiment includes a system reset bus, a system clock bus, a write enable bus, a data input bus, an address bus, and a data output bus.
Specifically, the input end of the base address register is connected to the data input bus, and the output end is connected to the address decoder and the read/write controller, and is configured to obtain a start address of a current device on the data input bus, and send the start address to the address decoder and the read/write controller. The input end of the base address register is connected with a data input bus, and the starting address of the current device mounted on the bus can be determined according to data input by the data input bus. Furthermore, the input end of the base address register is also connected with a system clock bus, so that the base address register can obtain the system clock input by the system clock bus.
The base register stores the starting address of the current device in the entire address space of the SRAM bus. Assuming a 16-bit address-wide SRAM bus with address lines from 0x0000 to 0xffff as its entire address space, different devices attached to the SRAM bus may occupy a portion of the entire address space, so that the starting address of the current device corresponding to the data input bus in the entire address space can be determined. It will be appreciated that the base register may send the start address to the address decoder to decode the actual addresses of the CSR register and the data buffer register of the operating layer circuit configuration; and the starting address is sent to the read-write controller, so that the read-write controller performs read-write control operation on the corresponding CSR register and the data buffer register based on the starting address, and the bus packaging layer circuit can package the register interfaces of all the configuration registers into an SRAM bus interface.
Specifically, the input ends of the CSR register and the data buffer register are connected to an address decoder, and the output ends are connected to the read/write controller, so that the address decoder obtains the actual addresses of the CSR register and the data buffer register, and the read/write controller performs read/write control based on the actual addresses. That is, the register interfaces corresponding to the CSR register and the data buffer register in the operation layer circuit are respectively connected to the address decoder and the read/write controller, so that the address decoder performs address decoding on the corresponding register to determine the actual address; and then the read-write controller performs data reading or data writing and other operations on the corresponding register according to the actual address so as to fulfill the aim of communication between the register and the SRAM bus.
As shown in fig. 3, the inputs of the CSR register and the data buffer register are also connected to the system clock bus and the system reset bus. The input ends of the CSR register and the data buffer register are respectively connected with a system clock bus and used for acquiring a system clock input by the system clock bus. The CSR register and the data buffer register are respectively connected with the system reset bus and used for resetting the system according to a reset signal sent by the system reset bus so as to realize the reset function.
As shown in fig. 3, the address decoder includes 1 base address logic gate, N-1 decoding adders and N-1 decoding logic gates, each decoding adder being connected to a decoding logic gate. Each decoding adder and a decoding logic gate are matched to form an address decoding component for decoding a CSR register or a data buffer register to obtain a corresponding actual address of the CSR register or the data buffer register. I.e., each address decode unit matches a CSR register or data buffer register.
The base address logic gate is connected with the base address register to obtain the initial address by matching with the base address register. As shown in fig. 3, the input end of the base address logic gate is connected to the address bus, the write enable bus and the base address register, and the output end is connected to the base address register, and is configured to generate a corresponding control signal according to signals input by the address bus and the write enable bus, and send the control signal to the base address register, so that the base address register obtains the start address, and sends the start address to the address decoder and the read/write controller.
The input end of each current decoding adder is connected with the base address register or the previous decoding adder, the output end of each current decoding adder is connected with a current decoding logic gate or the current decoding logic gate and the next decoding adder, and the current decoding adder is used for acquiring the current register actual address corresponding to the CSR register or the data buffer register connected with the current decoding logic gate according to the initial address or the previous register actual address and inputting the current register actual address into the current decoding logic gate or the current decoding logic gate and the next decoding adder. It will be appreciated that since the input of each current decoding adder is connected to the last decoding adder, the output of each current decoding adder except the last current decoding adder is connected to the input of the next decoding adder to input the current register real address of the current decoding adder as the last register real address to the input of the next decoding adder. The current decoding adder is an adder for decoding a current register (a CSR register or a data buffer register), the previous decoding adder is a decoding adder connected to an input terminal of the current decoding adder, and the next decoding adder is a decoding adder connected to an output terminal of the current decoding adder. The current decode logic gate is a logic gate coupled to the current decode adder. It can be understood that, if a next decoding adder exists in a certain current decoding adder, the output end of the current decoding adder is connected with the current decoding logic gate and the next decoding adder; if a certain current decoding adder does not have a next decoding adder, the output end of the current decoding adder is connected with the current decoding logic gate.
Specifically, the address decoder includes N-1 address decoding elements arranged in sequence, for example, in the circuit shown in FIG. 3, in a top-to-top order. When the 1 st address decoding component works, the input end of the current decoding adder 1 is connected with the base address register, and the output end is connected with the input ends of the current decoding logic gate 1 and the next decoding adder 2, and is used for acquiring the current register actual address D _1 corresponding to the CSR register or the data buffer register connected with the current decoding logic gate 1 according to the initial address input by the base address register, and sending the current register actual address D _1 to the current decoding logic gate 1. And sends the current register real address D _1 as the last register real address to the next decoding adder 2. Correspondingly, when the 2 nd address decoding component operates, the input end of the current decoding adder 2 is connected to the output end of the previous decoding adder 1, and the output end is connected to the input ends of the current decoding logic gate 2 and the next decoding adder 3, and is configured to obtain, according to the previous register actual address 1 output by the previous decoding adder 1, the current register actual address D _2 corresponding to the CSR register or the data buffer register connected to the current decoding logic gate 2, send the current register actual address D _2 as the previous register actual address to the next decoding adder 3 … …, and so on, obtain the current register actual address corresponding to the N-1 st CSR register or the data buffer register.
In this embodiment, an address decoder formed by a chain adder is adopted in the address decoder, that is, except that the first current decoding adder 1 is connected with a base address register to obtain an initial address; the input terminals of the remaining N-2 current decoding adders may be connected to the output terminal of the previous decoding adder to calculate the current register real address of the CSR register or the data buffer register corresponding to the current decoding adder according to the previous register real address output by the previous decoding adder. This chain-like structure, except that the first current decoding adder 1 needs a complete addition function, the remaining N-2 current decoding adders need only perform a power of 2 addition function, which can be typically 0, 1 and 2 of 2, depending on the addressing bit width of the target CPU bus system. The decoding adder with the reinforcement constant value of 2 power has simple circuit structure and can effectively save the consumption of logic resources. Compared with the conventional method, each real address is added from the start address, the offset to be added is larger and larger, and the bit width of the required real adder is larger and larger, so that the address decoder adopting the chain adder provided by the embodiment can save the consumption of logic resources.
As shown in fig. 3, each current decoding adder includes a first input terminal, a second input terminal, and an addition output terminal. The first input end of the current decoding adder is connected with the output end of the base address register or the output end of the last decoding adder and used for receiving the starting address or the actual address of the last register. A second input is coupled to the I3C communication controller for receiving an offset increment corresponding to a CSR register or data buffer register coupled to the current decode logic gate. And the addition output end is connected with the decoding logic gate or the current decoding logic gate and the next decoding adder and is used for outputting the current register real address obtained based on the starting address or the previous register real address and the offset increment. It will be appreciated that since the first input of each current decoding adder is connected to the output of the last decoding adder, the addition output of each current decoding adder except the last current decoding adder is connected to the first input of the next decoding adder to input the current register real address of the current decoding adder as the last register real address to the first input of the next decoding adder. It can be understood that, if the first input terminal of the current decoding adder is connected to the base register, the addition output terminal thereof outputs the current register actual address obtained based on the start address and the offset increment; if the first input end of the current decoding adder is connected with the last decoding adder, the addition output end of the current decoding adder outputs the current register actual address obtained based on the last register actual address and the offset increment. It can be understood that, if a next decoding adder exists in a certain current decoding adder, the output end of the current decoding adder is connected with the current decoding logic gate and the next decoding adder; if a certain current decoding adder does not have a next decoding adder, the output end of the current decoding adder is connected with the current decoding logic gate.
As shown in fig. 3, when the 1 st address decoding component operates, the first input terminal of the current decoding adder 1 is connected to the base register, and is configured to receive the start address input by the base register; the second input end is connected with the I3C communication controller and is used for receiving the offset increment 1 corresponding to the CSR register 1 input by the I3C communication controller; the addition output end is connected with the first input ends of the current decoding logic gate 1 and the next decoding adder 2; and the adder is configured to perform addition operation according to the start address and the offset increment 1, thereby obtaining a current register real address D _1 corresponding to the CSR register 1, send the current register real address D _1 to the current decoding logic gate 1, and send the current register real address D _1 as a previous register real address to the next decoding adder 2.
When the 2 nd address decoding component works, the first input end of the current decoding adder 2 is connected with the addition output end of the last decoding adder 1 and is used for receiving the actual address of the last register input by the last decoding adder 1; the second input end is connected with the I3C communication controller and is used for receiving the offset increment 2 corresponding to the CSR register 2 input by the I3C communication controller; the addition output end is connected with the first input ends of the current decoding logic gate 2 and the next decoding adder 3; and the adder is configured to perform addition operation according to the previous register real address and the offset increment 2, thereby obtaining a current register real address D _2 corresponding to the CSR register 2, send the current register real address D _2 to the current decoding logic gate 2, and send the current register real address D _2 as the previous register real address to the next decoding adder 3.
In analogy, when the (N-1) th address decoding component works, the first input end of the current decoding adder N-1 is connected with the addition output end of the last decoding adder N-2 and is used for receiving the actual address of the last register input by the last decoding adder N-2; the second input end is connected with the I3C communication controller and is used for receiving the offset increment N-1 corresponding to the data buffer register N-1 input by the I3C communication controller; because the current decoding adder N-1 does not have a corresponding next decoding adder, the addition output end is only connected with the current decoding logic gate N-1; and the current decoding logic gate is used for performing addition operation according to the actual address of the previous register and the offset increment N-1 so as to obtain the actual address D _ N-1 of the current register corresponding to the data buffer register and sending the actual address D _ N-1 of the current register to the current decoding logic gate N-1.
Correspondingly, the input end of the current decoding logic gate is connected with the address bus, the write enable bus and the current decoding adder; the output end is connected with the CSR register or the data buffer register and is used for controlling the CSR register or the data buffer register according to the comparison result of the target address input by the address bus and the actual address of the current register. That is, the output terminal of the current decoding logic gate may be connected to the CSR register, and is configured to control the CSR register according to the comparison result between the target address input by the address bus and the actual address of the current register and the signal input by the write enable bus. The output end of the decoding logic gate can also be connected with a data buffer register for controlling the data buffer register according to the comparison result of the target address input by the address bus and the actual address of the current register and the signal input by the write enable bus. Further, the input terminal of the current decoding logic gate may be further connected to a data input bus for receiving data input from the data input bus.
Specifically, each current decoding logic gate compares the binary bit of the target address A input by the address bus with the binary bit of the current register actual address B output by the current decoding adder, and if the two are all equal, the comparison result is true; if they are not equal, the comparison result is false. If the comparison result is true, and the write enable high level of the write enable bus input has a data bit of 1, outputting 1 to the CSR register or the data buffer register connected with the current decoding logic gate; if the comparison result is true, and the write enable input by the write enable bus is low level, and the data bit is 0, then the output to the CSR register or the data buffer register connected with the current decoding logic gate is 0; in other cases, the register is kept unchanged, so that the current decoding logic gate can control the CSR register or the data buffer register according to the comparison result of the target address and the real address and the signal input by the write enable bus.
In one embodiment, the read/write controller includes a control subtractor, a control logic gate, a data selector, and a data output register. The control subtracter is connected with the base register and the data selector and used for obtaining the current offset according to the initial address output by the base register and sending the current offset to the data selector, namely the control subtracter can calculate the current offset according to the initial address and send the current offset to the data selector. The control logic gate is connected with the SRAM bus, the base address register and the data output register and used for obtaining a target enabling signal according to a signal and a starting address input by the SRAM bus and sending the target enabling signal to the data output register, wherein the target enabling signal can be a writing enabling signal or a reading enabling signal. The data selector is connected with the configuration register, the control subtracter and the data output register and used for outputting a selection signal to the data output register according to the register output of the configuration register and the current offset, and the register output corresponding to the configuration register refers to data output to the data selector through the register interface corresponding to the configuration register. And the data output register is connected with the SRAM bus, the data selector and the control logic gate and is used for performing read-write control according to the selection signal and the target enabling signal. Namely, the data output register can realize data reading or data writing control of the SRAM bus and the CSR register according to the selection signal and the target enabling signal, so that the I3C communication controller is communicated with the SRAM bus. The read-write controller is formed by controlling the matching of the subtracter, the control logic gate, the data selector and the data output register, and the configuration register connected with the read-write controller is controlled to communicate with the SRAM bus, so that the aim of packaging the register interface of the configuration register into the SRAM bus interface is fulfilled.
As shown in fig. 3, the first input terminal of the control subtractor is connected to the address bus for receiving the target address input by the address bus; the second input end is connected with the base address register and used for receiving the starting address; the subtraction output end is connected with the data selector and used for obtaining the current offset according to the target address and the starting address and sending the current offset to the data selector. The control subtracter can perform subtraction operation according to a target address input by an address bus and a starting address input by a base register to obtain the current offset, and the current offset is sent to the data selector.
The input end of the control logic gate is connected with the address bus, the write enable bus and the base address register, and the output end of the control logic gate is connected with the data output register and used for acquiring a target enable signal according to a target address, a write enable signal input by the write enable bus and a starting address and sending the target enable signal to the data output register. The address bus, the write enable bus and the base register are connected to the input end of the control logic gate together, so that the control logic gate compares and judges whether the target address input by the address bus is between the initial address input by the base register and the initial address plus the number of CSR registers, and the output of the control logic gate is 1. The control logic gate is mainly used for acquiring a corresponding target enabling signal according to an enabling signal input by the write enabling bus when the address bus selects a current CSR register (namely, a target address is consistent with an actual address of the CSR register), and sending the target enabling signal to the data output register. For example, when the write enable bus is disabled, i.e. a CSR register is read, a high enable signal may be output to the data output register to enable the CSR register to store data on the SRAM data bus.
And the first input end of the data selector is connected with the output ends of the N configuration registers, the second input end of the data selector is connected with the subtraction output end of the control subtracter, and the subtraction output end of the data selector is connected with the data output register and used for acquiring a selection signal according to the current offset and sending the selection signal to the data output register. The first input end of the data selector is connected with all configuration registers arranged in the operation layer circuit, such as a base address register, N-k-1 CSR registers, k data buffer registers and the like, and is used for receiving register outputs of the configuration registers; the second input end is connected with the subtraction output end of the control subtracter and used for receiving the current offset of the subtraction output end, determining a selection signal output to the corresponding register according to the current offset and sending the selection signal to the data output register.
The input end of the data output register is connected with the data selector, the control logic gate and the system clock bus, and the output end of the data output register is connected with the data output bus and used for carrying out data read-write control on the data output bus according to the selection signal input by the data selector and the target enabling signal input by the control logic gate. Specifically, the actual address of the current register corresponding to each CSR register is calculated through a decoding adder; when the target address input by the address bus matches the current register real address corresponding to a CSR register, the corresponding target CSR register may be determined according to the selection signal. After the target CSR register is determined, if the target enable signal input by the control logic gate is a high-level signal, the data output register controls the target CSR register to store data on the SRAM bus so as to realize data writing operation; and if the target enable signal input by the control logic gate is a low-level signal, the data output register latches the target CSR register and outputs corresponding data to the SRAM bus so as to realize data reading operation.
In the bus packing layer circuit provided in this embodiment, an address decoding function, a read-write function, a base address configuration function, a data storage function, and an interrupt control function can be implemented, so that it is ensured that register interfaces of all configuration registers are packed into an SRAM bus interface by using the bus packing layer circuit, thereby implementing communication with an SRAM bus.
Specifically, the address decoding function can be realized by an address decoder, that is, each current decoding adder obtains the actual address of the current register based on the initial slope input by the base register or the actual address of the previous register input by the previous decoding adder through N-1 decoding adders sequentially connected with the base register, so as to realize the address decoding function. When the address bus hits the actual address of the current register corresponding to a certain configuration register (namely, the target address is matched with the actual address), the enable signal input based on the write enable bus; when the enabling signal is write, writing data on the SRAM bus into a corresponding CSR register; when the enable signal is read, the data of the corresponding CSR register is written into the data output register, and the read data is also placed on the SRAM bus because the CSR register is connected with the data output bus, so as to realize the read-write control function. It can be understood that, when the bus package layer circuit can implement the read-write function, the start address of the base address register can be changed through the write operation to implement the base address configuration function. The data storage function is similar to the read-write control function, except that the continuous CSR register is replaced by a common memory, and the read-write control function is adopted to store and read data in the common memory. The interrupt control function is that some CSR registers are configured to be an interrupt switch register (which can be the first interrupt identifier register) and an interrupt state register (which can be the second interrupt identifier register), and the interrupt switch register is set to be 1, so that the corresponding interrupt switch is turned on; when an interrupt occurs, the interrupt state register is read to inquire which interrupt occurs, and 0 is written into the interrupt state register to clear the purpose of the interrupt.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (8)
1. An SRAM bus compatible I3C interface circuit, comprising:
the operation layer circuit is connected with the I3C communication controller and comprises N configuration registers which are connected with the I3C communication controller and used for realizing a custom function, and each configuration register corresponds to a register interface and is used for communicating with the I3C communication controller; the operation layer circuit comprises 1 base address register for obtaining a starting address, N-k-1 CSR registers for realizing a control function and k data buffer registers for realizing a data buffer function;
the bus packing layer circuit is connected with the N configuration registers on the operation layer circuit, is connected with the SRAM bus, and is used for packing the register interfaces corresponding to the configuration registers into the SRAM bus interfaces so as to realize communication with the SRAM bus; the bus packaging layer circuit comprises an address decoder for realizing an address decoding function and a read-write controller for realizing a data read-write function, and the address decoder and the read-write controller are both connected with the configuration register;
the address decoder comprises 1 base address logic gate, N-1 decoding adders and N-1 decoding logic gates, and each decoding adder is connected with one decoding logic gate;
the base address logic gate is connected with the base address register to cooperate with the base address register to obtain the initial address;
the input end of each current decoding adder is connected with the base address register or the previous decoding adder, and the output end of each current decoding adder is connected with a current decoding logic gate or the current decoding logic gate and the next decoding adder, and is used for acquiring a current register actual address corresponding to the CSR register or the data buffer register connected with the current decoding logic gate according to the starting address or the previous register actual address, and inputting the current register actual address to the current decoding logic gate or the current decoding logic gate and the next decoding adder.
2. The SRAM bus compatible I3C interface circuit of claim 1, wherein the CSR registers comprise a base configuration register, a call configuration register, a presorting register, an SDR message length register, a DDR message length register, a static address register, a byte transfer counter, a word transfer counter, an SDR call address register, a DDR call address register, a read-write buffer pointer register, a buffer pointer reset register, a status register, and an interrupt identification register.
3. The SRAM bus compatible I3C interface circuit of claim 1, wherein the base register has an input coupled to a data input bus and an output coupled to the address decoder and the read/write controller for obtaining a start address associated with a current device on the data input bus and sending the start address to the address decoder and the read/write controller;
the input ends of the CSR register and the data buffer register are connected with the address decoder, and the output ends of the CSR register and the data buffer register are connected with the read-write controller, so that the address decoder obtains the actual addresses of the CSR register and the data buffer register, and the read-write controller performs read-write control based on the actual addresses.
4. The SRAM bus compatible I3C interface circuit of claim 1, wherein the address decoder comprises 1 base address logic gate, N-1 decode adders and N-1 decode logic gates, each of the decode adders being coupled to one of the decode logic gates;
the base address logic gate is connected with the base address register to cooperate with the base address register to obtain the initial address;
the input end of each current decoding adder is connected with the base address register or the previous decoding adder, and the output end of each current decoding adder is connected with a current decoding logic gate or the current decoding logic gate and the next decoding adder, and is used for acquiring a current register actual address corresponding to the CSR register or the data buffer register connected with the current decoding logic gate according to the starting address or the previous register actual address, and inputting the current register actual address to the current decoding logic gate or the current decoding logic gate and the next decoding adder.
5. The SRAM bus compatible I3C interface circuit of claim 1,
the first input end of the current decoding adder is connected with the output end of the base address register or the output end of the previous decoding adder and used for receiving a starting address or a practical address of the previous register; a second input terminal is connected to the I3C communication controller, and is configured to receive an offset increment corresponding to the CSR register or the data buffer register connected to the current decoding logic gate; the addition output end is connected with the current decoding logic gate or the current decoding logic gate and the next decoding adder and is used for outputting the current register actual address obtained based on the initial address or the previous register actual address and the offset increment;
the input end of the current decoding logic gate is connected with an address bus, a write enable bus and a current decoding adder; and the output end of the register is connected with the CSR register or the data buffer register and is used for controlling the CSR register or the data buffer register according to the comparison result of the target address input by the address bus and the actual address of the current register.
6. The SRAM bus compatible I3C interface circuit of claim 1, wherein the read/write controller comprises a control subtractor, a control logic gate, a data selector, and a data output register;
the control subtracter is connected with the base register and the data selector and used for acquiring a current offset according to an initial address output by the base register and sending the current offset to the data selector;
the control logic gate is connected with an SRAM bus, the base address register and the data output register and is used for acquiring a target enabling signal according to a signal input by the SRAM bus and the initial address and sending the target enabling signal to the data output register;
the data selector is connected with the configuration register, the control subtracter and the data output register and is used for outputting a selection signal to the data output register according to the register output of the configuration register and the current offset;
the data output register is connected with the SRAM bus, the data selector and the control logic gate and is used for performing read-write control according to the selection signal and the target enabling signal.
7. The SRAM bus compatible I3C interface circuit of claim 6,
the first input end of the control subtracter is connected with an address bus and used for receiving a target address input by the address bus; the second input end is connected with the base address register and used for receiving the starting address; the subtraction output end is connected with the data selector and used for obtaining the current offset according to the target address and the starting address and sending the current offset to the data selector;
the input end of the control logic gate is connected with the address bus, the write enable bus and the base address register, and the output end of the control logic gate is connected with the data output register, and is used for acquiring a target enable signal according to the target address, a write enable signal input by the write enable bus and the initial address, and sending the target enable signal to the data output register;
a first input end of the data selector is connected with output ends of the N configuration registers, a second input end of the data selector is connected with a subtraction output end of the control subtracter, and the subtraction output end of the data selector is connected with the data output register and used for acquiring a selection signal according to the current offset and sending the selection signal to the data output register;
the input end of the data output register is connected with the data selector and the control logic gate, and the output end of the data output register is connected with the data output bus and used for carrying out data read-write control with the data output bus according to a selection signal input by the data selector and a target enabling signal input by the control logic gate.
8. The SRAM bus compatible I3C interface circuit of claim 6, wherein the input terminals of the configuration register and the data output register are further coupled to a system clock bus; and the input ends of the CSR register and the data buffer register are also connected with a system reset bus.
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