CN101183347A - Bridge circuit of self-adapting velocity matching bus - Google Patents
Bridge circuit of self-adapting velocity matching bus Download PDFInfo
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- CN101183347A CN101183347A CNA2006101183293A CN200610118329A CN101183347A CN 101183347 A CN101183347 A CN 101183347A CN A2006101183293 A CNA2006101183293 A CN A2006101183293A CN 200610118329 A CN200610118329 A CN 200610118329A CN 101183347 A CN101183347 A CN 101183347A
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Abstract
The invention relates to a bridge circuit for self adaptive rate matching bus, which is characterized in that: bus conversion rate is automatically matched through detecting frequency ratio between high speed system bus clock (HCLK) and low speed peripheral bus clock (PCLK), thereby completing automatic bridging for AHB bus and APB bus. As an independent IP, the bus bridging circuit can be widely applied in design of SOC embedded type system chip based on AMBA bus frame.
Description
Technical field
The present invention relates to the chip design art field, be specifically related to a kind of bridgt circuit of self-adapting velocity matching bus.The present invention has realized the automatic bridge joint conversion of AMBA2.0 bus architecture high speed system bus (ahb bus) and low speed peripheral bus (APB bus), can be widely used in the design of SOC (the System on a Chip) chip based on the AMBA2.0 bus architecture.
Background technology
In the prior art, common APB bus bridge circuit has following several form:
One, HCLK (ahb bus clock) and PCLK (APB bus clock) are with APB bus bridge circuit frequently
Two, the fixing APB bus bridge circuit of frequency division (PCLK is the fixedly frequency division of HCLK)
Three, the APB bus bridge circuit of configurable divide ratio
First kind of APB bus bridge circuit is the simplest, be easy to realize, but very flexible is difficult to satisfy the requirement of different peripheral to frequency, and because APB Peripheral Interface and system's ahb bus are operated in same frequency, power consumption is higher in the time of can causing each Peripheral Interface work.
Second kind of APB bus bridge circuit reduced the frequency of operation of APB Peripheral Interface, and circuit is realized also than being easier to, but same very flexible is difficult to satisfy the requirement of different peripheral to frequency.
The third APB bus bridge circuit can satisfy the requirement of different peripheral to frequency of operation, and shortcoming is that every kind of frequency division all needs software that the APB bus bridge is configured, and has increased the complexity of software.
Summary of the invention
Purpose of the present invention mainly is the interface circuit that will solve between AMBA2.0 bus architecture high speed system bus and the low speed peripheral bus, and a kind of bridgt circuit of self-adapting velocity matching bus is provided.
The present invention is an advanced microcontroller bus architecture standard 2.0 (AMBA:Advanced Microcontroller Bus ArchitectureSpecification 2.0) of using Britain ARM company, high speed system bus is wherein followed Advanced High-performance Bus (AHB:Advanced High-performance Bus) agreement, and the low speed peripheral bus is followed Advanced Peripheral Bus (APB:Advanced Peripheral Bus) agreement.The present invention has finally realized the automatic bridge joint (Bridge) of ahb bus and APB bus.
The bridgt circuit of a kind of self-adapting velocity matching bus provided by the invention is by detecting the clock frequency ratio of AHB high-speed bus clock (HCLK) and APB low speed peripheral bus clock (PCLK) automatically, realized the automatic coupling of AHB and APB clock rate, with system to the read-write operation sequential of peripheral hardware from the AHB protocol conversion to the APB agreement, thereby the realization system is to the read-write operation of peripheral hardware.
The technical scheme of the bridgt circuit of a kind of self-adapting velocity matching bus provided by the invention is: 1, the scope of the HCLK of design support and the frequency ratio between the PCLK is the arbitrary integer between the 1-63.In this scope, system can dispose the divider ratio of PCLK in the PLCK clock generation circuit arbitrarily.Frequency ratio (the R of the HCLK/PCLK of this bus bridge
HCLK/PCLK) testing circuit finishes the detection of frequency ratio between HCLK and the PCLK automatically, thereby mate the switching rate between high speed ahb bus and the low speed APB bus automatically.2, two bus bridge control state machine of design are according to the frequency ratio (R of detected HCLK/PCLK
HCLK/PCLK) finish the bus bridge function from AHB to APB.The one, ahb bus transmission control state machine (AHB_FSM), another is an APB bus transfer control state machine (APB_FSM).Two state machines are by shaking hands, and will be transformed into the read-write (following the APB agreement) of APB bus to effective read-write (following the AHB agreement) of peripheral hardware from system's ahb bus, and Peripheral Interface is is effectively read and write.
More particularly, the bridgt circuit that the invention provides a kind of self-adapting velocity matching bus mainly comprises:
One HCLK/PCLK clock frequency ratio testing circuit, it finishes detection to the frequency ratio between HCLK and the PCLK in per two PCLK clock period.In first clock period, 6 binary counters are counted as counting clock with HCLK, the result of counting deposits in the register with HCLK when first PCLK clock period finishes, and the value of this register is the clock frequency ratio (R between HCLK and the PCLK
HCLK/PCLK).6 binary counting maximal values are 63, if need to enlarge PCLK frequency detecting scope, can increase number of counter bits, and the maximum PCLK divider ratio of 7 digit counter supports is that the maximum PCLK divider ratio of 127,8 digit counter supports is 255, and the rest may be inferred.Second clock period, with PCLK with R
HCLK/PCLKBe latched in another register, as reference value (Ref_R
HCLK/PCLK).When system changes the PCLK frequency, R when first PCLK clock period finishes
HCLK/PCLKCan be updated, like this at second clock period, R
HCLK/PCLKBe not equal to Ref_R
HCLK/PCLK, circuit can produce a reset signal, AHB is resetted to the bridgt circuit of APB, at the 3rd clock period (new R
HCLK/PCLKSense cycle), because Ref_R
HCLK/PCLKBe updated, equal R
HCLK/PCLK, bridgt circuit can begin operate as normal under new PCLK frequency.
According to the clock frequency ratio between detected HCLK and the PCLK, this bus bridge circuit is by an ahb bus transmission control state machine AHB_FSM and an APB bus transfer control state machine APB_FSM, with system to the read-write operation sequential of peripheral hardware from the AHB protocol conversion to the APB agreement.AHB_FSM detects the effectively transmitted signal and the feedback of status that receives from APB_FSM from ahb bus, APB_FSM then is used for receiving the effective read-write control signal from AHB_FSM output, convert effective read-write of following the APB agreement to, thereby finish the conversion of AHB and APB bus protocol peripheral hardware.
For example, the AHB_FSM state machine state is described below:
The AHB_IDLE:AHB bus free time;
AHB_WWAIT:AHB writes wait;
The AHB_WDRDY:AHB write data is ready to;
The AHB_WRITEPW:AHB write address is set up state, and follow-up is write operation;
The AHB_WRITEPR:AHB write address is set up state, and follow-up is read operation;
AHB_WWAITPW:AHB writes waiting status, and follow-up is write operation;
AHB_WWAITPR:AHB writes waiting status, and follow-up is read operation;
AHB_WWAITNP:AHB writes waiting status, no subsequent reads write operation;
The AHB_WRITENP:AHB write address is set up state, and no subsequent reads is write and bestirred oneself;
AHB_WEND:AHB writes end;
AHB_LDPRA:AHB reads the address and loads (be write operation last time);
AHB_RWAIT:AHB reads waiting status;
AHB_READ:AHB reads the address and sets up state;
The AHB_RDRDY:AHB read data is ready to.
Wherein, the APB_FSM state machine state is described below:
The APB_IDLE:APB bus free time;
APB_RSETUP:APB reads the address and sets up state;
APB_RENABLE:APB read data enabled state;
The APB_WSETUP:APB write address is set up state;
APB_WENABLE:APB write data enabled state.
And, a peripheral hardware address decoding and data selector channel circuit, it can be deciphered 4 high addresses from ahb bus, produces the gating signal of 16 Peripheral Interfaces.If need to increase the peripheral hardware number, then need increase the AHB address bus high address number that participates in the peripheral hardware address decoding, can produce 32 peripheral hardware gating signals as 5,6 can produce 64 peripheral hardware address gating signals, and the like.Low order address then converts the address bus of APB bus to.On data path, can data be delivered to different peripheral hardwares and the data that read from different peripheral simultaneously according to the Peripheral Interface gating signal.
The beneficial effect of the bridgt circuit of a kind of self-adapting velocity matching bus provided by the invention is: detect the frequency ratio (R between HCLK and the PCLK automatically
HCLK/PCLK), system need not the clock division control register into the configure dedicated of this bus bridge circuit Peripheral Interface work clock PCLK; Guaranteeing HCLK/PCLK clock frequency ratio (R
HCLK/PCLK) be that system can change the PCLK frequency at any time under the prerequisite of round values (adopt Synchronization Design between system bus and the Peripheral Interface usually, the frequency of HCLK must be the integer of PCLK frequency).In case system changes the PCLK frequency, this bus bridge circuit only needs 2 to 3 PCLK clock period, will finish the detection to the PCLK frequency, and circuit promptly can begin operate as normal under new PCLK.
This shows, the invention provides a kind of high performance self-adaption velocity matching bus bridgt circuit, it is by detecting the frequency ratio between high speed system bus clock (HCLK) and the low speed peripheral bus clock (PCLK), automatically matching bus switching rate has been finished the automatic bridge joint of ahb bus and APB bus.This bus bridge circuit can be widely used in the design based on the SOC embedded system chip of AMBA2.0 bus architecture as an IP independently.
Below, describe details and working condition in conjunction with the accompanying drawings and embodiments in detail according to the concrete device of the present invention's proposition.
Description of drawings
Fig. 1: schematic block circuit diagram of the present invention;
Fig. 2: ahb bus transmission control state machine process flow diagram of the present invention;
Fig. 3: APB bus transfer control state machine process flow diagram of the present invention.
Embodiment
Shown in accompanying drawing 1-3, the bridgt circuit of a kind of self-adapting velocity matching bus provided by the invention mainly comprises:
One HCLK/PCLK clock frequency ratio testing circuit, it finishes detection to the frequency ratio between HCLK and the PCLK in per two PCLK clock period; In first clock period, a counter is counted as counting clock with HCLK, and the result of counting deposits in the register with HCLK when first PCLK clock period finishes, and the value of this register is the clock frequency ratio (R between HCLK and the PCLK
HCLK/PCLK);
Second clock period, with PCLK with R
HCLK/PCLKBe latched in another register, as reference value (Ref_R
HCLK/CLK); When system changes the PCLK frequency, R when first PCLK clock period finishes
HCLK/PCLKCan be updated, like this at second clock period, R
HCLK/PCLKBe not equal to Ref_R
HCLK/PCLK, circuit can produce a reset signal, AHB is resetted to the bridgt circuit of APB, at the 3rd clock period (new R
HCLK/PCLKSense cycle), because Ref_R
HCLK/PCLKBe updated, equal R
HCLK/PCLK, bridgt circuit can begin operate as normal under new PCLK frequency;
According to the clock frequency ratio between detected HCLK and the PCLK, this bus bridge circuit is by an ahb bus transmission control state machine AHB_FSM and an APB bus transfer control state machine APB_FSM, with system to the read-write operation sequential of peripheral hardware from the AHB protocol conversion to the APB agreement; AHB_FSM detects the effectively transmitted signal and the feedback of status that receives from APB_FSM from ahb bus, APB_FSM then is used for receiving the effective read-write control signal from AHB_FSM output, convert effective read-write of following the APB agreement to, thereby finish the conversion of AHB and APB bus protocol peripheral hardware;
And, a peripheral hardware address decoding and data selector channel circuit, it can be deciphered the high address from ahb bus, produces the gating signal of several Peripheral Interfaces; Low order address then converts the address bus of APB bus to, on data path, can data be delivered to different peripheral hardwares and the data that read from different peripheral according to the Peripheral Interface gating signal simultaneously.
The bridgt circuit of a kind of self-adapting velocity matching bus provided by the invention is as a functional module of SOC chip, and its final design object is to finish the production of silicon.Register transfer level code (RTL Code) the available Verilog of this bus bridge circuit or VHDL hardware description language are realized.When doing the SOC system integration, this IP of exampleization gets final product in the RTL code, does not need to do any code revision.When realizing with the electric design automation software design, can be according to designing requirement, be mapped to the technology library of different chip production producer, form the required normal data file of chip production, consign to producer and produce.The register transfer level code of this bus bridge circuit is not subjected to the restriction of production technology as a soft nuclear.
As mentioned above, the bridgt circuit of a kind of self-adapting velocity matching bus provided by the invention has been realized based on ahb bus in the SOC chip of AMBA2.0 standard to the automatic bridge joint of APB bus.
The bridgt circuit of a kind of self-adapting velocity matching bus provided by the invention is by detecting the clock frequency ratio of AHB high-speed bus clock (HCLK) and low speed peripheral bus clock (PCLK) automatically, realized the automatic coupling of AHB and APB clock rate, with system to the read-write operation sequential of peripheral hardware from the AHB protocol conversion to the APB agreement, thereby the realization system is to the read-write operation of peripheral hardware.
In the HCLK/PCLK clock frequency ratio testing circuit of the bridgt circuit of a kind of self-adapting velocity matching bus that the preferred embodiment of the present invention provides, in first clock period, 6 binary counters are counted as counting clock with HCLK, the result of counting deposits in the register with HCLK when first PCLK clock period finishes, and the value of this register is the clock frequency ratio (R between HCLK and the PCLK
HCLK/PCLK).6 binary counting maximal values are 63, and promptly the scope N of the frequency ratio between HCLK and the PCLK is the arbitrary integer between the 1-63.In this scope, system can dispose the divider ratio of PCLK in the PLCK clock generation circuit arbitrarily.
Explain the workflow of automatic bridge joint conversion with a plurality of embodiment below in conjunction with accompanying drawing.
Bus bridge workflow (N=1) during 1, with frequency
At first, HCLK/PCLK clock frequency ratio testing circuit can detect HCLK and the same frequency of PCLK.Behind the bus reset, AHB_FSM and APB_FSM are in bus idle state.
When idle condition, when the ahb bus write operation, owing to be with frequently, the next clock period is a cycle data, and next clock period AHB_FSM enters the AHB write data and is ready to state.Perhaps when read operation, next clock period AHB_FSM enters AHB and reads the address and set up state
Be ready to this clock period of state when AHB_FSM is in the AHB write data, set up if having subsequent write operation, next clock period AHB_FSM to enter write address, follow-up is the write operation state; Set up if having subsequent read operation, next clock period AHB_FSM to enter write address, follow-up is the read operation state; If no subsequent reads write operation, next clock period AHB_FSM enter write address and set up, no subsequent reads write operation state.
Set up when AHB_FSM is in the AHB write address, follow-up is this clock period of write operation state, owing to be that next clock period AHB_FSM enters write data and is ready to state with frequently.
Set up when AHB_FSM is in the AHB write address, follow-up is this clock period of read operation state, and next clock period AHB_FSM enters AHB and reads the address loading condition
Set up when AHB_FSM is in the AHB write address, no follow-up be this clock period of read-write operation state, as if new write operation is arranged, next clock period AHB_FSM enters write data and is ready to state at this moment; If new read operation is arranged, next clock period AHB_FSM enters AHB and reads the address loading condition; If no new read-write operation, next clock period AHB_FSM enters AHB and writes done state.
Write this clock period of done state when AHB_FSM is in AHB, next clock period AHB_FSM entered write data and was ready to state if new write operation is arranged this moment; If new read operation is arranged, next clock period AHB_FSM enters AHB and reads the address loading condition; If no new read-write operation, next clock period AHB_FSM enters the ahb bus idle condition.
Read this clock period of address loading condition when AHB_FSM is in AHB, next clock period AHB_FSM enters AHB and reads the address and set up state.
Read the address and set up this clock period of state when AHB_FSM is in AHB, next clock period AHB_FSM enters the AHB read data and is ready to state.
Be ready to this clock period of state when AHB_FSM is in the AHB read data, next clock period AHB_FSM entered write data and was ready to state if new write operation is arranged this moment; If having new read operation, next clock period AHB_FSM to enter AHB reads the address and sets up state; If no new read-write operation, next clock period AHB_FSM enters the ahb bus idle condition.
In AHB_FSM work, APB_FSM is monitoring the state of AHB_FSM and is doing corresponding action all the time in synchronous operation, and system is transformed on the APB bus from ahb bus the read-write of peripheral hardware, finishes the read and write access to peripheral hardware.
The APB_FSM default setting is an idle condition.When AHB_FSM was in write data and is ready to state, next clock period APB_FSM entered the APB write address and sets up state; When next AHB_FSM is that AHB reads to set up state, next clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next clock period APB_FSM still maintains idle condition.
When APB_FSM was in the APB write address and sets up state, at present clock period, write address and write data were sent on the APB bus, because with frequently, next clock period APB_FSM enters APB write data enabled state.
When APB_FSM was in APB write data enabled state, at present clock period, address and data still remained unchanged on the APB bus, and the APB enable signal is put height.Meanwhile, when AHB_FSM was in write data and is ready to state, next clock period APB_FSM entered the APB write address once more and sets up state; When next AHB_FSM is that AHB reads to set up state or AHB reads the address loading condition, next clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next clock period APB_FSM enters idle condition.
Read the address when setting up state when APB_FSM is in APB,, read the address and be sent on the APB bus, because with frequently, next clock period APB_FSM enters APB read data enabled state at present clock period.
When APB_FSM was in APB read data enabled state, at present clock period, the address still remained unchanged on the APB bus, and the APB enable signal is put height, and the APB Peripheral Interface sends back to data on the APB bus.Meanwhile, when next AHB_FSM is that AHB reads to set up state or AHB reads the address loading condition, next clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next clock period APB_FSM enters idle condition.
Bus bridge workflow (N=5) when 2, PCLK is HCLK 5 frequency divisions
At first, it is HCLK 5 frequency divisions that HCLK/PCLK clock frequency ratio testing circuit can detect PCLK, corresponding 5 HCLK of each PCLK clock period.Behind the bus reset, AHB_FSM and APB_FSM are in bus idle state.
When idle condition, when the ahb bus write operation, owing to be 5 frequency divisions, if present clock period is and corresponding the 4th clock period of current PC LK, then next clock period AHB_FSM enters the AHB write data and is ready to state, writes waiting status otherwise AHB_FSM enters AHB; When read operation, if the current HCLK clock period is and corresponding the 4th clock period of current PC LK that next clock period AHB_FSM enters AHB and reads the address and set up state, reads waiting status otherwise AHB_FSM enters AHB.
When AHB_FSM was in AHB and writes waiting status, HCLK count down to corresponding the 4th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write data and is ready to state.
Be ready to this clock period of state when AHB_FSM is in the AHB write data, if subsequent write operation is arranged, next clock period AHB_FSM enters and writes wait, and follow-up is the write operation state; If subsequent read operation is arranged, next clock period AHB_FSM enters and writes wait, and follow-up is the read operation state; If no subsequent reads write operation, next clock period AHB_FSM enters and writes wait, no subsequent reads write operation state.
Write wait when AHB_FSM is in AHB, follow-up when being the write operation state, HCLK count down to corresponding the 4th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, and follow-up is the write operation state.
Set up when AHB_FSM is in the AHB write address, follow-up is this clock period of write operation state, and next clock period AHB_FSM enters write data and is ready to state.
Write wait when AHB_FSM is in AHB, follow-up when the read operation state, HCLK count down to corresponding the 4th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, and follow-uply is the read operation state.
Set up when AHB_FSM is in the AHB write address, follow-up is this clock period of read operation state, and next clock period AHB_FSM enters AHB and reads the address loading condition
Write wait when AHB_FSM is in AHB, during no subsequent reads write operation state, HCLK count down to corresponding the 4th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, no subsequent reads write operation state.
Set up when AHB_FSM is in the AHB write address, no follow-up be this clock period of read-write operation state, as if new write operation is arranged, next clock period AHB_FSM enters write data and is ready to state at this moment; If new read operation is arranged, next clock period AHB_FSM enters AHB and reads the address loading condition; If no new read-write operation, next clock period AHB_FSM enters AHB and writes done state.
Write this clock period of done state when AHB_FSM is in AHB, next clock period AHB_FSM entered and write waiting status if new write operation is arranged this moment; If new read operation is arranged, next clock period AHB_FSM enters AHB and reads waiting status; If no new read-write operation, next clock period AHB_FSM enters the ahb bus idle condition.
When AHB_FSM was in AHB and reads waiting status, HCLK count down to corresponding the 4th clock period with current PC LK by the time, and next clock period AHB_FSM enters AHB and reads the address and set up state.
Read this clock period of address loading condition when AHB_FSM is in AHB, next clock period AHB_FSM enters AHB and reads the address and set up state.
Read the address when setting up state when AHB_FSM is in AHB, HCLK count down to corresponding the 4th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB read data and is ready to state.
When AHB_FSM was in the AHB read data and is ready to state, HCLK count down to corresponding the 4th clock period with current PC LK by the time, and next clock period AHB_FSM entered write data and was ready to state if new write operation is arranged this moment; If having new read operation, next clock period AHB_FSM to enter AHB reads the address and sets up state; If no new read-write operation, next clock period AHB_FSM enters the ahb bus idle condition.
In AHB_FSM work, APB_FSM is monitoring the state of AHB_FSM and is doing corresponding action all the time in synchronous operation, and system is transformed on the APB bus from ahb bus the read-write of peripheral hardware, finishes the read and write access to peripheral hardware.
The APB_FSM default setting is an idle condition.When AHB_FSM was in write data and is ready to state, next clock period APB_FSM entered the APB write address and sets up state; When next AHB_FSM is that AHB reads to set up state, next clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next clock period APB_FSM still maintains idle condition.
When APB_FSM was in the APB write address and sets up state, in the current PC LK clock period, write address and write data were sent on the APB bus, and next PCLK clock period APB_FSM enters APB write data enabled state.
When APB_FSM was in APB write data enabled state, at present clock period, address and data still remained unchanged on the APB bus, and the APB enable signal is put height.Meanwhile, when AHB_FSM was in write data and is ready to state, next PCLK clock period APB_FSM entered the APB write address once more and sets up state; When next AHB_FSM is that AHB reads to set up state or AHB reads the address loading condition, next PCLK clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next PCLK clock period APB_FSM enters idle condition.
Read the address when setting up state when APB_FSM is in APB, in the current PC LK clock period, read the address and be sent on the APB bus, next PCLK clock period APB_FSM enters APB read data enabled state.
When APB_FSM was in APB read data enabled state, in the current PC LK clock period, the address still remained unchanged on the APB bus, and the APB enable signal is put height, and the APB Peripheral Interface sends back to data on the APB bus.Meanwhile, when next AHB_FSM is that AHB reads to set up state or AHB reads the address loading condition, next PCLK clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next PCLK clock period APB_FSM enters idle condition.
Bus bridge workflow (N=25) when 3, PCLK is HCLK 5 frequency divisions
At first, it is HCLK 25 frequency divisions that HCLK/PCLK clock frequency ratio testing circuit can detect PCLK, corresponding 25 HCLK of each PCLK clock period.Behind the bus reset, AHB_FSM and APB_FSM are in bus idle state.
When idle condition, when the ahb bus write operation, owing to be 25 frequency divisions, if present clock period is and corresponding the 24th clock period of current PC LK, then next clock period AHB_FSM enters the AHB write data and is ready to state, writes waiting status otherwise AHB_FSM enters AHB; When read operation, if the current HCLK clock period is and corresponding the 24th clock period of current PC LK that next clock period AHB_FSM enters AHB and reads the address and set up state, reads waiting status otherwise AHB_FSM enters AHB.
When AHB_FSM was in AHB and writes waiting status, HCLK count down to corresponding the 24th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write data and is ready to state.
Be ready to this clock period of state when AHB_FSM is in the AHB write data, if subsequent write operation is arranged, next clock period AHB_FSM enters and writes wait, and follow-up is the write operation state; If subsequent read operation is arranged, next clock period AHB_FSM enters and writes wait, and follow-up is the read operation state; If no subsequent reads write operation, next clock period AHB_FSM enters and writes wait, no subsequent reads write operation state.
Write wait when AHB_FSM is in AHB, follow-up when being the write operation state, HCLK count down to corresponding the 24th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, and follow-up is the write operation state.
Set up when AHB_FSM is in the AHB write address, follow-up is this clock period of write operation state, and next clock period AHB_FSM enters write data and is ready to state.
Write wait when AHB_FSM is in AHB, follow-up when the read operation state, HCLK count down to corresponding the 24th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, and follow-uply is the read operation state.
Set up when AHB_FSM is in the AHB write address, follow-up is this clock period of read operation state, and next clock period AHB_FSM enters AHB and reads the address loading condition
Write wait when AHB_FSM is in AHB, during no subsequent reads write operation state, HCLK count down to corresponding the 24th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, no subsequent reads write operation state.
Set up when AHB_FSM is in the AHB write address, no follow-up be this clock period of read-write operation state, as if new write operation is arranged, next clock period AHB_FSM enters write data and is ready to state at this moment; If new read operation is arranged, next clock period AHB_FSM enters AHB and reads the address loading condition; If no new read-write operation, next clock period AHB_FSM enters AHB and writes done state.
Write this clock period of done state when AHB_FSM is in AHB, next clock period AHB_FSM entered and write waiting status if new write operation is arranged this moment; If new read operation is arranged, next clock period AHB_FSM enters AHB and reads waiting status; If no new read-write operation, next clock period AHB_FSM enters the ahb bus idle condition.
When AHB_FSM was in AHB and reads waiting status, HCLK count down to corresponding the 24th clock period with current PC LK by the time, and next clock period AHB_FSM enters AHB and reads the address and set up state.
Read this clock period of address loading condition when AHB_FSM is in AHB, next clock period AHB_FSM enters AHB and reads the address and set up state.
Read the address when setting up state when AHB_FSM is in AHB, HCLK count down to corresponding the 24th clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB read data and is ready to state.
When AHB_FSM was in the AHB read data and is ready to state, HCLK count down to corresponding the 24th clock period with current PC LK by the time, and next clock period AHB_FSM entered write data and was ready to state if new write operation is arranged this moment; If having new read operation, next clock period AHB_FSM to enter AHB reads the address and sets up state; If no new read-write operation, next clock period AHB_FSM enters the ahb bus idle condition.
In AHB_FSM work, APB_FSM is monitoring the state of AHB FSM and is doing corresponding action all the time in synchronous operation, and system is transformed on the APB bus from ahb bus the read-write of peripheral hardware, finishes the read and write access to peripheral hardware.
The APB_FSM default setting is an idle condition.When AHB_FSM was in write data and is ready to state, next clock period APB_FSM entered the APB write address and sets up state; When next AHB_FSM is that AHB reads to set up state, next clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next clock period APB_FSM still maintains idle condition.
When APB_FSM was in the APB write address and sets up state, in the current PC LK clock period, write address and write data were sent on the APB bus, and next PCLK clock period APB_FSM enters APB write data enabled state.
When APB_FSM was in APB write data enabled state, at present clock period, address and data still remained unchanged on the APB bus, and the APB enable signal is put height.Meanwhile, when AHB_FSM was in write data and is ready to state, next PCLK clock period APB_FSM entered the APB write address once more and sets up state; When next AHB_FSM is that AHB reads to set up state or AHB reads the address loading condition, next PCLK clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next PCLK clock period APB_FSM enters idle condition.
Read the address when setting up state when APB_FSM is in APB, in the current PC LK clock period, read the address and be sent on the APB bus, next PCLK clock period APB_FSM enters APB read data enabled state.
When APB_FSM was in APB read data enabled state, in the current PC LK clock period, the address still remained unchanged on the APB bus, and the APB enable signal is put height, and the APB Peripheral Interface sends back to data on the APB bus.Meanwhile, when next AHB_FSM is that AHB reads to set up state or AHB reads the address loading condition, next PCLK clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next PCLK clock period APB_FSM enters idle condition.
Bus bridge workflow (N=63) when 4, PCLK is HCLK 63 frequency divisions
At first, it is HCLK 63 frequency divisions that HCLK/PCLK clock frequency ratio testing circuit can detect PCLK, corresponding 63 HCLK of each PCLK clock period.Behind the bus reset, AHB_FSM and APB_FSM are in bus idle state.
When idle condition, when the ahb bus write operation, owing to be 63 frequency divisions, if present clock period is and corresponding the 62nd clock period of current PC LK, then next clock period AHB_FSM enters the AHB write data and is ready to state, writes waiting status otherwise AHB_FSM enters AHB; When read operation, if the current HCLK clock period is and corresponding the 62nd clock period of current PC LK that next clock period AHB_FSM enters AHB and reads the address and set up state, reads waiting status otherwise AHB_FSM enters AHB.
When AHB_FSM was in AHB and writes waiting status, HCLK count down to corresponding the 62nd clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write data and is ready to state.
Be ready to this clock period of state when AHB_FSM is in the AHB write data, if subsequent write operation is arranged, next clock period AHB_FSM enters and writes wait, and follow-up is the write operation state; If subsequent read operation is arranged, next clock period AHB_FSM enters and writes wait, and follow-up is the read operation state; If no subsequent reads write operation, next clock period AHB_FSM enters and writes wait, no subsequent reads write operation state.
Write wait when AHB_FSM is in AHB, follow-up when being the write operation state, HCLK count down to corresponding the 62nd clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, and follow-up is the write operation state.
Set up when AHB_FSM is in the AHB write address, follow-up is this clock period of write operation state, and next clock period AHB_FSM enters write data and is ready to state.
Write wait when AHB_FSM is in AHB, follow-up when the read operation state, HCLK count down to corresponding the 62nd clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, and follow-uply is the read operation state.
Set up when AHB_FSM is in the AHB write address, follow-up is this clock period of read operation state, and next clock period AHB_FSM enters AHB and reads the address loading condition
Write wait when AHB_FSM is in AHB, during no subsequent reads write operation state, HCLK count down to corresponding the 62nd clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB write address and sets up, no subsequent reads write operation state.
Set up when AHB_FSM is in the AHB write address, no follow-up be this clock period of read-write operation state, as if new write operation is arranged, next clock period AHB_FSM enters write data and is ready to state at this moment; If new read operation is arranged, next clock period AHB_FSM enters AHB and reads the address loading condition; If no new read-write operation, next clock period AHB_FSM enters AHB and writes done state.
Write this clock period of done state when AHB_FSM is in AHB, next clock period AHB_FSM entered and write waiting status if new write operation is arranged this moment; If new read operation is arranged, next clock period AHB_FSM enters AHB and reads waiting status; If no new read-write operation, next clock period AHB_FSM enters the ahb bus idle condition.
When AHB_FSM was in AHB and reads waiting status, HCLK count down to corresponding the 62nd clock period with current PC LK by the time, and next clock period AHB_FSM enters AHB and reads the address and set up state.
Read this clock period of address loading condition when AHB_FSM is in AHB, next clock period AHB_FSM enters AHB and reads the address and set up state.
Read the address when setting up state when AHB_FSM is in AHB, HCLK count down to corresponding the 62nd clock period with current PC LK by the time, and next clock period AHB_FSM enters the AHB read data and is ready to state.
When AHB_FSM was in the AHB read data and is ready to state, HCLK count down to corresponding the 62nd clock period with current PC LK by the time, and next clock period AHB_FSM entered write data and was ready to state if new write operation is arranged this moment; If having new read operation, next clock period AHB_FSM to enter AHB reads the address and sets up state; If no new read-write operation, next clock period AHB_FSM enters the ahb bus idle condition.
In AHB_FSM work, APB_FSM is monitoring the state of AHB_FSM and is doing corresponding action all the time in synchronous operation, and system is transformed on the APB bus from ahb bus the read-write of peripheral hardware, finishes the read and write access to peripheral hardware.
The APB_FSM default setting is an idle condition.When AHB_FSM was in write data and is ready to state, next clock period APB_FSM entered the APB write address and sets up state; When next AHB_FSM is that AHB reads to set up state, next clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next clock period APB_FSM still maintains idle condition.
When APB_FSM was in the APB write address and sets up state, in the current PC LK clock period, write address and write data were sent on the APB bus, and next PCLK clock period APB_FSM enters APB write data enabled state.
When APB_FSM was in APB write data enabled state, at present clock period, address and data still remained unchanged on the APB bus, and the APB enable signal is put height.Meanwhile, when AHB_FSM was in write data and is ready to state, next PCLK clock period APB_FSM entered the APB write address once more and sets up state; When next AHB_FSM is that AHB reads to set up state or AHB reads the address loading condition, next PCLK clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next PCLK clock period APB_FSM enters idle condition.
Read the address when setting up state when APB_FSM is in APB, in the current PC LK clock period, read the address and be sent on the APB bus, next PCLK clock period APB_FSM enters APB read data enabled state.
When APB_FSM was in APB read data enabled state, in the current PC LK clock period, the address still remained unchanged on the APB bus, and the APB enable signal is put height, and the APB Peripheral Interface sends back to data on the APB bus.Meanwhile, when next AHB_FSM is that AHB reads to set up state or AHB reads the address loading condition, next PCLK clock period APB_FSM enters APB and reads to set up state; If do not have read-write operation on the ahb bus, then next PCLK clock period APB_FSM enters idle condition.
By above a plurality of examples as seen, the bridgt circuit of a kind of self-adapting velocity matching bus provided by the invention is by to shaking hands between the automatic detection of PCLK frequency and two finite state machines, realized that ahb bus is to the automatic bridge joint of APB bus with frequently the time.
Claims (6)
1. the bridgt circuit of a self-adapting velocity matching bus is characterized in that this bridgt circuit mainly comprises:
One HCLK/PCLK clock frequency ratio testing circuit, it finishes detection to the frequency ratio between HCLK and the PCLK in per two PCLK clock period; In first clock period, a counter is counted as counting clock with HCLK, and the result of counting deposits in the register with HCLK when first PCLK clock period finishes, and the value of this register is the clock frequency ratio (R between HCLK and the PCLK
HCLK/PCLK);
Second clock period, with PCLK with R
HCLK/PCLKBe latched in another register, as reference value (Ref_R
HCLK/PCLK); When system changes the PCLK frequency, R when first PCLK clock period finishes
HCLK/PCLKCan be updated, like this at second clock period, R
HCLK/PCLKBe not equal to Ref_R
HCLK/PCLK, circuit can produce a reset signal, AHB is resetted to the bridgt circuit of APB, at the 3rd clock period (new R
HCLK/PCLKSense cycle), because Ref_R
HCLK/PCLKBe updated, equal R
HCLK/PCLK, bridgt circuit can begin operate as normal under new PCLK frequency;
According to the clock frequency ratio between detected HCLK and the PCLK, this bus bridge circuit is by an ahb bus transmission control state machine AHB_FSM and an APB bus transfer control state machine APB_FSM, with system to the read-write operation sequential of peripheral hardware from the AHB protocol conversion to the APB agreement; AHB_FSM detects the effectively transmitted signal and the feedback of status that receives from APB_FSM from ahb bus, APB_FSM then is used for receiving the effective read-write control signal from AHB_FSM output, convert effective read-write of following the APB agreement to, thereby finish the conversion of AHB and APB bus protocol peripheral hardware;
And, a peripheral hardware address decoding and data selector channel circuit, it can be deciphered the high address from ahb bus, produces the gating signal of several Peripheral Interfaces; Low order address then converts the address bus of APB bus to, on data path, can data be delivered to different peripheral hardwares and the data that read from different peripheral according to the Peripheral Interface gating signal simultaneously.
2. the bridgt circuit of a kind of self-adapting velocity matching bus according to claim 1, it is characterized in that in the HCLK/PCLK clock frequency ratio testing circuit, in first clock period, 6 binary counters are counted as counting clock with HCLK, the result of counting deposits in the register with HCLK when first PCLK clock period finishes, and the value of this register is the clock frequency ratio (R between HCLK and the PCLK
HCLK/PCLK).
3. the bridgt circuit of a kind of self-adapting velocity matching bus according to claim 2 is characterized in that the HCLK that supports and the scope N of the frequency ratio between the PCLK can be the arbitrary integer between the 1-63.
4. the bridgt circuit of a kind of self-adapting velocity matching bus according to claim 3 is characterized in that the HCLK that supports and the scope N of the frequency ratio between the PCLK can be the arbitrary integer between the 1-63; If need to enlarge PCLK frequency detecting scope, can increase number of counter bits, the maximum PCLK divider ratio of 7 digit counter supports is that the maximum PCLK divider ratio of 127,8 digit counter supports is 255, the rest may be inferred.
5. the bridgt circuit of a kind of self-adapting velocity matching bus according to claim 1, it is characterized in that in peripheral hardware address decoding and the data selector channel circuit, it can be deciphered 4 high addresses from ahb bus, produces the gating signal of 16 Peripheral Interfaces.
6. the bridgt circuit of a kind of self-adapting velocity matching bus according to claim 5, it is characterized in that if needs increase the peripheral hardware number, then need increase the AHB address bus high address number that participates in the peripheral hardware address decoding, 5 can produce 32 peripheral hardware gating signals, 6 can produce 64 peripheral hardware address gating signals, and the like.
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| CNA2006101183293A CN101183347A (en) | 2006-11-14 | 2006-11-14 | Bridge circuit of self-adapting velocity matching bus |
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| CNA2006101183293A CN101183347A (en) | 2006-11-14 | 2006-11-14 | Bridge circuit of self-adapting velocity matching bus |
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| CNA2006101183293A Pending CN101183347A (en) | 2006-11-14 | 2006-11-14 | Bridge circuit of self-adapting velocity matching bus |
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| CN101344875B (en) * | 2008-08-15 | 2011-11-23 | 无锡中星微电子有限公司 | APB bus bridge of on-chip integration system SoC |
| CN101751115B (en) * | 2008-12-22 | 2011-11-23 | 上海海事大学 | Method for solving data transmission matching of DSP and low-speed output device |
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| CN111061663A (en) * | 2019-12-15 | 2020-04-24 | 苏州浪潮智能科技有限公司 | Data transmission method, device and related components |
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