CN101089838A - Method for implementing 12C read-write sequence - Google Patents

Method for implementing 12C read-write sequence Download PDF

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Publication number
CN101089838A
CN101089838A CN 200710128991 CN200710128991A CN101089838A CN 101089838 A CN101089838 A CN 101089838A CN 200710128991 CN200710128991 CN 200710128991 CN 200710128991 A CN200710128991 A CN 200710128991A CN 101089838 A CN101089838 A CN 101089838A
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China
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signal
clock
control register
delay
time
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郑其杉
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ZTE Corp
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ZTE Corp
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Abstract

A method for realizing I2C clock write/read time sequence includes realizing i2C clock signal, start signal, stop signal and response signal by setting data control register, clock control register and time delay then utilizing start signal, stop signal and response signal to finalize write/read operation by master-slave device in communication process.

Description

A kind of method that realizes the I2C read-write sequence
Technical field
The present invention relates to the telecommunications field, relate in particular to a kind of method of the I2C of realization read-write sequence.
Background technology
I2C is a kind of two-wire (SDA (Serial Data-serial data line) and SCL (Serial Clock-serial time clock line)) bus, by these two lines, communication mutually between system's components and parts.I2C comprises a plurality of equipment: master controller (bus master) and utility appliance (bus slave).Usually, master controller can and provide clock signal with the direct communication of utility appliance; Utility appliance can be from master controller that receive data or provide data for master controller.Can only there be a master controller to exist at any time, but can has many utility appliance to exist simultaneously.
At present, Start signal, Stop signal, I2C clock signal, ack signal are all produced by hardware, master-slave equipment is in communication process, and organic Start signal, Stop signal, ack signal are organized together forms an independence, complete time sequential routine.
1, data validity:
Data on the sda line must keep stable in the high level period of clock, the high or low level state of data line only could change when the clock signal of scl line is low level.As shown in Figure 1.
2, initial conditions:
As shown in Figure 2.
3, stop condition:
As shown in Figure 3.
4, the data transmission on the I2C:
Data can only be transmitted on I2C with byte mode, and data transmission unit is a byte.Normally as first, the back after each byte end of transmission (EOT), all can spread out of a response bit (ACK) from the other side immediately following 8 bit data with MSB (the most important position of most significant bit-) in transmission.Fig. 4 has listed the sequential of data transmission.
When the I2C master controller is sent out an order to utility appliance, software need be done following settings: utility appliance address (Slave Address), operational attribute be set be read or write, command word (CommandCode), data (Data), the unlatching (start) with control register enables position 1 then.If all parameters are all correct, finish the transmission of data when write operation, perhaps the reception of data is finished in read operation, and master controller will produce a SMI# signal or produce and interrupt.
I2C supports 7 kinds of command formats: Quick Command, send byte, receive byte, write byte, read byte, the read/write of the invocation of procedure and data block.Bottom has listed wherein the most frequently used several command formats (these orders all need to carry out a series of communication between the master/slave I2C equipment, and organic START, STOP, ack signal are organized together forms an independence, complete time sequential routine in the communication process):
1, read a byte from current location:
I2C memory device inside has an address pointer counter to be used to write down the pointer of current access location, and after the read/write operation of I2C memory device, this pointer will move and preserve automatically each time.Receive byte and just can realize obtaining simply the data that current pointer indication address bit is deposited.This operates in SDA (Serial Data-serial data) and goes up data stream as shown in Figure 5.
2, write a byte to current location:
Write a byte and to read a byte agreement very similar, unique difference is exactly the direction of transfer of data, and the data of reading a byte are to pass to master controller from utility appliance; And the data of writing a byte are to pass to utility appliance from master controller.This operates in SDA and goes up data stream and just change " 0 " into the 7th of first byte of Fig. 5.
3, write a byte (Byte)/word (Word) to the assigned address of storer:
The address that this command format requirement at first transmits a utility appliance, and command word last the position indicate it is a write operation, the response of wait utility appliance, the value of that byte that transmits the data address that length is a byte (Word Address) then and will write, the back sends a STOP command word again.This operates in SDA and goes up data stream as shown in Figure 6.The operation that writes a word is for writing the byte operation, and the operation before the STOP all is the same, just transmits the another one byte again, receive ACK after, send STOP again.Manipulation of data stream as shown in Figure 7.
4, read a byte (Byte)/word (Word) from the assigned address of storer:
Read operation and write operation are not quite alike, read an assigned address, must tell the address that storer will read earlier, and then carry out read operation, send the STOP signal again after receiving byte.If want to read from assigned address the data of a word (WORD), the operation before the STOP is all constant, just after receiving first byte, do not send STOP, read a byte again, receive ACK after, just send the STOP signal, detailed manipulation of data stream as shown in Figure 8.
Aforesaid operations all realizes by the visit of hardware realization to the I2C slave unit, following equipment must being arranged: I2C master controller and I2C slave unit by hardware.Thereby cause big, the poor stability of hardware design difficulty.
Summary of the invention
The technical problem underlying that the present invention solves provided a kind of method of the I2C of realization read-write sequence, solved the problem of hardware design complexity, poor stability.
In order to address the above problem, the present invention proposes a kind of method of the I2C of realization read-write sequence, combination by signal, finish read-write operation, principal feature is, I2C clock signal, Start signal are that start signal, Stop signal are stop signal, to send or obtain ack signal be that response signal is to realize by being provided with of Data Control register, clock-control register and time delays; And master-slave equipment utilizes Start signal, Stop signal, ack signal to finish read-write operation in communication process.
Further, method characteristics provided by the invention are that the I2C clock signal realizes by following steps:
Step 1, clock-control register puts 1, thus related circuit output high level;
Step 2, time-delay n ms;
Step 3, clock-control register is clear 0, thus the related circuit output low level;
Step 4 behind the time-delay nms, is carried out step 1 again, so circulation, thus realized producing the purpose of I2C clock signal with software.
Further, method characteristics provided by the invention are that the Start signal is realized by following steps:
Step 1 puts 1 to the Data Control register, exports high level on the data line;
Step 2, time-delay n/2ms;
Step 3, clock-control register puts 1, thus related circuit output high level;
Step 4, time-delay n/2ms;
Step 5, the Data Control register is clear 0, output low level on the data line;
Step 6, time-delay n/2ms;
Step 7, clock-control register is clear 0, thus the related circuit output low level;
Step 8, time-delay n/2ms, thus detect data line once variation from high to low when utilizing software to realize clock for high level.
Further, method characteristics provided by the invention are that the Stop signal is realized by following steps:
Step 1, the Data Control register is clear 0, output low level on the data line;
Step 2, clock-control register is clear 0, the related circuit output low level;
Step 3, time-delay n/2ms;
Step 4, clock-control register puts 1, related circuit output high level;
Step 5, time-delay n/2ms;
Step 6, the Data Control register puts 1, exports high level on the data line;
Step 7, time-delay n/2ms, thus detect data line once variation from low to high when having realized clock for high level.
Further, method characteristics provided by the invention are, obtain ack signal and realize by following steps:
Step 1, the Data Control register puts 1, exports high level on the data line;
Step 2, time-delay 1ms;
Step 3, clock-control register puts 1, related circuit output high level;
Step 4, time-delay 1ms;
Step 5, the read data control register;
Step 6, whether the lowest order of judgment data control register is 1, if, execution in step seven, otherwise, execution in step four;
Step 7, clock-control register is clear 0, thereby has realized ack signal that the I2C main equipment receives at data line when being high, and slave unit output is still for high.
Further, method characteristics provided by the invention are, send ack signal and realize by following steps:
Step 1, the Data Control register is clear 0, output low level on the data line;
Step 2, time-delay n/2ms;
Step 3, clock-control register puts 1, related circuit output high level;
Step 4, time-delay n/2ms;
Step 5, clock-control register is clear 0, thereby has realized that data line produces the high clock signal of half clock period when low.
Further, said method also has following characteristics, and master-slave equipment utilizes Start signal, Stop signal, ack signal to finish read-write operation in communication process, carries out write operation and realizes by following steps:
Step 1 sends the Start signal;
Step 2 sends a specific control word 0x86;
Step 3 is waited for the slave unit response signal;
Step 4 sends address offset;
Step 5 is waited for the slave unit response signal;
Step 6, the value that transmission will write;
Step 7 is waited for the slave unit response signal;
Step 8 sends the Stop signal, thereby has realized writing a byte to assigned address.
Further, said method also has following characteristics, and master-slave equipment utilizes Start signal, Stop signal, ack signal to finish read-write operation in communication process, carries out read operation and realizes by following steps:
Step 1 sends the Start signal;
Step 2 sends a specific control word 0x86;
Step 3 is waited for the slave unit response signal;
Step 4 sends address offset;
Step 5 is waited for the slave unit response signal;
Step 6 sends the Start signal;
Step 7 sends a specific control word 0x87;
Step 8 is waited for the slave unit response signal;
Step 9 reads the value that I2C passes back;
Step 10 sends the Stop signal, thereby has realized reading a byte from assigned address.
Adopt the method for the invention can simplify the complexity of hardware design, strengthen module portability, increased the dirigibility of system design, shortened the cycle of product development, greatly reduce the product bug that causes owing to hardware reason, finally improved the qualification rate and the serviceable life of product.
Description of drawings
Fig. 1 is the significance bit transmission time sequence figure of I2C bus;
Fig. 2 is the sequential chart of the Start signal of I2C;
Fig. 3 is the sequential chart of the Stop signal of I2C;
Fig. 4 is I2C byte transformat figure;
Fig. 5 is a data flow diagram of reading a byte manipulation from current location;
Fig. 6 is the I2C controller is write a data flow diagram from a byte manipulation to the address of appointment;
Fig. 7 is the I2C controller is write a data flow diagram from a data block operations to the address of appointment;
Fig. 8 is the I2C controller reads a byte manipulation from assigned address a data flow diagram;
Fig. 9 is a software clocking process flow diagram;
Figure 10 is that software produces the Start signal flow graph;
Figure 11 is that software produces the Stop signal flow graph;
Figure 12 is that software obtains the ack signal process flow diagram;
Figure 13 is that software realizes sending the ack signal process flow diagram;
Figure 14 writes a byte processing flow chart to assigned address;
Figure 15 reads a byte processing flow chart from assigned address.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in detail.
The present invention needs hardware that two controllable digital signals are provided, and this two signal links to each other with SCL with the SDA of I2C device respectively.Software writes 1 in control register, related circuit output high level; Software writes 0 in control register, the related circuit output low level.
The present invention realizes the following basic function of I2C:
(1) software produces the I2C clock;
(2) software is realized the START signal;
(3) software is realized the STOP signal;
(4) software realizes obtaining ack signal;
(5) software realizes sending ack signal;
(6) write a byte to assigned address
(7) read a byte from assigned address.
Describe in detail below.
(1) software produces the I2C clock:
The clock of I2C as shown in Figure 1, though there is not synchronous requirement, but have certain restricting relation between clock and the data, data must keep stable in the high level period of clock, and the high or low level state of data line only could change when clock signal is low level.Its treatment scheme as shown in Figure 9.In Fig. 9, the step of execution is as follows: step 1, and clock-control register puts 1, thus related circuit output high level; Step 2, time-delay nms; Step 3, clock-control register is clear 0, thus the related circuit output low level, step 4 behind the time-delay nms, is carried out step 1 again, so circulation, thus realized producing the purpose of I2C clock signal with software.
(2) software is realized the method for START signal:
The START signal is characterized in detecting data line once variation from high to low during for high level at clock as shown in Figure 2.Its treatment scheme as shown in figure 10.In Figure 10, the step of execution is as follows: step 1, the Data Control register is put 1, and export high level on the data line; Step 2, time-delay n/2ms; Step 3, clock-control register puts 1, thus related circuit output high level; Step 4, time-delay n/2ms; Step 5, the Data Control register is clear 0, output low level on the data line; Step 6, time-delay n/2ms; Step 7, clock-control register is clear 0, thus the related circuit output low level; Step 8, time-delay n/2ms, thus detect data line once variation from high to low when utilizing software to realize clock for high level.
(3) software is realized the method for STOP:
STOP as shown in Figure 3, the characteristics of this signal are to detect data line once variation from low to high during for high level at clock.Its treatment scheme is carried out following steps as shown in figure 11: step 1, and the Data Control register is clear 0, output low level on the data line; Step 2, clock-control register is clear 0, the related circuit output low level; Step 3, time-delay n/2ms; Step 4, clock-control register puts 1, related circuit output high level; Step 5, time-delay n/2ms; Step 6, the Data Control register puts 1, exports high level on the data line; Step 7, time-delay n/2ms, thus detect data line once variation from low to high when having realized clock for high level.
(4) software realizes obtaining the method for ack signal:
The ack signal characteristics that the I2C main equipment receives are at data line when being high, and slave unit output is still for high.Its treatment scheme as shown in figure 12, the step of execution is as follows: step 1, the Data Control register puts 1, exports high level on the data line; Step 2, time-delay 1ms; Step 3, clock-control register puts 1, related circuit output high level; Step 4, time-delay 1ms; Step 5, the read data control register; Step 6, whether the lowest order of judgment data control register is 1, if, execution in step seven, otherwise, execution in step four; Step 7, clock-control register is clear 0, thereby has realized ack signal that the I2C main equipment receives at data line when being high, and slave unit output is still for high.
(5) software realizes sending the method for ack signal:
The ack signal characteristics that the I2C main equipment sends are to produce the high clock signal of half clock period when low at data line.Its treatment scheme as shown in figure 13, the step of execution is as follows: step 1, the Data Control register is clear 0, output low level on the data line; Step 2, time-delay n/2ms; Step 3, clock-control register puts 1, related circuit output high level; Step 4, time-delay n/2ms; Step 5, clock-control register is clear 0, thereby has realized that data line produces the high clock signal of half clock period when low.
(6) write a byte to assigned address:
Writing of each byte all needs to carry out a series of communication between the master/slave I2C equipment, organic time sequential routine that START, STOP, ack signal are organized together independence of formation, finish in the communication process.Complete sequential as shown in Figure 6.The function that write operation of software realization can call the front to be provided can realize writing to assigned address the operation of a particular data, and its treatment scheme may further comprise the steps as shown in figure 14: step 1 sends the Start signal; Step 2 sends a specific control word 0x86; Step 3 is waited for the slave unit response signal; Step 4 sends address offset; Step 5 is waited for the slave unit response signal; Step 6, the value that transmission will write; Step 7 is waited for the slave unit response signal; Step 8 sends the Stop signal, thereby has realized writing a byte to assigned address.
(7) read a byte from assigned address:
Reading of each byte also all needs to carry out a series of communication between the master/slave I2C equipment, organically START, STOP, ack signal organized together the time sequential routine that forms an independence, finishes in the communication process.Complete sequential as shown in Figure 8.The function that the front is called in read operation meeting of software realization to be provided can realize reading from assigned address the operation of a byte, and its treatment scheme comprises the steps: step 1 as shown in figure 15, sends the Start signal; Step 2 sends a specific control word 0x86; Step 3 is waited for the slave unit response signal; Step 4 sends address offset; Step 5 is waited for the slave unit response signal; Step 6 sends the Start signal; Step 7 sends a specific control word 0x87; Step 8 is waited for the slave unit response signal; Step 9 reads the value that I2C passes back; Step 10 sends the Stop signal, thereby has realized reading a byte from assigned address.

Claims (8)

1, a kind of method that realizes the I2C read-write sequence, combination by signal, finish read-write operation, it is characterized in that, I2C clock signal, Start signal are that start signal, Stop signal are stop signal, to send or obtain ack signal be that response signal is to realize by being provided with of Data Control register, clock-control register and time delays, and master-slave equipment utilizes Start signal, Stop signal, ack signal to finish read-write operation in communication process.
2, method according to claim 1 is characterized in that, the I2C clock signal realizes by following steps:
Step 1, clock-control register puts 1, thus related circuit output high level;
Step 2, time-delay n ms;
Step 3, clock-control register is clear 0, thus the related circuit output low level;
Step 4 behind the time-delay n ms, is carried out step 1 again, so circulation, thus realized producing the purpose of I2C clock signal with software.
3, method according to claim 1 is characterized in that, the Start signal is realized by following steps:
Step 1 puts 1 to the Data Control register, exports high level on the data line;
Step 2, time-delay n/2ms;
Step 3, clock-control register puts 1, thus related circuit output high level;
Step 4, time-delay n/2ms;
Step 5, the Data Control register is clear 0, output low level on the data line;
Step 6, time-delay n/2ms;
Step 7, clock-control register is clear 0, thus the related circuit output low level;
Step 8, time-delay n/2ms, thus detect data line once variation from high to low when utilizing software to realize clock for high level.
4, method according to claim 1 is characterized in that, the Stop signal is realized by following steps:
Step 1, the Data Control register is clear 0, output low level on the data line;
Step 2, clock-control register is clear 0, the related circuit output low level;
Step 3, time-delay n/2ms;
Step 4, clock-control register puts 1, related circuit output high level;
Step 5, time-delay n/2ms;
Step 6, the Data Control register puts 1, exports high level on the data line;
Step 7, time-delay n/2ms, thus detect data line once variation from low to high when having realized clock for high level.
5, method according to claim 1 is characterized in that, obtains ack signal and realizes by following steps:
Step 1, the Data Control register puts 1, exports high level on the data line;
Step 2, time-delay 1ms;
Step 3, clock-control register puts 1, related circuit output high level;
Step 4, time-delay 1ms;
Step 5, the read data control register;
Step 6, whether the lowest order of judgment data control register is 1, if, execution in step seven, otherwise, execution in step four;
Step 7, clock-control register is clear 0, thereby has realized ack signal that the I2C main equipment receives at data line when being high, and slave unit output is still for high.
6, method according to claim 1 is characterized in that, sends ack signal and realizes by following steps:
Step 1, the Data Control register is clear 0, output low level on the data line;
Step 2, time-delay n/2ms;
Step 3, clock-control register puts 1, related circuit output high level;
Step 4, time-delay n/2ms;
Step 5, clock-control register is clear 0, thereby has realized that data line produces the high clock signal of half clock period when low.
7, method according to claim 1 is characterized in that, master-slave equipment utilizes Start signal, Stop signal, ack signal to finish read-write operation in communication process, carries out write operation and realizes by following steps:
Step 1 sends the Start signal;
Step 2 sends a specific control word 0x86;
Step 3 is waited for the slave unit response signal;
Step 4 sends address offset;
Step 5 is waited for the slave unit response signal;
Step 6, the value that transmission will write;
Step 7 is waited for the slave unit response signal;
Step 8 sends the Stop signal, thereby has realized writing a byte to assigned address.
8, method according to claim 1 is characterized in that, master-slave equipment utilizes Start signal, Stop signal, ack signal to finish read-write operation in communication process, carries out read operation and realizes by following steps:
Step 1 sends the Start signal;
Step 2 sends a specific control word 0x86;
Step 3 is waited for the slave unit response signal;
Step 4 sends address offset;
Step 5 is waited for the slave unit response signal;
Step 6 sends the Start signal;
Step 7 sends a specific control word 0x87;
Step 8 is waited for the slave unit response signal;
Step 9 reads the value that I2C passes back;
Step 10 sends the Stop signal, thereby has realized reading a byte from assigned address.
CN 200710128991 2007-07-28 2007-07-28 Method for implementing 12C read-write sequence Pending CN101089838A (en)

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Application Number Priority Date Filing Date Title
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102567270A (en) * 2011-12-05 2012-07-11 深圳市金凯博自动化测试有限公司 USB (universal serial bus)-to-I2C (inter-integrated circuit) adapter
CN101645057B (en) * 2008-08-06 2012-07-18 中兴通讯股份有限公司 Method and device for preventing CPU local bus from suspension
CN102622325A (en) * 2011-12-23 2012-08-01 苏州华芯微电子股份有限公司 I2C (inter-integrated circuit) bus starting and stopping circuit structure
CN104125047A (en) * 2013-04-24 2014-10-29 精工爱普生株式会社 Communication circuit, physical quantity measurement device, electronic apparatus, and communication method
CN106126362A (en) * 2016-06-17 2016-11-16 青岛海信宽带多媒体技术有限公司 A kind of optical module I2C bus unrest sequential diagnosis method and device
CN109857688A (en) * 2019-01-21 2019-06-07 飞依诺科技(苏州)有限公司 The data transmission method and system of I2C bus interface applied to Medical Devices
CN110362524A (en) * 2018-04-11 2019-10-22 杭州海康威视数字技术股份有限公司 Timing signal generating method, device, logic card and storage medium

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645057B (en) * 2008-08-06 2012-07-18 中兴通讯股份有限公司 Method and device for preventing CPU local bus from suspension
CN102567270A (en) * 2011-12-05 2012-07-11 深圳市金凯博自动化测试有限公司 USB (universal serial bus)-to-I2C (inter-integrated circuit) adapter
CN102622325A (en) * 2011-12-23 2012-08-01 苏州华芯微电子股份有限公司 I2C (inter-integrated circuit) bus starting and stopping circuit structure
CN102622325B (en) * 2011-12-23 2014-12-24 苏州华芯微电子股份有限公司 I2C (inter-integrated circuit) bus starting and stopping circuit structure
CN104125047A (en) * 2013-04-24 2014-10-29 精工爱普生株式会社 Communication circuit, physical quantity measurement device, electronic apparatus, and communication method
CN104125047B (en) * 2013-04-24 2019-05-03 精工爱普生株式会社 Telecommunication circuit, physical amount measuring device, electronic equipment, communication means
CN106126362A (en) * 2016-06-17 2016-11-16 青岛海信宽带多媒体技术有限公司 A kind of optical module I2C bus unrest sequential diagnosis method and device
CN106126362B (en) * 2016-06-17 2019-01-04 青岛海信宽带多媒体技术有限公司 A kind of optical module I2C bus unrest sequential diagnosis method and device
CN110362524A (en) * 2018-04-11 2019-10-22 杭州海康威视数字技术股份有限公司 Timing signal generating method, device, logic card and storage medium
CN110362524B (en) * 2018-04-11 2021-04-09 杭州海康威视数字技术股份有限公司 Time sequence signal generation method and device, logic circuit board and storage medium
CN109857688A (en) * 2019-01-21 2019-06-07 飞依诺科技(苏州)有限公司 The data transmission method and system of I2C bus interface applied to Medical Devices

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