KR100622943B1 - Controller for automatically controlling timing specification and the timing specification controlling method thereof - Google Patents

Abstract

A controller capable of automatically controlling timing specifications and a method of controlling timing specifications thereof are disclosed. This controller is based on a counter that counts the main clock according to the set value, which is the number of main clocks to be included in one cycle, and a finite state machine (FSM) that generates a control signal when the counter counts half of the set value. And a data generator for generating data on the basis of the generated control signal. This not only reduces the burden on the central processing unit by the controller using the minimum software controllable registers, but also secures a margin at the setting time and holding time by accurate timing control, thereby stabilizing communication.

Timing specifications, setup time, hold time

Description

Controller for automatically controlling timing specification and the timing specification controlling method

1 is a timing diagram according to a communication protocol of a general I2C bus,

2 is a block diagram of an electronic device including an I 2 C bus controller according to an embodiment of the present invention;

3 is a timing diagram of an I2C bus controller according to an embodiment of the present invention; and

4 is a flowchart provided to explain a timing specification control method of an I2C bus controller according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: main processor 200: I2C bus controller

210: period selection register 220: edge selection register

230: Counter 240: FSM

250: synchronization clock generation unit 260: data generation unit

270 control unit 300 SCL

350: SDA 400: Slave Device

The present invention relates to a controller and a method of controlling a timing specification thereof, and more particularly, to a controller capable of automatically adjusting timing specifications of slave devices performing data communication according to a synchronous clock and a method of controlling the timing specification thereof. will be.

In general, in most systems, the controller has slave devices for system control, and the controller and slave devices communicate with the synchronous clock provided by the controller. An alternative example of communicating on a synchronous clock is I2C.

I2C is a two-wire, bi-directional serial bus that provides a communication link between integrated circuits, also called Inter-IC. Specifically, I2C is a serial bus protocol capable of communicating with a plurality of slave devices, and can control a plurality of slave devices using only a power line and two lines SCL and SDA. The SCL (Serial Clock Line) is a line for clock transmission, and the SDA (Serial DAta line) is a line for transmitting data serially. Data is transmitted and received on the data line by one bit according to the clock. Therefore, it is important to control the timing specifications between the clock and the data for stable communication with the slave device.

 1 illustrates a timing diagram according to a communication protocol of a general I2C bus.

Referring to FIG. 1, the state of SDA is changed only when SCL is low. Therefore, the data is valid only in a section where SCL is high. In order to satisfy the timing specification of the I2C protocol, t _{HD: STA} , which is a start time, t _{HD: DAT} , which is a data retention time, t _{SU; STA} , a time when the start condition is set, t _{SU; DAT} , a data setting time, etc. Control of the same timing parameters is required.

However, the conventional timing spec control method uses a method of providing a dedicated controller or controlling in software to control the timing spec.

The method of controlling timing specifications using a dedicated controller required a software controllable register as many as timing parameters to control timing parameters in order to implement accurate protocols and timing specifications.

In addition, the method of controlling the timing specifications in software is controlled through the IO port of the central processing unit, and implemented as a method of functionalizing the control method of a predetermined time interval through the central processing unit in software.

Thus, a dedicated controller is not only complicated by a large number of registers in the design, but also an increase in software management. In addition, the software control method through the IO port increases the burden on the central processing unit, and since accurate timing control is impossible, a loss of timing may occur, which may cause data corruption.

Accordingly, an object of the present invention is to design a dedicated controller for avoiding a software control method that burdens the central processing unit, but a controller capable of automatically controlling timing specifications without separate software control for each parameter. To provide a timing specification control method.

A controller according to the present invention for achieving the above object is a counter for counting the main clock according to a set value which is the number of main clocks to be included in one period, FSM for generating a control signal when the counter counts half of the set value (Finite State Machine), a synchronization clock generation unit for generating a synchronization clock according to the valid data determination edge based on the generated control signal, and a data generation unit for generating data based on the generated control signal.

The apparatus may further include a period selection register in which the set value is stored, and an edge selection register in which the valid data determination edge is stored.

The sync clock generator generates the sync clock until the control signal generation point when the valid data determination edge is a rising edge, and generates the sync clock after the control signal generation time when the valid data determination edge is a falling edge. It is desirable to.

On the other hand, the timing specification control method of the controller of the present invention, the step of counting the main clock according to the set value which is the number of the main clock to be included in one period, generating a control signal when counting half of the set value, the generation Generating a synchronous clock according to the valid data determination edge based on the generated control signal, and generating data based on the generated control signal.

The generating of the synchronization clock may include generating the synchronization clock until the control signal generation time when the valid data determination edge is a rising edge, and generating the synchronization clock after the control signal generation time when the valid data determination edge is a falling edge. It is desirable to generate a clock.

Hereinafter, with reference to the drawings will be described in detail the present invention.

2 is a block diagram of an electronic device including an I 2 C bus controller according to an embodiment of the present invention.

The electronic device includes a main processor 100, an I2C bus controller 200, an SCL 300, an SDA 350, and a slave device 400. The main processor 100 uses the I2C bus controller 200. It communicates with the slave device 400 through a serial control line (SCL) 300 and a serial data line (SDA) 350.

The I2C bus controller 200 automatically communicates with the slave device 400 with the synchronization clock and data, and uses only the minimum software controllable registers to communicate based on the synchronization clock. An example of a controller that controls the.

Referring to FIG. 2, the I2C bus controller 200 includes a period select register 210, an edge select register 220, a counter 230, an FSM 240, a synchronous clock generator 250, and a data generator ( 260, and a controller 270.

The main processor 100 generates a main clock pulse.

The period selection register 210 stores a setting value for one period of the main clock pulse. The set value represents the number of main clock pulses to be included in one period.

The edge selection register 220 stores an edge of a synchronous clock (hereinafter referred to as 'valid data determination edge') for setting a time point for determining valid data.

The counter 230 counts the main clock pulses by the set value stored in the period selection register 210.

The finite state machine (FSM) 240 generates a control signal that is a reference signal when the counter 230 counts a half cycle, that is, a half value of the set value. The control signal is a signal that is a reference for generation of a synchronous clock and data change.

The sync clock generator 250 generates a sync clock based on the control signal generated by the FSM 240 and applies the sync clock to the SCL 300. Specifically, if the rising edge is stored as the valid data determination edge in the edge selection register 220, the synchronization clock generation unit 250 ends the generation of the synchronization clock at the end of generation of the control signal. On the other hand, if the falling edge is stored as the valid data determination edge in the edge selection register 220, the synchronization clock generator 250 generates a synchronization clock at the end of generation of the control signal.

The data generator 260 generates the data to change at the time when the control signal is generated and applies the data to the SDA 350.

Accordingly, when the rising edge is stored as the valid data determination edge in the edge selection register 220, the data generator 260 changes the data at a time corresponding to the falling edge of the synchronous clock. do. On the other hand, if the falling edge is stored as the valid data determination edge in the edge selection register 220, the data generator 260 changes the data at the time corresponding to the rising edge of the synchronization clock.

The controller 270 is responsible for the function control of the I2C bus controller 200 and the interface with the main processor 100. The control unit 270 sets a predetermined set value and valid data determination edge.

The slave device 400 operates on the basis of the synchronous clock applied through the SCL 300 and determines valid data among data applied through the SDA 350 according to the valid data determination edge set by the controller 270. . When the rising edge of the synchronous clock is set to the valid data determination edge, the slave device 400 determines the data corresponding to the rising edge of the synchronous clock as a valid value. When the falling edge of the synchronous clock is set to the valid data determination edge, the slave device 400 determines the data corresponding to the falling edge of the synchronous clock as a valid value.

3 is a timing diagram of an I2C bus controller according to an embodiment of the present invention.

As shown in Fig. 3, a timing diagram when the valid data determination edge is the rising edge of the synchronous clock and the data corresponding to the rising edge of the synchronous clock are valid data, and a change in data occurs on the falling edge of the synchronous clock. Indicates.

(a) The main clock is a signal generated by the main processor 100.

(b) Counter_A is a signal output by counting the main clock by the counter 230 by the set value. At this time, for example, the set value is 20. The counter 230 counts (a) the main clock by 20 from 0 to 19 and outputs (b) Counter_A.

(c) Control_A is a signal generated by the FSM 240. The FSM 240 generates the reference signal (c) Control_A at the moment when the counter 230 counts half of the set value, that is, 10 from 0 to 9.

(d) The synchronous clock is a signal generated by the synchronous clock generator 250. The sync clock generator 250 outputs the sync clock (d) until (c) the end of Control_A, that is, while the counter 230 counts the half value 10 of the set value.

(e) The data is a signal generated by the data generator 260. The data generator 260 changes (e) the data at the time corresponding to the falling edge of the (d) synchronous clock based on (c) Control_A.

Similarly, if the data corresponding to the falling edge of the synchronous clock is valid data and a change in data occurs on the rising edge of the synchronous clock, if the set value is 20, (a) main clock and (b) Counter_A shown in FIG. Same as (c) Control_A, (e) data. Only the synchronous clock is generated from the end of (c) Control_A based on (c) Control_A. That is, in FIG. 3, (d) the synchronous clock is shifted by 10 to the right.

As a result, timing specifications are automatically controlled to ensure a margin for the setup time and a margin for the retention time while satisfying the setup time specification and the hold time specification.

4 is a flowchart provided to explain a timing specification control method of an I2C bus controller according to an embodiment of the present invention.

Referring to FIG. 4, the controller 270 sets a set value and valid data determination edge (S400). The control unit 270 stores the set value in the period selection register 210 and the valid data determination edge in the edge selection register 220.

The counter 230 counts the main clock generated by the main processor 100 according to the set value (S410).

The FSM 240 determines whether the value counted by the counter 230 is half of the set value (S420).

If it is determined that the counted value is half of the set value, the FSM 240 generates a control signal (S430).

The sync clock generator 250 generates a sync clock according to the valid data determination edge based on the generated control signal, and the data generator 260 generates data based on the generated control signal (S440).

As described above, according to the present invention, the burden on the central processing unit is reduced by the controller using only the minimum software controllable registers. In addition, accurate timing control ensures a margin at the set time and the hold time, thereby stabilizing communication.

In addition, while the above has been shown and described with respect to preferred embodiments of the present invention, the present invention is not limited to the specific embodiments described above, the technology to which the invention belongs without departing from the spirit of the invention claimed in the claims Various modifications can be made by those skilled in the art, and these modifications should not be understood from the technical idea or the prospect of the present invention.

Claims (5)

A counter for counting the main clock according to a set value, the number of main clocks to be included in one period; A finite state machine (FSM) which generates a control signal when the counter counts half of the set value; A synchronization clock generation unit configured to generate a synchronization clock according to a valid data determination edge based on the generated control signal; And And a data generator configured to generate data based on the generated control signal. The method of claim 1, A period selection register for storing the set value; And And an edge selection register at which the valid data determination edge is stored. The method of claim 1, The synchronous clock generation unit, If the valid data determination edge is a rising edge, the synchronous clock is generated until the control signal generation point; And if the valid data determination edge is a falling edge, generating the synchronous clock after the control signal generation point. Counting the main clock according to a set value which is a number of main clocks to be included in one period; Generating a control signal when counting half of the set value; Generating a synchronous clock according to a valid data determination edge based on the generated control signal; And And generating data on the basis of the generated control signal. The method of claim 4, wherein Generating the synchronous clock, If the valid data determination edge is a rising edge, the synchronous clock is generated until the control signal generation point; And generating the synchronous clock after the control signal generation time point when the valid data determination edge is a falling edge.

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