CN116893987B - Hardware acceleration method, hardware accelerator and hardware acceleration system - Google Patents
Hardware acceleration method, hardware accelerator and hardware acceleration system Download PDFInfo
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Abstract
The invention provides a hardware acceleration method, a hardware accelerator and a hardware acceleration system. Comprising the following steps: sequentially reading descriptors from an input FIFO, and resolving the first address and the length of a source data packet and the first address of a destination data packet from the descriptors; reading the source data packet from the memory according to the head address and the length of the source data packet; performing decoding processing or encoding processing on the source data packet according to a preset rule to obtain a target data packet; writing the destination data packet into the memory according to the first address of the destination data packet; updating the descriptor, and writing the updated descriptor into the output FIFO. The invention can reduce the interaction between software and hardware, reduce the requirement on memory resources and improve the system performance.
Description
Technical Field
The present invention relates to the field of network communications technologies, and in particular, to a hardware acceleration method, a hardware accelerator, and a hardware acceleration system.
Background
The operation of consuming CPU resources by complex comparison is handed to hardware processing, but because of the variety of certain network data types, software assistance is still required after part of hardware processing is performed, or hardware processing is still required after software processing, so that the back-and-forth interaction of software and hardware can reduce the overall performance of the system. How to avoid frequent interaction of software and hardware is one of the keys to improve system performance.
In the current interaction mode of software and hardware, a management mechanism of TX_FIFO and RX_FIFO is generally adopted, that is, two FIFO needs to be applied at a receiving end and a transmitting end, so that data transmission and memory recovery are facilitated. This is less friendly for some embedded platforms where memory resources are intense.
Disclosure of Invention
In view of this, the present invention provides a hardware acceleration method, a hardware accelerator, and a hardware acceleration system, which can reduce the interaction between software and hardware, reduce the requirement for memory resources, and improve the system performance.
In a first aspect, the present invention provides a hardware acceleration method, including:
sequentially reading descriptors from an input FIFO, the descriptors including the following description fields: a description field of a head address of a storage space of the memory, a description field of a head address offset of a source data packet, a description field of a length of the source data packet, a description field of a head address offset of a destination data packet, and a description field of a length of the destination data packet;
analyzing the first address and length of the source data packet and the first address of the destination data packet from the descriptor;
reading a source data packet from a memory according to the head address and the length of the source data packet;
performing decoding processing or encoding processing on the source data packet according to a preset rule to obtain a target data packet;
writing the destination data packet into a memory according to the first address of the destination data packet;
updating the descriptor, comprising: updating a description field of the length of the destination data packet according to the actual length of the destination data packet;
and writing the updated descriptors into an output FIFO so that the processor reads the updated descriptors from the output FIFO in batches and reads the destination data packets from the memory according to the updated descriptors.
Optionally, the descriptor further includes the following description fields: description field of discrete frame characteristics of the destination data packet, description field of data errors and description field of CRC check result;
the updating the descriptor further comprises: and updating the description field of the discrete frame characteristics of the destination data packet, the description field of the data errors and the description field of the CRC check result according to the actual condition of data processing.
Optionally, the description field of the discrete frame characteristic of the destination data packet includes a plurality of bits, wherein the 1bit of the highest bit is an end-of-frame identification bit, and the remaining plurality of bits are discrete frame sequence number indication bits.
Optionally, the description field of the data error includes a plurality of bits, where 1bit is used to indicate that the source packet is not a protocol packet, and 1bit is used to indicate that the source packet length exceeds a protocol specification.
Optionally, the method further comprises:
inquiring the state of the output FIFO, and triggering an interrupt when any interrupt triggering condition is met so that a processor can timely read updated descriptors from the output FIFO in batches, and reading a target data packet from a memory according to the updated descriptors;
the interrupt trigger conditions include:
the output FIFO is full;
the output FIFO changing from empty to non-empty and filling to a certain amount;
the output FIFO changes from empty to non-empty and the configured latency has arrived.
In a second aspect, the present invention provides a hardware accelerator comprising:
a data reading module for sequentially reading descriptors from an input FIFO, the descriptors comprising the following description fields: a description field of a head address of a storage space of a memory, a description field of a head address offset of a source data packet, a description field of a length of the source data packet, a description field of a head address offset of a destination data packet and a description field of a length of the destination data packet, and resolving the head address and the length of the source data packet and the head address of the destination data packet from the descriptors;
the descriptor analyzing module is used for analyzing the first address and the length of the source data packet and the first address of the destination data packet from the descriptor;
the data reading module is further used for reading the source data packet from the memory according to the first address and the length of the source data packet;
the data processing module is used for carrying out decoding processing or encoding processing on the source data packet according to a preset rule to obtain a target data packet;
the data write-back module is used for writing the destination data packet into the memory according to the first address of the destination data packet;
a descriptor updating module, configured to update the descriptor, including: updating a description field of the length of the destination data packet according to the actual length of the destination data packet;
the data write-back module is further configured to write the updated descriptor into the output FIFO, so that the processor reads the updated descriptor from the output FIFO in batch, and reads the destination data packet from the memory according to the updated descriptor.
Optionally, the descriptor further includes the following description fields: description field of discrete frame characteristics of the destination data packet, description field of data errors and description field of CRC check result;
the descriptor updating module is further configured to: and updating the description field of the discrete frame characteristics of the destination data packet, the description field of the data errors and the description field of the CRC check result according to the actual condition of data processing.
In a third aspect, the present invention provides a hardware acceleration system, including the above hardware accelerator, further including: a memory storage device and a processor,
the memory is used for storing a source data packet and a destination data packet;
and a portion of the memory space of the memory storage is configured as an input FIFO and an output FIFO;
the input FIFO is used for storing descriptors;
the output FIFO is used for storing the updated descriptors;
the processor is configured to write a source data packet to the memory storage, and determine the following description fields in the descriptor: a description field of a head address of a storage space of a memory storage, a description field of a head address offset of a source data packet, a description field of a length of the source data packet, and a description field of a head address offset of a destination data packet, and writing the descriptors into the input FIFO in batches;
and the device is also used for reading the updated descriptors from the output FIFO in batches and reading the target data packet from the memory according to the updated descriptors.
In a fourth aspect, the present invention provides a chip, including the hardware acceleration system described above.
In a fifth aspect, the present invention provides an electronic device, including the above chip.
The invention provides a hardware acceleration method, a hardware accelerator and a hardware acceleration system, which define flexible and simplified descriptors during the interaction of software and hardware, the hardware accelerator acquires a source data packet through the descriptors and informs a CPU of the information of a destination data packet in the form of the descriptors, so that the interaction between the software and the hardware is reduced, and the performance advantage of the hardware accelerator is fully exerted. And the interaction of software and hardware only needs one input FIFO and one output FIFO, and the purpose of the interaction of the software and the hardware is realized under the condition of occupying less memory.
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FIG. 1 is a flow chart of a hardware acceleration method according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a hardware accelerator according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating a hardware acceleration system according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Furthermore, the terms "mounted," "configured," "provided," "connected," "coupled," and "sleeved" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
One embodiment of the present invention provides a hardware acceleration method, as shown in fig. 1, which includes steps S101 to S107.
Step S101, sequentially reading descriptors from the input FIFO, the descriptors including the following description fields: the description field of the head address of the storage space of the memory, the description field of the head address offset of the source data packet, the description field of the length of the source data packet, the description field of the head address offset of the destination data packet and the description field of the length of the destination data packet.
Step S102, the first address and length of the source data packet and the first address of the destination data packet are resolved from the descriptor.
For descriptors stored in the input FIFO, several fields are of practical significance, namely a description field of the memory space head address of the memory store, a description field of the head address offset of the source packet, a description field of the length of the source packet, a description field of the head address offset of the destination packet. According to the fields, the head address and length of the source data packet and the head address of the destination data packet can be resolved.
The description field of the length of the destination packet is updated according to the actual length of the destination packet, so that there is no practical meaning here.
The description fields in the descriptor are determined by the CPU and are batch written to the input FIFO by the CPU.
Step S103, reading the source data packet from the memory according to the head address and the length of the source data packet.
In this application, a data packet to be processed by the hardware accelerator is referred to as a source data packet. When the hardware accelerator is used for decoding, the source packet may be a PPP data frame received from the external interface. When the hardware accelerator is used for encoding, the source packet may be an IP packet generated by an upper layer application.
The source packets are also written by the CPU into memory storage.
And step S104, carrying out decoding processing or encoding processing on the source data packet according to a preset rule to obtain a target data packet.
In this application, a packet generated after the decoding or encoding process by the hardware accelerator is referred to as a destination packet.
The hardware accelerator decodes the source data packet, including: analyzing the received PPP data frame to obtain an original message; performing CRC (cyclic redundancy check) to verify the accuracy of the data; the frame header, address information, control information, CRC value, and frame trailer are removed.
The hardware accelerator encodes the source data packet, including: calculating CRC values of an original message, a control field and an address field; escape and add frame header (0 x 7E), address field (0 xFF) and control field (0 x 03); escaping and adding original message data; escaping and adding the CRC value calculated before; the end of frame (0 x 7E) is added.
Step S105, the destination data packet is written into the memory according to the first address of the destination data packet.
For a system with a tight memory storage (DDR), a destination address (address of a destination packet) and a source address (address of a source packet) can be designated as the same storage space, and an original address operation is implemented by using a time difference of internal cache processing of a hardware accelerator.
Step S106, updating the descriptor, including: and updating the description field of the length of the destination data packet according to the actual length of the destination data packet.
In step S107, the updated descriptors are written into the output FIFO, so that the processor reads the updated descriptors from the output FIFO in batch, and reads the destination packet from the memory according to the updated descriptors.
IN this embodiment, the input FIFO (may be denoted as in_fifo) and the output FIFO (may be denoted as out_fifo) are formed IN a partial space configuration occupying the memory (DDR). The storage space is distinguished from the source and destination packets by addresses. Because only one input FIFO and one output FIFO are needed for the interaction of the software and the hardware, the purpose of the interaction of the software and the hardware is realized under the condition of occupying less memory.
In this embodiment, when a single data packet is specifically processed by the hardware accelerator, the hardware accelerator first parses a descriptor corresponding to the single data packet, then retrieves a certain amount of source data from a source address specified by the descriptor according to the depth of the internal buffer memory to perform hardware processing, then writes out a destination data packet according to a destination address specified by the descriptor, dynamically updates the descriptor according to the data processing situation in real time, and writes out the updated descriptor. The whole process can be described simply as: fetch descriptor- > fetch source packet- > packet handling- > write destination packet- > write descriptor. Then according to the performance requirement, the 5 steps can realize full-flow operation or partial flow, so that the performance is improved.
Regarding the depth of the internal cache, there is the following relationship: the larger the system delay, the deeper the internal cache depth; the higher the processing performance, the deeper the internal cache depth.
For example: assuming that the performance requires half byte per cycle, then the system average latency is around 60 cycles, then the cache depth 16 is sufficient (width 32) to meet the ping-pong usage requirement of one burst 8. As 8 x 32/4=64 >60.
For the source data packet and the destination data packet, the descriptors and the data packets are in one-to-one correspondence, so that diversified data access requirements are conveniently met. Corresponding to complex situations such as discrete frames in an actual scene, the corresponding relation between a source data packet and a destination data packet is relatively complex, and various complex arrangement and combination situations such as one-to-many and many-to-one exist. Therefore, the hardware accelerator not only needs to correctly complete the most basic encoding and decoding operation, but also needs to record the relation between the source data packet and the destination data packet and some abnormal conditions, process various conditions such as merging and splitting of the source data packet, discarding and the like in time, dynamically update the descriptor according to the data processing conditions and write out the updated descriptor. The CPU can comprehensively understand the situation of the destination data packet only by taking the descriptor in the OUT_FIFO, and frequent interaction of software and hardware is avoided.
Further, to meet the above-mentioned complications, in one embodiment, the descriptor further includes the following description fields: description field of discrete frame characteristics of the destination data packet, description field of data errors and description field of CRC check result;
updating the descriptor, further comprising: and updating the description field of the discrete frame characteristics of the destination data packet, the description field of the data error and the description field of the CRC check result according to the actual condition of data processing.
The main fields of the descriptors of the hardware and software interactions and their meanings are given in table 1.
TABLE 1
The description field of the discrete frame characteristic of the destination data packet includes a plurality of bits, taking 8 bits as an example, and may be represented as Seq [7:0], where the 1bit of the highest bit is an end-of-frame identification bit, and the remaining 7 bits are discrete frame number indication bits.
The description field of the data error may be denoted as Errcode, and includes a plurality of bits, where 1bit is used to indicate that the source packet is not a protocol packet, and 1bit is used to indicate that the source packet length exceeds the protocol specification, but is not limited to these error types.
The processing of the source packet and how to update the description field Seq 7:0 of the discrete frame characteristics of the destination packet will be described in a specific example.
There are 3 source packets to be decoded, 1000byte,1000 byte,500 byte each, denoted a/B/C (this process does not take into account special cases such as very long errors).
The a packet 1000 bytes are broken into 200, 500, 300 bytes, but not ending with 7e last;
b packets 1000 bytes are split into 300, 400, 300 bytes, ending with 7 e;
the C packet 500 bytes is split into 50, 450 bytes, ending with 7 e.
Then there are:
1-200, 201-700 are all output as independent frames, with seq=0;
701-1000 as a first frame output of one discrete frame, whose seq [7:0] =0000_0001;
1001-1300 is output as the last frame of a discrete frame, whose seq [7:0] =1000_0010;
1301-1700, 1701-2000 are all output as independent frames, with seq=0;
2001-2050, 2051-2500 are all output as independent frames, with seq=0.
There are 1-to-many cases in all of the 3 source packets, but the first 2 packets of a, the last 2 packets of B and the C packets are output seq=0, called independent frames, the 3 rd packet of a and the 1 st packet of B, and seq is not 0, which is called discrete frames, which are composed of a plurality of data segments with discontinuous addresses, the discrete frames correspond to a plurality of source packets, and the software can conveniently recognize that the relationship between the batches of data is convenient.
When the hardware accelerator is used as a decoder, the description field of discrete frame characteristics of a destination data packet, the description field of data errors and the description field of CRC check results need to be updated; as the description field of the length of the destination packet in the descriptor needs to be updated at the time of the encoder, the description field of the data error (for example, the output exceeds the specified length) and the description field of the CRC check result need to be updated.
Further described, the present application adopts the FIFO structure to reduce the interaction between software and hardware, the CPU can detect the running condition of the hardware accelerator at any time by actively querying the point of the FIFO to facilitate the subsequent operation, but the interrupt mechanism is also an indispensable mechanism, and at present, the following interrupts (each interrupt has a corresponding mask bit to mask the report) are defined in the hardware accelerator:
1. the fault interruption can be generated under the abnormal conditions such as the error of the crc or the length exceeding, and the like, and the information can be brought into a specific descriptor for writing;
2. the OUT_FIFO is full, the hardware accelerator stops working, at the moment, the CPU needs to timely process the data packet with the encoded and decoded data packet, and the OUT_FIFO space is released so that the accelerator can continue to operate;
3. the out_fifo is changed from empty to non-empty and filled to a certain amount (the software can configure the threshold) to trigger the interrupt, so that the CPU can batch data packets and reduce the interrupt as much as possible;
4. when the OUT_FIFO is changed from empty to non-empty and the configured waiting time is up, the interrupt is triggered, so that the CPU can read the data in time and reduce the interrupt as far as possible.
With the interrupt mechanism, once the situation occurs in the encoding and decoding process, the interrupt mechanism can be fed back to the CPU in time, and the CPU can decide whether to intervene immediately through configuration according to the current scene requirement.
Thus, in one embodiment, the hardware acceleration method further comprises:
inquiring the state of the output FIFO, and triggering an interrupt when any interrupt triggering condition is met so that a processor can timely read updated descriptors from the output FIFO in batches, and reading a target data packet from a memory according to the updated descriptors;
the interrupt trigger conditions include:
the output FIFO is full;
the output FIFO changes from empty to non-empty and fills to a certain amount;
the output FIFO changes from empty to non-empty and the configured latency has arrived.
According to the hardware acceleration method provided by the embodiment of the invention, flexible and simplified descriptors are defined during the interaction of software and hardware, the hardware accelerator acquires the source data packet through the descriptors and informs the CPU of the information of the destination data packet in the form of the descriptors, so that the interaction between the software and the hardware is reduced, and the performance advantage of the hardware accelerator is fully exerted. And the interaction of software and hardware only needs one input FIFO and one output FIFO, and the purpose of the interaction of the software and the hardware is realized under the condition of occupying less memory.
In another aspect, one embodiment of the present invention provides a hardware accelerator, as shown in fig. 2, comprising: a data reading module 201, a descriptor parsing module 202, a data processing module 203, a data write-back module 204 and a descriptor updating module 205,
a data reading module 201, configured to sequentially read descriptors from the input FIFO, where the descriptors include the following description fields: a description field of a head address of a storage space of a memory, a description field of a head address offset of a source data packet, a description field of a length of the source data packet, a description field of a head address offset of a destination data packet and a description field of a length of the destination data packet, and resolving the head address and the length of the source data packet and the head address of the destination data packet from the descriptors;
the descriptor parsing module 202 is configured to parse the first address and length of the source data packet and the first address of the destination data packet from the descriptor;
the data reading module 201 is further configured to read the source data packet from the memory according to the first address and the length of the source data packet;
the data processing module 203 is configured to perform decoding processing or encoding processing on the source data packet according to a preset rule to obtain a destination data packet;
the data write-back module 204 is configured to write the destination data packet into the memory according to the first address of the destination data packet;
a descriptor updating module 205, configured to update a descriptor, including: updating a description field of the length of the destination data packet according to the actual length of the destination data packet;
the data write-back module 204 is further configured to write the updated descriptor into the output FIFO, so that the processor reads the updated descriptor from the output FIFO in batch, and reads the destination packet from the memory according to the updated descriptor.
Further, in one embodiment, the descriptor further includes the following description fields: description field of discrete frame characteristics of the destination data packet, description field of data errors and description field of CRC check result;
the descriptor updating module 205 is further configured to: and updating the description field of the discrete frame characteristics of the destination data packet, the description field of the data error and the description field of the CRC check result according to the actual condition of data processing.
The hardware accelerator provided in the embodiment of the present invention is used for executing the above method embodiment, and the specific flow and details thereof refer to the above embodiment, and are not repeated herein.
On the other hand, an embodiment of the present invention further provides a hardware acceleration system, and fig. 3 is a schematic structural diagram of the hardware acceleration system, as shown in fig. 3, where the hardware acceleration system includes the hardware accelerator 301 of the foregoing embodiment, and further includes: memory storage 302 and communication bus 303, hardware accelerator 301 and memory storage 302 communicate with each other via communication bus 303. The memory storage 302 is configured to store source packets and destination packets, the source packets and destination packets occupy a majority of the memory space of the memory storage, and a portion of the memory space of the memory storage 302 is configured as an input FIFO for storing descriptors and an output FIFO for storing updated descriptors. The memory space of the input FIFO, output FIFO, source packet and destination packet is distinguished by address. In addition, the input FIFO and output FIFO sizes may be determined based on the actual system content space, with higher performance being achievable with larger FIFOs generally open.
With further reference to FIG. 3, the hardware acceleration system further includes:
a processor 304, configured to write the source data packet into the memory storage, and determine the following description fields in the descriptor: a description field of a first address of a storage space of the memory, a description field of a first address offset of a source data packet, a description field of a length of the source data packet, and a description field of a first address offset of a destination data packet, and writing descriptors into the input FIFO in batches;
and the device is also used for reading updated descriptors from the output FIFO in batches and reading the destination data packet from the memory according to the updated descriptors.
When the hardware acceleration system works, the CPU firstly writes the prepared descriptors into the IN_FIFO IN batches, updates the write pointer corresponding to the IN_FIFO, reads the source data packet from the source address appointed by the descriptor after the hardware accelerator reads the descriptors from the IN_FIFO, updates the read pointer corresponding to the IN_FIFO, sequentially carries OUT hardware decoding or encoding on each source data packet, writes the destination data packet to the destination address appointed by the descriptor, updates the descriptors, writes the updated descriptors into the OUT_FIFO so that the CPU reads the destination data packet, and updates the write pointer of the OUT_FIFO. After the CPU reads the descriptor from the OUT_FIFO, the read pointer of the OUT_FIFO is updated, and then the destination data packet is read from the destination address designated by the descriptor, so that the whole data processing flow is completed.
In another aspect, an embodiment of the present invention provides a chip that includes the hardware acceleration system of the above embodiment.
In another aspect, an embodiment of the present invention provides an electronic device, including the above chip.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or the like.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. A method of hardware acceleration, the method comprising:
sequentially reading descriptors from an input FIFO, the descriptors being batch written to the input FIFO by a processor, the descriptors comprising the following description fields: a description field of a head address of a storage space of the memory, a description field of a head address offset of a source data packet, a description field of a length of the source data packet, a description field of a head address offset of a destination data packet, and a description field of a length of the destination data packet;
analyzing the first address and length of the source data packet and the first address of the destination data packet from the descriptor;
reading a source data packet from a memory according to the head address and the length of the source data packet;
performing decoding processing or encoding processing on the source data packet according to a preset rule to obtain a target data packet;
writing the destination data packet into a memory according to the first address of the destination data packet;
updating the description field of the descriptor, comprising: updating a description field of the length of the destination data packet according to the actual length of the destination data packet;
and writing the updated descriptors into an output FIFO so that the processor reads the updated descriptors from the output FIFO in batches and reads the destination data packets from the memory according to the updated descriptors.
2. The method of claim 1, wherein the descriptor further comprises the following description fields: description field of discrete frame characteristics of the destination data packet, description field of data errors and description field of CRC check result;
the updating the description field of the descriptor further comprises: and updating the description field of the discrete frame characteristics of the destination data packet, the description field of the data errors and the description field of the CRC check result according to the actual condition of data processing.
3. The method of claim 2, wherein the description field of the discrete frame characteristics of the destination data packet includes a plurality of bits, wherein the most significant 1bit is an end of frame identification bit and the remaining plurality of bits are discrete frame number indication bits.
4. The method of claim 2, wherein the description field of the data error comprises a plurality of bits, wherein 1bit is used to indicate that the source packet is not a protocol packet and 1bit is used to indicate that the source packet length is outside of protocol specifications.
5. The method according to claim 1, wherein the method further comprises:
inquiring the state of the output FIFO, and triggering an interrupt when any interrupt triggering condition is met so that a processor can timely read updated descriptors from the output FIFO in batches, and reading a target data packet from a memory according to the updated descriptors;
the interrupt trigger conditions include:
the output FIFO is full;
the output FIFO changing from empty to non-empty and filling to a certain amount;
the output FIFO changes from empty to non-empty and the configured latency has arrived.
6. A hardware accelerator, comprising:
a data reading module for sequentially reading descriptors from an input FIFO, the descriptors being batch written to the input FIFO by a processor, the descriptors comprising the following description fields: a description field of a head address of a storage space of a memory, a description field of a head address offset of a source data packet, a description field of a length of the source data packet, a description field of a head address offset of a destination data packet and a description field of a length of the destination data packet, and resolving the head address and the length of the source data packet and the head address of the destination data packet from the descriptors;
the descriptor analyzing module is used for analyzing the first address and the length of the source data packet and the first address of the destination data packet from the descriptor;
the data reading module is further used for reading the source data packet from the memory according to the first address and the length of the source data packet;
the data processing module is used for carrying out decoding processing or encoding processing on the source data packet according to a preset rule to obtain a target data packet;
the data write-back module is used for writing the destination data packet into the memory according to the first address of the destination data packet;
a descriptor updating module, configured to update a description field of the descriptor, including: updating a description field of the length of the destination data packet according to the actual length of the destination data packet;
the data write-back module is further configured to write the updated descriptor into the output FIFO, so that the processor reads the updated descriptor from the output FIFO in batch, and reads the destination data packet from the memory according to the updated descriptor.
7. The hardware accelerator of claim 6, wherein the descriptor further comprises the following description fields: description field of discrete frame characteristics of the destination data packet, description field of data errors and description field of CRC check result;
the descriptor updating module is further configured to: and updating the description field of the discrete frame characteristics of the destination data packet, the description field of the data errors and the description field of the CRC check result according to the actual condition of data processing.
8. A hardware acceleration system comprising the hardware accelerator of claim 6 or 7, further comprising: a memory storage device and a processor,
the memory is used for storing a source data packet and a destination data packet;
and a portion of the memory space of the memory storage is configured as an input FIFO and an output FIFO;
the input FIFO is used for storing descriptors;
the output FIFO is used for storing the updated descriptors;
the processor is configured to write a source data packet to the memory storage, and determine the following description fields in the descriptor: a description field of a head address of a storage space of a memory storage, a description field of a head address offset of a source data packet, a description field of a length of the source data packet, and a description field of a head address offset of a destination data packet, and writing the descriptors into the input FIFO in batches;
and the device is also used for reading the updated descriptors from the output FIFO in batches and reading the target data packet from the memory according to the updated descriptors.
9. A chip comprising the hardware acceleration system of claim 8.
10. An electronic device comprising the chip of claim 9.
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