CN109446130A - A kind of acquisition methods and system of I/O device status information - Google Patents
A kind of acquisition methods and system of I/O device status information Download PDFInfo
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- CN109446130A CN109446130A CN201811268334.1A CN201811268334A CN109446130A CN 109446130 A CN109446130 A CN 109446130A CN 201811268334 A CN201811268334 A CN 201811268334A CN 109446130 A CN109446130 A CN 109446130A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The application provides the acquisition methods and system of a kind of I/O device status information, which comprises the status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, to obtain the status information of I/O equipment；The status information of acquired I/O equipment is stored to status information memory space corresponding with I/O equipment；CPU is according to the status information memory space in default rule access on-site programmable gate array FPGA, to obtain the status information of the I/O equipment stored in status information memory space.
Description
Technical field
This application involves field of communication technology more particularly to a kind of acquisition methods and system of I/O device status information.
Background technique
In order to realize that different specific functions, the CPU such as display, communication and data acquisition usually require to connect multiple I/O
(Input/Output) equipment.In system work process, CPU needs to obtain the status information of I/O equipment.Generally I/O is set
Standby internal with status register, when changing I/O equipment working state, I/O equipment will modify corresponding state deposit
The status information stored in device.
The mode that CPU generallys use poll at present obtains the status information of I/O equipment, i.e. CPU at regular intervals, is accessed
Status register inside I/O equipment obtains the status information of I/O equipment.
Since CPU usually connects multiple I/O equipment, CPU needs successively to obtain each I/O by way of poll and sets
Standby status information, the status information for obtaining these I/O equipment need to occupy a large amount of cpu resource, increase cpu load.
Summary of the invention
In view of this, the application provides the acquisition methods and system of a kind of I/O device status information.
Specifically, the application is achieved by the following technical solution:
A kind of acquisition methods of I/O device status information, which is characterized in that the acquisition applied to I/O device status information
System, the system comprises CPU, on-site programmable gate array FPGA and at least one I/O equipment, the CPU and scene can
Programming gate array FPGA is attached by PCIe bus, and the on-site programmable gate array FPGA is attached with I/O equipment,
It is at the scene that each I/O equipment allocates independent status information memory space, the method in advance in programmable gate array FPGA
Include:
The status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, to obtain
The status information of I/O equipment；
The status information of acquired I/O equipment is stored to status information memory space corresponding with I/O equipment；
CPU is according to the status information memory space in default rule access on-site programmable gate array FPGA, to obtain
The status information of the I/O equipment stored in status information memory space.
A kind of acquisition system of I/O device status information, which is characterized in that the system comprises: CPU, field-programmable
Gate array FPGA and at least one I/O equipment, the CPU are connected with on-site programmable gate array FPGA by PCIe bus
It connects, the on-site programmable gate array FPGA is attached with I/O equipment, is at the scene each I/ in programmable gate array FPGA
O device allocates independent status information memory space in advance；
The status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, to obtain
The status information of I/O equipment；
The status information of acquired I/O equipment is stored to status information memory space corresponding with I/O equipment；
CPU is according to the status information memory space in default rule access on-site programmable gate array FPGA, to obtain
The status information of the I/O equipment stored in status information memory space.
The application accesses the Status register in the I/O equipment being attached with itself by on-site programmable gate array FPGA
Device is stored the status information of acquired I/O equipment to shape corresponding with I/O equipment with obtaining the status information of I/O equipment
State information storage space, the status information that CPU can be accessed in on-site programmable gate array FPGA according to default rule store
Space, to obtain the status information of the I/O equipment stored in status information memory space, in this way, CPU and field-programmable
Gate array FPGA is attached by PCIe bus, passes through the state of on-site programmable gate array FPGA indirect gain I/O equipment
Information, the status information for obtaining I/O equipment do not need to occupy a large amount of cpu resource, can effectively reduce cpu load.
Detailed description of the invention
Fig. 1 is a kind of application scenarios schematic diagram shown in one exemplary embodiment of the application；
Fig. 2 is a kind of interactive stream of the acquisition methods of I/O device status information shown in one exemplary embodiment of the application
Cheng Tu；
Fig. 3 is a kind of hardware knot of the acquisition system of I/O device status information shown in one exemplary embodiment of the application
Structure schematic diagram.
Specific embodiment
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they be only with it is such as appended
The example of the consistent device and method of some aspects be described in detail in claims, the application.
It is only to be not intended to be limiting the application merely for for the purpose of describing particular embodiments in term used in this application.
It is also intended in the application and the "an" of singular used in the attached claims, " described " and "the" including majority
Form, unless the context clearly indicates other meaning.It is also understood that term "and/or" used herein refers to and wraps
It may be combined containing one or more associated any or all of project listed.
It will be appreciated that though various information, but this may be described using term first, second, third, etc. in the application
A little information should not necessarily be limited by these terms.These terms are only used to for same type of information being distinguished from each other out.For example, not departing from
In the case where the application range, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as
One information.Depending on context, word as used in this " if " can be construed to " ... when " or " when ...
When " or " in response to determination ".
A kind of acquisition methods of I/O device status information provided by the embodiments of the present application are illustrated first, this method
It may comprise steps of:
The status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, to obtain
The status information of I/O equipment；
The status information of acquired I/O equipment is stored to status information memory space corresponding with I/O equipment；
CPU is according to the status information memory space in default rule access on-site programmable gate array FPGA, to obtain
The status information of the I/O equipment stored in status information memory space.
A kind of application scenario diagram as shown in Figure 1, CPU are connected with on-site programmable gate array FPGA by PCIe bus
It connects, on-site programmable gate array FPGA is attached with multiple I/O equipment, is in advance at the scene every in programmable gate array FPGA
A I/O equipment distributes independent status information memory space, and wherein status information memory space is field programmable gate array
The corresponding memory space of FPGA base address register, the space abbreviation BAR (Base Address Registers), each state letter
The capacity of breath memory space can be determined according to actual needs.CPU is total by PCIe with on-site programmable gate array FPGA
Line is attached, and by the status information of on-site programmable gate array FPGA indirect gain I/O equipment, obtains the shape of I/O equipment
State information does not need to occupy a large amount of cpu resource, can effectively reduce cpu load.
As shown in Fig. 2, being a kind of interaction flow of the acquisition methods of I/O device status information provided by the embodiments of the present application
Figure, this method can specifically include following steps:
S201, the status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, with
Obtain the status information of I/O equipment；
It is a kind of acquisition system of I/O device status information shown in one exemplary embodiment of the application referring to shown in Fig. 3
Hardware structural diagram according to the priority of each I/O equipment, corresponding access modules are realized by programming in this application,
Such as priority, low I/O equipment, is accessed using polling mode, I/O equipment higher for priority, using interrupt or in
The disconnected mode cooperated with poll accesses, and realizes command process module by programming, and the information for handling CPU reads instruction and visits
It asks the interrupt signal of module, and is responsible for the status information of the I/O equipment stored in reading state memory space.
It should be noted that between access modules and I/O equipment, can be it is one-to-one access, i.e., each access mould
Block correspond to an I/O equipment, be also possible to it is one-to-many access, i.e., each access modules correspond at least one I/O equipment.
The status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, to obtain
The status information of I/O equipment, specific implementation may is that in on-site programmable gate array FPGA preconfigured access modules according to
The status register in I/O equipment that preset access rule access is attached with itself, to obtain the state letter of I/O equipment
Breath.Such as the corresponding I/O equipment 1 of access modules 1, the corresponding I/O equipment 2 of access modules 2, the corresponding I/O equipment 3 of access modules 3, scene
Status register in programmable gate array FPGA in preconfigured each accessible corresponding I/O equipment of access modules
Device, to obtain the status information of each I/O equipment, in another example access modules 1 correspond to I/O equipment 1, I/O equipment 2, I/O equipment 3,
State in on-site programmable gate array FPGA in itself accessible corresponding I/O equipment of preconfigured access modules 1 is posted
Storage, to obtain the status information of each I/O equipment.
In addition, the access of preconfigured access modules each of is attached with itself in on-site programmable gate array FPGA
Status register in I/O equipment can be matched with obtaining the status information of I/O equipment by poll, interruption, interruption and poll
The mode of conjunction is realized.
1) access modules access the Status register in each I/O equipment being attached with itself by way of poll
Device, the status information to obtain I/O equipment: access modules by task poll or time poll in a manner of access and itself into
Status register in the I/O equipment of row connection, to obtain the status information of I/O equipment, by the state of acquired I/O equipment
Status information memory space corresponding with I/O equipment is arrived in information, storage.
2) access modules access the Status register in each I/O equipment being attached with itself by way of interruption
Device, to obtain the status information of I/O equipment: I/O equipment sends interrupt signal to access modules, and the format of interrupt signal needs to join
The communication protocol between on-site programmable gate array FPGA and I/O equipment is examined, access modules are visited after receiving interrupt signal
It asks the status register of corresponding I/O equipment, to obtain the status information of I/O equipment, the state of acquired I/O equipment is believed
Status information memory space corresponding with I/O equipment is arrived in breath, storage.
3) access modules are accessed in each I/O equipment being attached with itself interrupting with by way of poll cooperation
Status register, to obtain the status information of I/O equipment: I/O equipment sends interrupt signal to access modules, due to I/O equipment
, there is the problems such as I/O equipment persistently sends interrupt signal in the reasons such as abnormal state or improper use, and access modules are learning interruption
After signal sends exception, it is switched to polling mode, access modules are accessed and oneself by way of task poll or time poll
The status register in I/O equipment that body is attached, to obtain the status information of I/O equipment, by acquired I/O equipment
Status information memory space corresponding with I/O equipment is arrived in status information, storage, after learning that interrupt signal is sent normally, switching
Return interrupt mode.
The status information of acquired I/O equipment is stored to status information corresponding with I/O equipment and stores sky by S202
Between；
All there is corresponding status information memory space in programmable gate array FPGA at the scene in each I/O equipment,
Such as I/O equipment 1, I/O equipment 2, I/O equipment 3, all there is corresponding state letter in programmable gate array FPGA at the scene
Cease memory space 1, status information memory space 2, status information memory space 3.
The status information of acquired I/O equipment is stored to status information memory space corresponding with I/O equipment, such as
The acquired corresponding status information of I/O equipment 1 is stored to the corresponding status information memory space 1 of I/O equipment 1.
S203, CPU access the status information memory space in on-site programmable gate array FPGA according to default rule, with
Obtain the status information of the I/O equipment stored in status information memory space.
CPU is according to the status information memory space in default rule access on-site programmable gate array FPGA, to obtain
The status information of the I/O equipment stored in status information memory space specifically by poll or can interrupt two ways realization:
1) CPU obtains the status information of the I/O equipment stored in status information memory space: CPU by way of poll
Information is sent to on-site programmable gate array FPGA by PCIe bus according to the preset period and reads instruction；Field programmable gate
After array FPGA receives the information reading instruction, instruction is read to the information and is parsed to obtain the information and read
The state memory space address carried in instruction fetch, wherein state memory space address can be some corresponding shape of I/O equipment
The address of state memory space is also possible to the address of the corresponding state memory space of certain several I/O equipment, is also possible to whole I/
The address of the corresponding state memory space of O device；It is read from the corresponding state memory space of the state memory space address
The status information of the I/O equipment of reading is packaged and returns to CPU by the status information of I/O equipment；CPU receives scene can
The status information for the I/O equipment that gate array FPGA returns is programmed, to obtain the I/O equipment stored in status information memory space
Status information.
2) CPU obtains the status information of the I/O equipment stored in status information memory space by way of interruption: scene
PCIe interrupt signal is sent to CPU by programmable gate array FPGA, and the mark of I/O equipment is carried in the PCIe interrupt signal；
CPU receives the PCIe interrupt signal, extracts the mark of the I/O equipment carried in the PCIe interrupt signal；According to described
The mark of I/O equipment sends information to on-site programmable gate array FPGA and reads instruction；On-site programmable gate array FPGA receives
After reading instruction to the information, instruction is read to the information and is parsed to obtain in the information reading instruction and carry
State memory space address, the state memory space address is for the I/O equipment pre-assigned status information storage
State memory space address corresponding to space；I/ is read from the corresponding state memory space of the state memory space address
The status information of the I/O equipment of reading is packaged and returns to CPU by the status information of O device；CPU receives scene and can compile
The status information for the I/O equipment that journey gate array FPGA returns, to obtain the shape of the I/O equipment stored in status information memory space
State information.
Wherein, access modules send interrupt signal to command process module, and the interrupt signal is in I/O equipment to access modules
The mark of I/O equipment is added on the interrupt signal basis of transmission, usually the number of I/O equipment, command process module should
Interrupt signal is converted to PCIe interrupt signal, is interrupted by MSI (Message Signal Interrupt, message signal interrupt)
Etc. modes be sent to CPU.Furthermore it if command process module receives multiple interrupt signals of access modules transmission, needs pair
These interrupt signals are arbitrated, and the interrupt signal is then converted to PCIe interrupt signal, pass through MSI (Message
Signal Interrupt, message signal interrupt) interrupt etc. modes be sent to CPU.
The application is set by above step by the I/O that on-site programmable gate array FPGA access is attached with itself
Status register in standby, to obtain the status information of I/O equipment, by the status information of acquired I/O equipment store to
The corresponding status information memory space of I/O equipment, CPU can be accessed in on-site programmable gate array FPGA according to default rule
Status information memory space, to obtain the status information of the I/O equipment stored in status information memory space, in this way,
CPU is attached with on-site programmable gate array FPGA by PCIe bus, by obtaining between on-site programmable gate array FPGA
The status information of I/O equipment is taken, the status information for obtaining I/O equipment does not need to occupy a large amount of cpu resource, can effectively reduce
Cpu load.
Corresponding with above method embodiment, present invention also provides a kind of acquisition system of I/O device status information, institutes
The system of stating includes: CPU, on-site programmable gate array FPGA and at least one I/O equipment, the CPU and field programmable gate
Array FPGA is attached by PCIe bus, and the on-site programmable gate array FPGA is attached with I/O equipment, at the scene
It is that each I/O equipment allocates independent status information memory space in advance in programmable gate array FPGA；
The status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, to obtain
The status information of I/O equipment；
The status information of acquired I/O equipment is stored to status information memory space corresponding with I/O equipment；
CPU is according to the status information memory space in default rule access on-site programmable gate array FPGA, to obtain
The status information of the I/O equipment stored in status information memory space.
Above system realizes that process is specifically detailed in the realization process that step is corresponded in the above method, and details are not described herein.
For system embodiments, since it corresponds essentially to embodiment of the method, so related place is referring to method reality
Apply the part explanation of example.System embodiment described above is only schematical, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to actual
The purpose for needing to select some or all of the modules therein to realize application scheme.Those of ordinary skill in the art are not paying
Out in the case where creative work, it can understand and implement.
The present invention can be in the general described in the text, such as program up and down of calculated value executable instruction performed by computer
Module.Generally, program module includes routines performing specific tasks or implementing specific abstract data types, programs, objects, group
Part, data structure etc..The present invention can also be practiced in a distributed computing environment, in these distributed computing environments, by
Task is executed by the connected remote processing devices of communication network.In a distributed computing environment, program module can be with
In the local and remote computer storage media including storage equipment.
The above is only a specific embodiment of the invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of acquisition methods of I/O device status information, which is characterized in that the acquisition system applied to I/O device status information
System, the system comprises CPU, on-site programmable gate array FPGA and at least one I/O equipment, the CPU can compile with scene
Journey gate array FPGA is attached by PCIe bus, and the on-site programmable gate array FPGA is attached with I/O equipment,
It is that each I/O equipment allocates independent status information memory space, the method packet in advance in on-site programmable gate array FPGA
It includes:
The status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, is set with obtaining I/O
Standby status information；
The status information of acquired I/O equipment is stored to status information memory space corresponding with I/O equipment；
CPU is according to the status information memory space in default rule access on-site programmable gate array FPGA, to obtain state
The status information of the I/O equipment stored in information storage space.
2. the method according to claim 1, wherein the on-site programmable gate array FPGA access and itself into
Status register in the I/O equipment of row connection, to obtain the status information of I/O equipment, comprising:
On-site programmable gate array FPGA accesses the state in the I/O equipment being attached with itself according to preset access rule
Register, to obtain the status information of I/O equipment.
3. the method according to claim 1, wherein the CPU accesses field-programmable according to default rule
Status information memory space in gate array FPGA, to obtain the state letter of the I/O equipment stored in status information memory space
Breath, comprising:
CPU sends information to on-site programmable gate array FPGA by PCIe bus according to the preset period and reads instruction；
After on-site programmable gate array FPGA receives the information reading instruction, instruction is read to the information and is parsed
The state memory space address carried in instruction is read to obtain the information；
The status information that I/O equipment is read from the corresponding state memory space of the state memory space address, by reading
The status information of I/O equipment is packaged and returns to CPU；
CPU receives the status information for the I/O equipment that on-site programmable gate array FPGA returns, to obtain status information memory space
The status information of the I/O equipment of middle storage.
4. the method according to claim 1, wherein the CPU accesses field-programmable according to default rule
Status information memory space in gate array FPGA, to obtain the state letter of the I/O equipment stored in status information memory space
Breath, comprising:
PCIe interrupt signal is sent to CPU by on-site programmable gate array FPGA, carries I/O equipment in the PCIe interrupt signal
Mark；
CPU receives the PCIe interrupt signal, extracts the mark of the I/O equipment carried in the PCIe interrupt signal；
Information, which is sent, to on-site programmable gate array FPGA according to the mark of the I/O equipment reads instruction；
After on-site programmable gate array FPGA receives the information reading instruction, instruction is read to the information and is parsed
The state memory space address carried in instruction is read to obtain the information, the state memory space address is for the I/
State memory space address corresponding to the pre-assigned status information memory space of O device；
The status information that I/O equipment is read from the corresponding state memory space of the state memory space address, by reading
The status information of I/O equipment is packaged and returns to CPU；
CPU receives the status information for the I/O equipment that on-site programmable gate array FPGA returns, to obtain status information memory space
The status information of the I/O equipment of middle storage.
5. method according to any one of claims 1 to 4, which is characterized in that
The status information memory space is the corresponding memory space of on-site programmable gate array FPGA base address register.
6. a kind of acquisition system of I/O device status information, which is characterized in that the system comprises: CPU, field programmable gate
Array FPGA and at least one I/O equipment, the CPU are connected with on-site programmable gate array FPGA by PCIe bus
It connects, the on-site programmable gate array FPGA is attached with I/O equipment, is at the scene each I/ in programmable gate array FPGA
O device allocates independent status information memory space in advance；
The status register in I/O equipment that on-site programmable gate array FPGA access is attached with itself, is set with obtaining I/O
Standby status information；
The status information of acquired I/O equipment is stored to status information memory space corresponding with I/O equipment；
CPU is according to the status information memory space in default rule access on-site programmable gate array FPGA, to obtain state
The status information of the I/O equipment stored in information storage space.
7. system according to claim 6, which is characterized in that the on-site programmable gate array FPGA is especially by following
Mode obtains the status information of I/O equipment:
On-site programmable gate array FPGA accesses the state in the I/O equipment being attached with itself according to preset access rule
Register, to obtain the status information of I/O equipment.
8. system according to claim 6, which is characterized in that the CPU obtains status information especially by following manner
The status information of the I/O equipment stored in memory space:
CPU sends information to on-site programmable gate array FPGA by PCIe bus according to the preset period and reads instruction；
After on-site programmable gate array FPGA receives the information reading instruction, instruction is read to the information and is parsed
The state memory space address carried in instruction is read to obtain the information；
The status information that I/O equipment is read from the corresponding state memory space of the state memory space address, by reading
The status information of I/O equipment is packaged and returns to CPU；
CPU receives the status information for the I/O equipment that on-site programmable gate array FPGA returns, to obtain status information memory space
The status information of the I/O equipment of middle storage.
9. system according to claim 6, which is characterized in that the CPU obtains status information especially by following manner
The status information of the I/O equipment stored in memory space:
PCIe interrupt signal is sent to CPU by on-site programmable gate array FPGA, carries I/O equipment in the PCIe interrupt signal
Mark；
CPU receives the PCIe interrupt signal, extracts the mark of the I/O equipment carried in the PCIe interrupt signal；
Information, which is sent, to on-site programmable gate array FPGA according to the mark of the I/O equipment reads instruction；
After on-site programmable gate array FPGA receives the information reading instruction, instruction is read to the information and is parsed
The state memory space address carried in instruction is read to obtain the information, the state memory space address is for the I/
State memory space address corresponding to the pre-assigned status information memory space of O device；
The status information that I/O equipment is read from the corresponding state memory space of the state memory space address, by reading
The status information of I/O equipment is packaged and returns to CPU；
CPU receives the status information for the I/O equipment that on-site programmable gate array FPGA returns, to obtain status information memory space
The status information of the I/O equipment of middle storage.
10. system according to any one of claims 1 to 4, which is characterized in that
The status information memory space is the corresponding memory space of on-site programmable gate array FPGA base address register.
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| CN201811268334.1A CN109446130B (en) | 2018-10-29 | 2018-10-29 | Method and system for acquiring state information of I/O (input/output) equipment |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110059039A (en) * | 2019-03-25 | 2019-07-26 | 北京龙鼎源科技股份有限公司 | Input/output I/O polling method and I/O main website, system, storage medium |
| CN110413471A (en) * | 2019-07-29 | 2019-11-05 | 杭州迪普科技股份有限公司 | A kind of FPGA internal signal data capture method, system |
| CN114860343A (en) * | 2022-05-26 | 2022-08-05 | 苏州浪潮智能科技有限公司 | Speed regulation method, system, terminal and storage medium for accelerator card |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101140556A (en) * | 2007-09-11 | 2008-03-12 | 中兴通讯股份有限公司 | Method and device for realizing accessing multiple I2C slave device by programmable device |
| JP2010049510A (en) * | 2008-08-22 | 2010-03-04 | Koyo Electronics Ind Co Ltd | Bus arbitration system and programmable controller of multi-cpu configuration |
| CN101719110A (en) * | 2009-12-18 | 2010-06-02 | 烽火通信科技股份有限公司 | Real-time monitoring method of multipath I2C device in optical communication device |
| CN102012879A (en) * | 2010-12-10 | 2011-04-13 | 上海申瑞电力科技股份有限公司 | High-capacity data acquisition device and data transmission method thereof |
| CN102253913A (en) * | 2011-05-30 | 2011-11-23 | 神州数码网络(北京)有限公司 | Device for carrying out state acquisition and output control on multi-board-card port |
| JP2012221373A (en) * | 2011-04-12 | 2012-11-12 | Digital Electronics Corp | Computer system |
| CN105765545A (en) * | 2014-07-15 | 2016-07-13 | 华为技术有限公司 | Sharing method and device for PCIe I/O device and interconnection system |
| CN205385545U (en) * | 2016-02-01 | 2016-07-13 | 信阳师范学院 | Real -time image information treater based on FPGA |
| WO2017112345A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Speculative enumeration of bus-device-function address space |
| CN108227614A (en) * | 2018-01-25 | 2018-06-29 | 郑州云海信息技术有限公司 | A kind of data flow control module based on FPGA, control method and circuit |
| CN108595353A (en) * | 2018-04-09 | 2018-09-28 | 杭州迪普科技股份有限公司 | A kind of method and device of the control data transmission based on PCIe buses |
| CN108668106A (en) * | 2017-03-28 | 2018-10-16 | 杭州海康威视数字技术股份有限公司 | Camera status acquisition methods, video camera and camera chain |
-
2018
- 2018-10-29 CN CN201811268334.1A patent/CN109446130B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101140556A (en) * | 2007-09-11 | 2008-03-12 | 中兴通讯股份有限公司 | Method and device for realizing accessing multiple I2C slave device by programmable device |
| JP2010049510A (en) * | 2008-08-22 | 2010-03-04 | Koyo Electronics Ind Co Ltd | Bus arbitration system and programmable controller of multi-cpu configuration |
| CN101719110A (en) * | 2009-12-18 | 2010-06-02 | 烽火通信科技股份有限公司 | Real-time monitoring method of multipath I2C device in optical communication device |
| CN102012879A (en) * | 2010-12-10 | 2011-04-13 | 上海申瑞电力科技股份有限公司 | High-capacity data acquisition device and data transmission method thereof |
| JP2012221373A (en) * | 2011-04-12 | 2012-11-12 | Digital Electronics Corp | Computer system |
| CN102253913A (en) * | 2011-05-30 | 2011-11-23 | 神州数码网络(北京)有限公司 | Device for carrying out state acquisition and output control on multi-board-card port |
| CN105765545A (en) * | 2014-07-15 | 2016-07-13 | 华为技术有限公司 | Sharing method and device for PCIe I/O device and interconnection system |
| WO2017112345A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Speculative enumeration of bus-device-function address space |
| CN205385545U (en) * | 2016-02-01 | 2016-07-13 | 信阳师范学院 | Real -time image information treater based on FPGA |
| CN108668106A (en) * | 2017-03-28 | 2018-10-16 | 杭州海康威视数字技术股份有限公司 | Camera status acquisition methods, video camera and camera chain |
| CN108227614A (en) * | 2018-01-25 | 2018-06-29 | 郑州云海信息技术有限公司 | A kind of data flow control module based on FPGA, control method and circuit |
| CN108595353A (en) * | 2018-04-09 | 2018-09-28 | 杭州迪普科技股份有限公司 | A kind of method and device of the control data transmission based on PCIe buses |
Non-Patent Citations (3)
| Title |
|---|
| D. TANG: ""DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance"", 《 HPCA - 16 2010 THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE》 * |
| 邹丽新: "《单片微型计算机原理及接口技术》", 31 August 2018 * |
| 龚坚: ""一种基于Rocket I/O的视频数据采集和高速串行传输系统的设计与实现"", 《现代电子技术》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110059039A (en) * | 2019-03-25 | 2019-07-26 | 北京龙鼎源科技股份有限公司 | Input/output I/O polling method and I/O main website, system, storage medium |
| CN110413471A (en) * | 2019-07-29 | 2019-11-05 | 杭州迪普科技股份有限公司 | A kind of FPGA internal signal data capture method, system |
| CN114860343A (en) * | 2022-05-26 | 2022-08-05 | 苏州浪潮智能科技有限公司 | Speed regulation method, system, terminal and storage medium for accelerator card |
| CN114860343B (en) * | 2022-05-26 | 2024-03-26 | 苏州浪潮智能科技有限公司 | Acceleration card rate adjustment method, system, terminal and storage medium |
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