CN114860343B - Acceleration card rate adjustment method, system, terminal and storage medium - Google Patents
Acceleration card rate adjustment method, system, terminal and storage medium Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention relates to the technical field of ARM servers, and particularly provides a method, a system, a terminal and a storage medium for adjusting an acceleration card speed, wherein the method comprises the following steps: identifying an acceleration card at a server start stage; reading capability ID information of an acceleration card; and reading a corresponding speed value based on the capability ID information, and writing the speed value into a speed setting register of the accelerator card. The invention breaks through the limitation that the ARM architecture can only read the first 250 bytes of the offset address through the PC I configuration space, breaks through the problems that the data after the offset address is 250 bytes of the PC I configuration space cannot be read and the actual rate of the PC I is set by default, further supports the adaptability and practicality of the ARM server, is convenient for introducing more PC I components into the ARM architecture server, and is mainly protected.
Description
Technical Field
The invention belongs to the technical field of ARM servers, and particularly relates to a method, a system, a terminal and a storage medium for adjusting an acceleration card speed.
Background
The ARM server has higher and higher mirror output rate along with the improvement of energy consumption ratio and cost performance, and is not involved in ARM no matter a cloud primary processor for general computing or an AI/ML accelerator for reasoning training, so that an attractive high cost performance alternative scheme is presented for cloud manufacturers. The acceleration card of the ARM server has performance bottleneck at present, namely the speed of finding the card under the system after the acceleration card realizes support is always kept at 5.0GT/S, but not the speed of the maximum support of the card.
Disclosure of Invention
Aiming at the problem that the speed of an accelerator card in an ARM server can not reach the maximum speed in the prior art, the invention provides an accelerator card speed adjusting method, an accelerator card speed adjusting system, a terminal and a storage medium, so as to solve the technical problems.
In a first aspect, the present invention provides a method for adjusting an acceleration card rate, including:
identifying an acceleration card at a server start stage;
reading capability ID information of an acceleration card;
and reading a corresponding speed value based on the capability ID information, and writing the speed value into a speed setting register of the accelerator card.
Further, identifying the accelerator card at the server start-up stage includes:
in the BIOS starting process, obtaining the device ID and the vendor ID of the external device enumerated by the local bus;
judging whether the external equipment is an acceleration card or not according to the equipment ID and the supplier ID of the external equipment.
Further, the capability ID information of the accelerator card is read, including:
the capability ID information of the offset 0x34 register is read by the local bus configuration space read function and checked whether the capability ID information is 0x26.
Further, reading a corresponding rate value based on the capability ID information, and writing the rate value into a rate setting register of the accelerator card, including:
and if the capability ID information is 0X26, reading the value of an offset address 0X34 register of the capability ID information, and writing the read value into a speed setting register of the accelerator card.
In a second aspect, the present invention provides an accelerator card rate adjustment system comprising:
the device identification unit is used for identifying the acceleration card in the starting stage of the server;
a device reading unit for reading capability ID information of the accelerator card;
and the rate adjusting unit is used for reading the corresponding rate value based on the capability ID information and writing the rate value into a rate setting register of the accelerator card.
Further, the device identification unit includes:
the ID acquisition module is used for acquiring the device ID and the vendor ID of the external device enumerated by the local bus in the BIOS starting process;
and the ID identification module is used for judging whether the external equipment is an accelerator card or not according to the equipment ID of the external equipment and the supplier ID.
Further, the device reading unit includes:
and the capability reading module is used for reading the capability ID information of the offset 0x34 register through the local bus configuration space reading function and checking whether the capability ID information is 0x26.
Further, the rate adjustment unit includes:
and the rate writing module is used for reading the value of the offset address 0X34 register of the capability ID information if the capability ID information is 0X26, and writing the read value into the rate setting register of the accelerator card.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program,
the processor is configured to call and run the computer program from the memory, so that the terminal performs the method of the terminal as described above.
In a fourth aspect, there is provided a computer storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method of the above aspects.
The method, the system, the terminal and the storage medium for adjusting the speed of the accelerator card have the advantages that in the PCI enumeration process when the BIOS is started, the Device ID and the Vendor ID information are used for judging and confirming whether the accelerator card exists or not, the offset address of 0x34 is read through the PCI configuration space reading function for judging the capacity ID information, and confirming whether the capacity ID information is the capacity ID information of the Gen4 speed, if so, the numerical value of a 0x34 register is read, and the actual supporting speed of the accelerator card is set to be Gen4. The invention breaks through the limitation that the ARM architecture can only read the first 250 bytes of the offset address through the PCI configuration space, breaks through the problems that the data after the offset address of the PCI configuration space is 250 bytes can not be read and the actual speed of the PCI is set by default, further supports the suitability and the practicability of the ARM server, is convenient for introducing more PCI components into the ARM architecture server, and is emphasized and protected.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic flow chart of a method of one embodiment of the invention.
FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
The following explains key terms appearing in the present invention.
The application of ARM servers by domestic cloud manufacturers is more prone to game, coding, video and audio services, so that an acceleration card supporting the h.264 video compression standard becomes a bottleneck point of ARM server service layout, and the ARM processor is excellent in test due to the high core number of ARM architecture and 2x 128-bit SIMD vector units of each core, and coding performance is 1.2 times and 2.2 times higher than that of AMD Milan and Intel Icelake of x86 respectively; the performance of each watt is respectively 1.4 to 2.4 times of that of each watt, so the advantage of the ARM architecture server promotes each cloud factory to carry out the business support work of the acceleration card, but the speed of finding the card under the system after the acceleration card is supported is always kept at 5.0GT/S, rather than the maximum supported speed of the card.
The ARM server is increasingly applied to the accelerator card and supports the self-adaptive function of the link rate by default, and the practical result is that the link rate is checked under the system and is not the maximum link rate Gen4 supported by the ARM server, so that the accelerator card loses the performance of the accelerator card, and the ARM server is meaningless. Meanwhile, the ARM server has the defects that the ARM server cannot manually set the speed of the equipment in advance, but can set the speed of the PCI equipment after the equipment is found and identified, so that the waste of human resources is caused, the ARM server for deploying accelerator cards in batches is also not facilitated, the standard PCI protocol is provided with speed setting registers of space information which are in PCIE extended Capability Header x26 (GEN 4) two tables and are positioned within the first 250 bytes of PCI configuration space offset, but PCIE extended Capability Header x26 (GEN 4) two tables of the accelerator card are positioned at 300 bytes of PCI configuration space, the ARM cannot judge the actual supporting speed of the positioning accelerator card during PCI enumeration, and the speed is set according to the default Gen2 speed, so that the link speed of the accelerator card is seen to be the root cause of the Gen2 speed not Gen4 speed under the system. In order to realize the function of automatically identifying the accelerator card and supporting the Gen4 speed, the design of the accelerator card is combined to be adjusted to meet the requirement of automatically identifying and setting the accelerator card to be in a Gen4 state, so that the advantage that the accelerator card is identified as Gen4 under the system and the performance of the accelerator card is not influenced is realized.
FIG. 1 is a schematic flow chart of a method of one embodiment of the invention. The execution body of fig. 1 may be an acceleration card rate adjustment system.
As shown in fig. 1, the method includes:
step 110, identifying an acceleration card in a server start-up phase;
step 120, reading capability ID information of the accelerator card;
and 130, reading a corresponding speed value based on the capability ID information, and writing the speed value into a speed setting register of the accelerator card.
The invention breaks through the limitation that the ARM architecture can only read the first 250 bytes of the offset address through the PCI configuration space, breaks through the problems that the data after the offset address of the PCI configuration space is 250 bytes can not be read and the actual speed of the PCI is set by default, further supports the suitability and the practicability of the ARM server, is convenient for introducing more PCI components into the ARM architecture server, and is emphasized and protected.
In order to facilitate understanding of the present invention, the following describes the acceleration card rate adjustment method according to the present invention in conjunction with the process of adjusting the acceleration card rate in the embodiment.
Specifically, the acceleration card rate adjustment method includes:
s1, identifying the accelerator card in a server starting stage.
In the BIOS starting process, obtaining the device ID and the vendor ID of the external device enumerated by the local bus; judging whether the external equipment is an acceleration card or not according to the equipment ID and the supplier ID of the external equipment.
The PCI (PCI (Peripheral Component Interconnect)) is a standard for defining local buses introduced by Intel (Intel) corporation in 1991 during BIOS boot-up, which allows Device information to be determined by Device Id and Vendor Id when up to 10 PCI compliant expansion cards are installed in a computer for enumeration. If the device is not the acceleration card, setting and starting according to the PCI link rate of the card which is actually read. The specific method for judging whether the external device is an acceleration card according to the device ID of the external device and the supplier ID is to judge whether the format content of the device ID accords with the format content of the acceleration card and judge whether the supplier ID belongs to the acceleration card supplier.
S2, reading capability ID information of the accelerator card.
If the external device is identified as the accelerator card in the step S1, the capability ID information of the offset 0x34 register is read by the PCI configuration space reading function, and whether the acquired capability ID information is 0x26 is determined.
If the capability ID information with the capability value of 0X26 is not read, the reading function is exited, and the PCI link rate is set according to the value actually acquired by the BIOS to perform rate setting.
S3, reading a corresponding speed value based on the capability ID information, and writing the speed value into a speed setting register of the accelerator card.
If the capability ID information value of 0X26 is read in step S2, the value of the offset address 0X34 register of the capability ID is read, and the read value information is written into the rate setting register of the current PCI device, so as to realize the setting of the supported accelerator card rate Gen4.
After PCI enumeration is completed, the system is normally started to enter the OS and checks whether the speed of the acceleration card under the OS is Gen4, and when the acceleration card is accessed and the speed is Gen4, the system meets the expected target.
The conventional PCI rate reading configuration space is obtained through judging the capability ID information, but the PCI enumeration process of the BIOS is only within the first 250 bytes of the PCI configuration space by default, so that the speed reading and setting of the actual supported speed of a standard PCI card is not problematic, but the speed of the ARM architecture cannot accurately obtain the speed supported by the speed card due to the fact that the speed of the speed card exceeds the first 250 bytes of the PCI configuration space, so that the speed register actually supported by the speed card is further read, namely the PCI configuration space 0x34 register is obtained and the actual supported speed is set and supported, and the key point of the invention is that whether the speed card is accessed or not is judged through PCI enumeration of the BIOS and the actual offset position of the capability ID register is read through the PCI configuration space offset register and the speed setting value of the Gen4 is read to actually set so as to support the realization of the Gen4 speed under the ARM architecture supported speed card system, and the actual performance requirement is met.
The invention judges and confirms whether the acceleration card exists through Device Id and Vendor ID information in PCI enumeration in BIOS starting, judges the capability ID information through reading the offset address of 0x34 by PCI configuration space reading function, confirms whether the capability ID information is Gen4 speed capability ID information, if yes, reads the value of the 0x34 register and sets the actual supporting speed of the acceleration card as Gen4.
As shown in fig. 2, the system 200 includes:
a device identification unit 210 for identifying the accelerator card at the start-up stage of the server;
a device reading unit 220 for reading capability ID information of the accelerator card;
and a rate adjustment unit 230 for reading the corresponding rate value based on the capability ID information and writing the rate value into a rate setting register of the accelerator card.
Optionally, as an embodiment of the present invention, the device identification unit includes:
the ID acquisition module is used for acquiring the device ID and the vendor ID of the external device enumerated by the local bus in the BIOS starting process;
and the ID identification module is used for judging whether the external equipment is an accelerator card or not according to the equipment ID of the external equipment and the supplier ID.
Optionally, as an embodiment of the present invention, the device reading unit includes:
and the capability reading module is used for reading the capability ID information of the offset 0x34 register through the local bus configuration space reading function and checking whether the capability ID information is 0x26.
Optionally, as an embodiment of the present invention, the rate adjustment unit includes:
and the rate writing module is used for reading the value of the offset address 0X34 register of the capability ID information if the capability ID information is 0X26, and writing the read value into the rate setting register of the accelerator card.
Fig. 3 is a schematic structural diagram of a terminal 300 according to an embodiment of the present invention, where the terminal 300 may be used to execute the acceleration card rate adjustment method according to the embodiment of the present invention.
The terminal 300 may include: a processor 310, a memory 320 and a communication unit 330. The components may communicate via one or more buses, and it will be appreciated by those skilled in the art that the configuration of the server as shown in the drawings is not limiting of the invention, as it may be a bus-like structure, a star-like structure, or include more or fewer components than shown, or may be a combination of certain components or a different arrangement of components.
The memory 320 may be used to store instructions for execution by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile memory terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. The execution of the instructions in memory 320, when executed by processor 310, enables terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by running or executing software programs and/or modules stored in the memory 320, and invoking data stored in the memory. The processor may be comprised of an integrated circuit (Integrated Circuit, simply referred to as an IC), for example, a single packaged IC, or may be comprised of a plurality of packaged ICs connected to the same function or different functions. For example, the processor 310 may include only a central processing unit (Central Processing Unit, simply CPU). In the embodiment of the invention, the CPU can be a single operation core or can comprise multiple operation cores.
And a communication unit 330 for establishing a communication channel so that the storage terminal can communicate with other terminals. Receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium in which a program may be stored, which program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (random access memory, RAM), or the like.
Therefore, the invention judges the PCI enumeration through the Device Id and the Vendor ID information and confirms whether the accelerator card exists or not in the PCI enumeration process when the BIOS is started, reads the offset address of 0x34 to judge the capability ID information through the PCI configuration space reading function and confirms whether the capability ID information is the capability ID information of Gen4 rate, if so, reads the value of the 0x34 register and sets the actual supporting rate of the accelerator card as Gen4. The invention breaks through the limitation that the ARM architecture can only read the first 250 bytes of the offset address through the PCI configuration space, and breaks through the problems that the data after the offset address of the PCI configuration space is 250 bytes can not be read and the actual speed of the PCI is set by default, thereby further supporting the suitability and practicality of the ARM server, facilitating the introduction of more PCI components into the ARM architecture server, so that the technical effects achieved by the embodiment can be highlighted and protected, and the description is omitted.
It will be apparent to those skilled in the art that the techniques of embodiments of the present invention may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solution in the embodiments of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium such as a U-disc, a mobile hard disc, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, etc. various media capable of storing program codes, including several instructions for causing a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the method described in the embodiments of the present invention.
The same or similar parts between the various embodiments in this specification are referred to each other. In particular, for the terminal embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference should be made to the description in the method embodiment for relevant points.
In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods may be implemented in other ways. For example, the system embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, system or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
Although the present invention has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and it is intended that all such modifications and substitutions be within the scope of the present invention/be within the scope of the present invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. An acceleration card rate adjustment method, comprising:
identifying an acceleration card at a server start stage;
reading capability ID information of an acceleration card;
reading a corresponding rate value based on the capability ID information, and writing the rate value into a rate setting register of an acceleration card;
identifying the accelerator card at the start-up phase of the server, comprising:
in the BIOS starting process, obtaining the device ID and the vendor ID of the external device enumerated by the local bus;
judging whether the external equipment is an acceleration card or not according to the equipment ID of the external equipment and the supplier ID;
the ability ID information of the acceleration card is read, including:
reading capability ID information of an offset 0x34 register through a local bus configuration space reading function, and checking whether the capability ID information is 0x26;
reading a corresponding rate value based on the capability ID information, and writing the rate value into a rate setting register of an accelerator card, comprising:
and if the capability ID information is 0X26, reading the value of an offset address 0X34 register of the capability ID information, and writing the read value into a speed setting register of the accelerator card.
2. An acceleration card rate adjustment system, comprising:
the device identification unit is used for identifying the acceleration card in the starting stage of the server;
a device reading unit for reading capability ID information of the accelerator card;
the speed adjusting unit is used for reading the corresponding speed value based on the capability ID information and writing the speed value into a speed setting register of the accelerator card;
the device identification unit includes:
the ID acquisition module is used for acquiring the device ID and the vendor ID of the external device enumerated by the local bus in the BIOS starting process;
the ID identification module is used for judging whether the external equipment is an acceleration card or not according to the equipment ID of the external equipment and the ID of the provider;
the device reading unit includes:
the capability reading module is used for reading the capability ID information of the offset 0x34 register through a local bus configuration space reading function and checking whether the capability ID information is 0x26;
the rate adjustment unit includes:
and the rate writing module is used for reading the value of the offset address 0X34 register of the capability ID information if the capability ID information is 0X26, and writing the read value into the rate setting register of the accelerator card.
3. A terminal, comprising:
a processor;
a memory for storing execution instructions of the processor;
wherein the processor is configured to perform the method of claim 1.
4. A computer readable storage medium storing a computer program, which when executed by a processor implements the method of claim 1.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108776595A (en) * | 2018-06-11 | 2018-11-09 | 郑州云海信息技术有限公司 | A kind of recognition methods, device, equipment and the medium of the video card of GPU servers |
| CN109446130A (en) * | 2018-10-29 | 2019-03-08 | 杭州迪普科技股份有限公司 | A kind of acquisition methods and system of I/O device status information |
| CN109885438A (en) * | 2019-02-27 | 2019-06-14 | 苏州浪潮智能科技有限公司 | A kind of FPGA method for testing reliability, system, terminal and storage medium |
| CN110083558A (en) * | 2019-06-03 | 2019-08-02 | 苏州长江睿芯电子科技有限公司 | One kind is calculated for adaptively programmable storage accelerates card device |
| CN110377469A (en) * | 2019-07-12 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of detection system and method for PCIE device |
| CN111045964A (en) * | 2019-12-06 | 2020-04-21 | 思尔芯(上海)信息科技有限公司 | PCIE interface-based high-speed transmission method, storage medium and terminal |
| CN111722877A (en) * | 2020-06-11 | 2020-09-29 | 苏州浪潮智能科技有限公司 | PCIE configuration identification method and related assembly |
| CN112732616A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | BMC starting method, device and equipment based on SPI controller |
| CN114138527A (en) * | 2021-11-12 | 2022-03-04 | 浪潮电子信息产业股份有限公司 | Method, device and medium for improving performance of server |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5374268B2 (en) * | 2009-07-28 | 2013-12-25 | ラピスセミコンダクタ株式会社 | Information processing device |
-
2022
- 2022-05-26 CN CN202210581392.XA patent/CN114860343B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108776595A (en) * | 2018-06-11 | 2018-11-09 | 郑州云海信息技术有限公司 | A kind of recognition methods, device, equipment and the medium of the video card of GPU servers |
| CN109446130A (en) * | 2018-10-29 | 2019-03-08 | 杭州迪普科技股份有限公司 | A kind of acquisition methods and system of I/O device status information |
| CN109885438A (en) * | 2019-02-27 | 2019-06-14 | 苏州浪潮智能科技有限公司 | A kind of FPGA method for testing reliability, system, terminal and storage medium |
| CN110083558A (en) * | 2019-06-03 | 2019-08-02 | 苏州长江睿芯电子科技有限公司 | One kind is calculated for adaptively programmable storage accelerates card device |
| CN110377469A (en) * | 2019-07-12 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of detection system and method for PCIE device |
| CN111045964A (en) * | 2019-12-06 | 2020-04-21 | 思尔芯(上海)信息科技有限公司 | PCIE interface-based high-speed transmission method, storage medium and terminal |
| CN111722877A (en) * | 2020-06-11 | 2020-09-29 | 苏州浪潮智能科技有限公司 | PCIE configuration identification method and related assembly |
| CN112732616A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | BMC starting method, device and equipment based on SPI controller |
| CN114138527A (en) * | 2021-11-12 | 2022-03-04 | 浪潮电子信息产业股份有限公司 | Method, device and medium for improving performance of server |
Non-Patent Citations (1)
| Title |
|---|
| GSP与PCI交互的FPGA接口设计与实现;王淑芳;薛崇峰;;现代制造工程(第12期);全文 * |
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