JP2012221373A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system for which the number of pins of a CPU required for achieving interruption is small and polling is not required to discriminate from which I/O device the interruption is requested.SOLUTION: The CPU includes an input port for an interruption request signal and an output port for a timing reference signal, and the I/O device includes an input port for the timing reference signal and an output port for the interruption request signal. The plurality of output ports for the interruption request signal are wired OR connected to the input port for the interruption request signal. When requesting the interruption to the CPU, the I/O device utilizes the timing reference signal and turns the interruption request signal to be outputted from the output port for the interruption request signal to an active state in a timing section allocated individually beforehand to each I/O device.

Description

  The present invention relates to a computer system including a CPU (Central Processing Unit) and a plurality of I / O devices (input / output devices).

  In a conventional computer system, an interrupt request notification from the I / O device to the CPU is generally performed by one of the following two methods (first interrupt request notification method and second interrupt request notification method). Met.

  First, the first interrupt request notification method will be described. FIG. 11 is a diagram illustrating a schematic configuration example of a conventional computer system that performs the first interrupt request notification method. FIG. 11 illustrates a configuration in the case where the computer system includes 15 I / O devices. In the conventional computer system shown in FIG. 11, the CPU 11 has as many input ports (interrupt request signal input ports) I_ # 1 to I_ # 15 as the number of I / O devices 12_ # 1 to 12_ # 15 that receive interrupt request signals. 15 interrupt request signal transmission lines corresponding to the number of the I / O devices 12_ # 1 to 12_ # 15, that is, 15 are provided, and the interrupt request signal input ports I_ # 1 to I_ # 1 of the CPU 1 are provided by the interrupt request signal transmission lines. The I_ # 15 is connected to the interrupt request signal output port O of each of the I / O devices 12_ # 1 to 12_ # 15. However, if a priority encoder (not shown) in the CPU 11 is externally attached, the number of interrupt request signal input ports of the CPU 11 can be reduced from 15 to 4.

  In the conventional computer system shown in FIG. 11, the CPU 11 can determine by hardware the I / O device from which the interrupt request has been made. Then, according to the determination result, the CPU 11 reads the interrupt vector for the I / O device that requested the interrupt from the main memory 13, and based on the read vector (the start address of the service routine), the I / O device that requested the interrupt. The interrupt service routine for the O device is accessed, and the interrupt service process for the I / O device that requested the interrupt is executed. For example, if the I / O device that made the interrupt request is the I / O device 12_ # 2, the interrupt vector for the I / O device that made the above interrupt request becomes the “maskable interrupt # 2 vector”, and the above interrupt request The interrupt service routine for the I / O device that has been performed becomes the “interrupt # 2 service routine”. Note that the value of the program counter PC and the like is saved in the memory stack using the stack pointer SP before execution of the interrupt service process, and is restored after completion of the interrupt service process.

  Next, the second interrupt request notification method will be described. FIG. 12 is a diagram illustrating a schematic configuration example of a conventional computer system that performs the second interrupt request notification method. FIG. 12 illustrates the configuration in the case where the computer system includes 15 I / O devices, as in FIG. In the conventional computer system shown in FIG. 12, the CPU 21 has one interrupt request signal input port I, and an interrupt request signal output of an open drain output or an open collector output of each of the I / O devices 22_ # 1 to 22_ # 15. The port O is wired OR connected to the interrupt request signal input port I of the CPU 21, and the interrupt request signal input port I of the CPU 21 is connected to the pull-up resistor 24. In the conventional computer system shown in FIG. 12, when an interrupt request signal is output from any one or more I / O devices, the interrupt request signal input port I of the CPU 1 is statically low. Therefore, in the conventional computer system shown in FIG. 12, the CPU 21 cannot determine by hardware which I / O device has made the interrupt request. For this reason, when the interrupt request signal input port I becomes Low, the CPU 21 reads the maskable interrupt vector from the main memory 23 and accesses the service routine common to the interrupts based on the read vector (the start address of the service routine). The interrupt service processing is executed after determining by polling which I / O device is requesting an interrupt by a service routine (software) common to interrupts. Note that the value of the program counter PC and the like is saved in the memory stack using the stack pointer SP before execution of the interrupt service process, and is restored after completion of the interrupt service process.

JP 7-28392 A (paragraphs 0004 and 0005)

  The first interrupt request notification method described above has the advantage that polling is not required to determine which I / O device has received an interrupt request, and the interrupt service routine can be made independent for each I / O device. While having the advantage of being able to do so, it has the disadvantage of increasing the number of CPU pins required to implement interrupts.

  The second interrupt request notification method described above has the advantage that the number of CPU pins required for realizing the interrupt is small, but in order to determine which I / O device has received the interrupt request. However, the interrupt service routine is common to all I / O devices, and the interrupt service routine cannot be made independent for each I / O device.

  In view of the above situation, the present invention provides a computer system that requires a small number of CPU pins for realizing an interrupt and that does not require polling to determine which I / O device has made an interrupt request. The purpose is to provide.

  In order to achieve the above object, a computer system according to the present invention is a computer system including a CPU and a plurality of I / O devices, and the CPU includes an interrupt request signal input port and a timing reference signal output port. The I / O device includes a timing reference signal input port and an interrupt request signal output port, wherein a plurality of the interrupt request signal output ports are wired-ORed to the interrupt request signal input port, and the CPU Generating a timing reference signal having a constant period and a pulse width smaller than 1/3 of the predetermined period, and outputting the timing reference signal from the timing reference signal output port. When the interrupt request is made, the timing input to the timing reference signal input port In the timing interval that is individually assigned in advance to each of the I / O devices among three or more timing intervals obtained by dividing one period of the timing reference signal into three or more using a reference signal, the interrupt The interrupt request signal output from the request signal output port is activated, and the CPU determines whether or not the interrupt request signal input to the interrupt request signal input port is in the active state for each timing interval. To be configured (first configuration).

  According to the above first configuration, the number of CPU pins required to realize an interrupt is only two, ie, an interrupt request signal input port and a timing reference signal output port. In addition, according to the first configuration, it is possible to determine which I / O device has received the interrupt request based on the timing section in which the interrupt request signal is in the active state. Does not require polling to determine if it was.

  The computer system of the first configuration further includes a memory for storing an interrupt service routine for each I / O device, and the CPU is based on a determination result of whether or not the interrupt request signal is in an active state. It is preferable that the configuration is such that the interrupt service routine of the I / O device that requested the interrupt is accessed and the interrupt service processing for the I / O device that requested the interrupt is executed (second configuration).

  According to the second configuration, the interrupt service routine can be made independent for each I / O device.

  In the computer system of the first configuration or the second configuration, the pulse width of the timing reference signal is 1 / N (N is a natural number of 3 or more) of a fixed period of the timing reference signal, and the timing The section is a section obtained by dividing a predetermined period of the timing reference signal by N with reference to the rising edge of the timing reference signal. When the I / O device makes an interrupt request to the CPU, the timing is A plurality of types of timing signals that approximate the plurality of types of delayed signals obtained by delaying the timing reference signal by an integral multiple of the pulse width of the timing reference signal using the timing reference signal input to the reference signal input port A timing that is assigned in advance to each of the I / O devices from among the plurality of types of timing signals. By selecting the timing signal corresponding to the interrupt interval, the interrupt request signal output from the interrupt request signal output port is activated in the timing interval assigned in advance to each of the I / O devices. 3).

  According to the third configuration, the I / O device uses the clock signal having at least one of a phase and a period different from the interrupt processing clock signal used when the timing reference signal is generated on the CPU side. Can be generated. Therefore, it is not necessary for the I / O device to prepare a clock signal having the same phase and cycle as the interrupt processing clock signal used when generating the timing reference signal on the CPU side.

  In the computer system having the third configuration, the CPU preferably has a configuration (fourth configuration) for determining whether or not the interrupt request signal is in an active state substantially at the center of the timing interval. .

  According to the fourth configuration, it is possible to reliably prevent a problem from occurring due to a timing signal shift caused by approximation.

  According to the present invention, it is possible to realize a computer system in which the number of CPU pins required for realizing an interrupt is small and no polling is required to determine which I / O device has made an interrupt request. .

It is a figure which shows schematic structure of the computer system which concerns on one Embodiment of this invention. It is a timing chart which shows an example of various signals in a computer system concerning one embodiment of the present invention. It is a timing chart which shows the other example of the various signals in the computer system which concerns on one Embodiment of this invention. It is a figure which shows the example of 1 circuit structure of the I / O part of CPU with which the computer system which concerns on one Embodiment of this invention is provided. It is a timing chart which shows an example of the various signals of the I / O part of CPU with which the computer system concerning one embodiment of the present invention is provided. It is a timing chart which shows a timing reference signal and its delay signal. It is a figure which shows the example of 1 circuit structure of the I / O part of CPU with which the computer system which concerns on one Embodiment of this invention is provided. It is a timing chart which shows an example of the various signals of the I / O part of CPU with which the computer system concerning one embodiment of the present invention is provided. It is a figure which shows the rising timing of each decoding signal. It is a figure which shows the other circuit structural example of the I / O part of CPU with which the computer system which concerns on one Embodiment of this invention is provided. It is a figure which shows the further another circuit structural example of the I / O part of CPU with which the computer system which concerns on one Embodiment of this invention is provided. It is a figure which shows the example of schematic structure of the conventional computer system which performs the 1st interrupt request notification system. It is a figure which shows the example of schematic structure of the conventional computer system which performs the 2nd interruption request notification system.

  Embodiments of the present invention will be described below with reference to the drawings.

<Overall configuration of computer system>
FIG. 1 shows a schematic configuration of a computer system according to an embodiment of the present invention. The computer system according to an embodiment of the present invention shown in FIG. 1 includes a CPU 1, 15 I / O devices 2 — # 1 to 2 — # 15, a main memory 3, and a pull-up resistor 4. The number of I / O devices included in the computer system according to the present invention is not particularly limited as long as it is two or more. However, in the computer system according to the embodiment of the present invention shown in FIG. It is set as the structure provided with O apparatus.

  In the computer system according to the embodiment of the present invention shown in FIG. 1, the CPU 1 has one interrupt request signal input port I, and the open drain output or the open collector output of each of the I / O devices 2_ # 1 to 2_ # 15. The interrupt request signal output port O of the CPU 1 is wired OR connected to the interrupt request signal input port I of the CPU 1, and the interrupt request signal input port I of the CPU 1 is connected to the pull-up resistor 4.

  Furthermore, in the computer system according to the embodiment of the present invention shown in FIG. 1, the CPU 1 includes one timing reference signal output port O, and the timing reference signal IREF is sent from the timing reference signal output port O of the CPU 1 to each I / O. Supplied to the timing reference signal input port I of the O devices 2_ # 1 to 2_ # 15.

  The CPU 1 generates a timing reference signal IREF that is a pulse signal having a constant cycle and whose pulse width is 1 / N of the fixed cycle. Note that N is a natural number of 3 or more, and in this embodiment, N = 16.

  The I / O device 2_ # i (i is a natural number between 1 and 15) uses the timing reference signal IREF input to the timing reference signal input port I when making an interrupt request to the CPU 1 to perform timing. Among timing intervals T0 to T15 (see FIGS. 2A and 2B) in which one cycle of the reference signal IREF is divided into N based on the rising edge of the timing reference signal IREF, in the timing interval Ti assigned in advance to the I / O device 2_ # i The interrupt request signal output from the interrupt request signal output port O is set to the low state, that is, the active state.

  Therefore, an ideal timing chart of the interrupt request signal ITRQ_L input to the interrupt request signal input port I of the CPU 1 is as shown in FIG. 2A when there is an interrupt request from the I / O device 2_ # 2, for example. For example, when there is an interrupt request from the I / O device 2_ # 4 and the I / O device 2_ # 12, the result is as shown in FIG. 2B.

  The CPU 1 determines from which I / O device an interrupt request has been made by determining whether or not the interrupt request signal ITRQ_L input to the interrupt request signal input port I is in a low state, that is, in an active state, for each timing section. , And whether the request satisfies the interrupt priority, the CPU 1 can determine by hardware. Then, according to the determination result, the CPU 1 reads the interrupt vector for the I / O device that requested the interrupt from the main memory 3, and based on the read vector (start address of the service routine), the I / O device that requested the interrupt. The interrupt service routine for the O device is accessed, and the interrupt service process for the I / O device that requested the interrupt is executed. For example, if the I / O device that made the interrupt request is I / O device 2_ # 2, the interrupt vector for the I / O device that made the above interrupt request becomes “maskable interrupt # 2 vector”, and the above interrupt request The interrupt service routine for the I / O device that has been performed becomes the “interrupt # 2 service routine”. Note that the value of the program counter PC and the like is saved in the memory stack using the stack pointer SP before execution of the interrupt service process, and is restored after completion of the interrupt service process.

  The computer system according to the embodiment of the present invention shown in FIG. 1 has the advantage that only two CPU pins are required to realize an interrupt, and to determine which I / O device has made an interrupt request. There is an advantage that no polling is required, and an interrupt service routine can be made independent for each I / O device.

<Configuration of CPU I / O Portion>
Next, the I / O portion of the CPU 1 will be described. One circuit configuration example of the I / O portion of the CPU 1 is shown in FIG. An example of various signals in the I / O portion of the CPU 1 is shown in the time chart of FIG. The time chart shown in FIG. 4 is an example when there is an interrupt request from each of the I / O device 2_ # 1, I / O device 2_ # 2, I / O device 2_ # 7, and I / O device 2_ # 15. Is shown.

  The frequency divider 101 divides the clock signal CPU_CLK of the CPU 1 to generate an interrupt processing clock signal INTERRUPT_CLK (see FIG. 4). The 4-bit binary counter 102 performs a count operation in synchronization with the interrupt processing clock signal INTERRUPT_CLK. The counter values (decimal numbers) 0 to 15 of the 4-bit binary counter 102 correspond to the timing sections T0 to T15 shown in FIGS. 2A and 2B. The AND gate 103 sends the logical product IREF0 (see FIG. 4) of all the bits of the 4-bit binary counter 102 to the D terminal of the D flip-flop 104. The D flip-flop 104 holds the state of the output signal IREF0 of the AND gate 103 at the rising timing of the interrupt processing clock signal INTERRUPT_CLK, and outputs it from the Q terminal as the timing reference signal IREF (see FIG. 4). The timing reference signal IREF output from the Q terminal of the D flip-flop 104 is output from the timing reference signal output port O (see FIG. 1) of the CPU 1. Further, the 4-bit binary counter 102 is reset by the timing reference signal IREF output from the Q terminal of the D flip-flop 104. In the present embodiment, as shown in FIG. 4, the pulse width of the timing reference signal IREF is 880 nS as an example.

  The noise filter 105 removes noise from the inverted signal of the interrupt request signal ITRQ_L (see FIG. 4) input to the interrupt request signal input port I (see FIG. 1) of the CPU 1, and the interrupt request signal ITRQ_L from which the noise has been removed. The inversion signal is supplied to a shift register configured by D flip-flops 106_ # 15 to 106_ # 1 that shifts at the falling timing of the interrupt processing clock signal INTERRUPT_CLK.

  The data selector 107_ # i (i is a natural number between 1 and 15) is the (16-i) stage output of the shift register, that is, the D flip-flop 106_ # i when the timing reference signal IREF is “1 (High)”. Data output from the Q terminal is sent to the D terminal of the D flip-flop 108_ # i. When the timing reference signal IREF is “0 (Low)”, the data RQj output from the Q terminal of the D flip-flop 108_ # i To the D terminal of the D flip-flop 108_ # i. In this way, the interrupt request signal ITRQ_L, which is serial data, is converted into parallel data RQ15 to RQ1. The CPU 1 uses the parallel data RQ15 to RQ1 to determine which I / O device has received the interrupt request using hardware such as a priority encoder (not shown) in the CPU 11.

<Configuration of I / O part of I / O device>
Next, the I / O portion of the I / O device 2_ # i will be described. As described above, when making an interrupt request to the CPU 1, the I / O device 2_ # i uses the timing reference signal IREF input to the timing reference signal input port I to make one cycle of the timing reference signal IREF. The interrupt request signal output from the interrupt request signal output port O in the timing section Ti assigned in advance to the I / O device 2_ # i in the timing sections T0 to T15 (see FIGS. 2A and 2B) obtained by dividing N into A low state, that is, an active state is set. In order to realize such an operation, for example, the I / O device 2_ # i has 15 types of delay signals (FIG. 5) obtained by delaying the timing reference signal IREF by 1 to 15 times the pulse width of the timing reference signal IREF. The timing request signals TIM1 to TIM15) shown in FIG. 5 are generated, and the interrupt request signal is set to the low state in the timing section Ti by using the timing signals TIMi in the timing signals TIM1 to TIM15.

  However, normally, the I / O device 2_ # i cannot prepare a clock signal having the same phase and cycle as the interrupt processing clock signal INTERRUPT_CLK used when generating the timing reference signal IREF on the CPU 1 side. A circuit that generates the signals TIM1 to TIM15 cannot be realized by a simple circuit such as a shift register to which the timing reference signal IREF is input.

  Therefore, for example, the I / O portion of the I / O device 2_ # i has the circuit configuration shown in FIG. 6, and the I / O device 2_ # i generates timing signals TIM1A to TIM15A that approximate the timing signals TIM1 to TIM15. Like that. FIG. 7 shows an example of various signals in the I / O portion of the I / O device 2_ # i. FIG. 7 also shows ideal timing signals TIM1 and TIM2 for reference in addition to various signals of the I / O portion of the I / O device 2_ # i.

  The I / O device 2_ # i has a clock signal having a period equal to or less than 1/6 of the pulse width of the timing reference signal IREF, and this clock signal is referred to as a sampling clock signal SMP_CLK. In this embodiment, since the pulse width of the timing reference signal IREF is 880 nS, the frequency of the sampling clock signal SMP_CLK is about 6.8 MHz or more. In the present embodiment, the frequency of the sampling clock signal SMP_CLK is 10 MHz.

  The D flip-flop 201 outputs the timing reference signal IREF from the Q terminal in synchronization with the sampling clock signal SMP_CLK. The D flip-flop 202, the D flip-flop 203, and the AND gate 204 synchronize the timing reference signal IREF (see FIG. 7) that is not synchronized with the sampling clock signal SMP_CLK, and then the rising detection signal IREF_RISE (of the timing reference signal IREF). (See FIG. 7).

  The 8-bit counter 205 is synchronously reset by the rising edge detection signal IREF_RISE input to the RES terminal, and performs a counting operation in synchronization with the sampling clock signal SMP_CLK (see FIG. 7).

  The timing decoder 206 generates decode signals TMS1 to TMS15 and TMS15D based on the counter value of the 8-bit counter 205. When the decode signal TMSi (i is a natural number between 1 and 15) occurs, the INT_REQ output from the Q terminal of the D flip-flop 207 that holds the state of INT_PEN at the rising timing of the sampling clock signal SMP_CLK is “1”. (In the case of (High) ") is a signal for determining the rising edge of the timing signal TIMiA (i is a natural number of 1 to 15). The decode signal TMS15D is a timing signal when an interrupt occurs (when INT_REQ output from the Q terminal of the D flip-flop 207 that holds the state of INT_PEN at the rising timing of the sampling clock signal SMP_CLK is “1 (High)”). This is a signal for determining the falling edge of the TIM 15A.

  The delay time from the rise of the timing reference signal IREF to the rise of the timing signal TIMi (i is a natural number of 1 to 15) and the delay time from the rise of the timing reference signal IREF to the fall of the timing signal TIM15 are as shown in FIG. It is. Since it is generally not possible to assume that “there is a signal synchronized with the input signal IREF on the I / O device side”, if a signal close to the timing following the input signal IREF is created using the sampling clock signal SMP_CLK, each decode signal The rising timing range is as shown in FIG. Then, the rising timing of each decode signal is determined as shown in FIG. 8 so that the pulse width of the timing signal TIMiA is 8 or 9 clocks of the sampling clock signal SMP_CLK. The determined timing (count value of the 8-bit counter 205) is shown beside each decode signal in FIG.

  The SR flip-flop 208_i (i is a natural number between 1 and 15) is reset by the rising detection signal IREF_RISE in synchronization with the rising of the sampling clock signal SMP_CLK, and both INT_REQ and the decoding signal TMSi are “1 (High)”. If it is set, the decode signal TMS (i + 1) (where the decode signal TMS15D when i = 15) is “1 (High)” is reset, and the timing signal TIMiA is output from the Q terminal.

  In the timing selection register 209, setting values that are individually set for each I / O device are set in advance. In this embodiment, 4-bit data that is i is set as a set value for the I / O device 2_ # i (i is a natural number of 1 to 15). If the I / O device does not require an interrupt, the setting value set in the timing selection register 209 in the I / O device having the configuration of this embodiment may be set to zero.

  Based on the set value held in the timing selection register 209, the selector 210 selects and outputs the timing signal TIMiA if the set value is i. The timing signal output from the selector 210 is an open drain output and output from the interrupt request signal output port O of each I / O device.

  In the configuration example shown in FIG. 6, when an interrupt occurs (when INT_REQ output from the Q terminal of the D flip-flop 207 that holds the state of INT_PEN at the rising timing of the sampling clock signal SMP_CLK is “1 (High)”). Although the timing signal TIMiA (i is a natural number between 1 and 15) slightly deviates from the ideal timing signal TIMi (see FIG. 5), the CPU 1 detects the interrupt request signal ITRQ_L at approximately the center of each timing interval. By doing so, there is no problem caused by the deviation.

<Others>
As mentioned above, although embodiment which concerns on this invention was described, the range of this invention is not limited to this, A various change can be added and implemented in the range which does not deviate from the main point of invention.

  For example, in the circuit configuration of the I / O portion of the I / O device, an AND gate is not provided before the SR flip-flop 208_i as shown in FIG. 6, but between the SR flip-flop and the selector 210 as shown in FIG. May be provided with an AND gate, or an AND gate may be provided after the selector 210 as shown in FIG.

  Further, for example, in the circuit configuration of the I / O portion of the I / O device, an open collector output may be used instead of an open drain output as shown in FIG.

1, 11, 21 CPU
2_ # 1 to 2_ # 15 I / O device 12_ # 1 to 12_ # 15 I / O device 22_ # 1 to 22_ # 15 I / O device 3, 13, 23 Main memory 4, 24 Pull-up resistor 101 Frequency divider 102 4-bit binary counter 103 AND gate 104 D flip-flop 105 Noise filter 106_ # 1-106_ # 15 D flip-flop 107_ # 1-107_ # 15 Data selector 108_ # 1-108_ # 15 D flip-flop 201-203 D flip-flop 204 AND gate 205 8-bit counter 206 Timing decoder 207 D flip-flop 208_1-208_15 SR flip-flop 209 Timing selection register 210 Selector PC Program counter SP Stack pointer

Claims (4)

A computer system comprising a CPU and a plurality of I / O devices,
The CPU includes an interrupt request signal input port and a timing reference signal output port, and the I / O device includes a timing reference signal input port and an interrupt request signal output port, and a plurality of the interrupt request signal output ports. Is wired OR connected to the interrupt request signal input port,
The CPU generates a timing reference signal that is a pulse signal having a constant cycle and a pulse width smaller than 1/3 of the fixed cycle, and outputs the timing reference signal from the timing reference signal output port.
When making an interrupt request to the CPU, the I / O device uses the timing reference signal input to the timing reference signal input port to set one cycle of the timing reference signal to three or more. In a timing interval that is individually assigned in advance to each of the I / O devices among three or more timing intervals obtained by dividing, an interrupt request signal output from the interrupt request signal output port is made active,
The CPU determines whether or not the interrupt request signal input to the interrupt request signal input port is in an active state for each timing section. A memory for storing an interrupt service routine for each I / O device;
The CPU accesses the interrupt service routine of the I / O device that has made an interrupt request based on a determination result of whether or not the interrupt request signal is in an active state, and the I / O device that has issued the interrupt request The computer system according to claim 1, wherein an interrupt service process is executed. The pulse width of the timing reference signal is 1 / N (N is a natural number of 3 or more) of a fixed period of the timing reference signal;
The timing section is a section obtained by dividing a predetermined period of the timing reference signal by N on the basis of the rising edge of the timing reference signal.
When making an interrupt request to the CPU, the I / O device uses the timing reference signal input to the timing reference signal input port to convert the timing reference signal to a pulse width of the timing reference signal. A plurality of types of timing signals approximated to a plurality of types of delayed signals delayed by an integral multiple of the time are generated, and each of the I / O devices is associated with a timing interval individually assigned in advance from the plurality of types of timing signals. 2. The interrupt request signal output from the interrupt request signal output port is set in an active state in a timing section in which each of the I / O devices is individually assigned in advance by selecting a timing signal. Or the computer system of Claim 2.   4. The computer system according to claim 3, wherein the CPU determines whether or not the interrupt request signal is in an active state substantially at the center of the timing interval.

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