CN109446130B - Method and system for acquiring state information of I/O (input/output) equipment - Google Patents

Abstract

The application provides a method and a system for acquiring I/O equipment state information, wherein the method comprises the following steps: the FPGA accesses a state register in the I/O equipment connected with the FPGA to acquire the state information of the I/O equipment; storing the acquired state information of the I/O equipment to a state information storage space corresponding to the I/O equipment; and the CPU accesses a state information storage space in the field programmable gate array FPGA according to a preset rule so as to acquire the state information of the I/O equipment stored in the state information storage space.

Description

Method and system for acquiring state information of I/O (input/output) equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and a system for acquiring status information of an I/O device.

Background

To implement different specific functions such as display, communication, and data acquisition, a CPU generally needs to connect a plurality of I/O (Input/Output) devices. During the system operation, the CPU needs to obtain the status information of the I/O device. Generally, an I/O device has a status register therein, and whenever the operating status of the I/O device changes, the I/O device modifies the status information stored in the corresponding status register.

Currently, a polling method is usually adopted by a CPU to obtain status information of an I/O device, that is, the CPU accesses a status register inside the I/O device at intervals to obtain the status information of the I/O device.

Because the CPU is usually connected to a plurality of I/O devices, the CPU needs to sequentially acquire the status information of each I/O device in a polling manner, and acquiring the status information of the I/O devices needs to occupy a large amount of CPU resources, which increases the CPU load.

Disclosure of Invention

In view of the above, the present application provides a method and a system for acquiring status information of an I/O device.

Specifically, the method is realized through the following technical scheme:

the method for acquiring the state information of the I/O equipment is characterized by being applied to an acquisition system of the state information of the I/O equipment, wherein the system comprises a CPU, a field programmable gate array FPGA and at least one I/O equipment, the CPU is connected with the field programmable gate array FPGA through a PCIe bus, the field programmable gate array FPGA is connected with the I/O equipment, and an independent state information storage space is pre-allocated to each I/O equipment in the field programmable gate array FPGA, and the method comprises the following steps:

the FPGA accesses a state register in the I/O equipment connected with the FPGA to acquire the state information of the I/O equipment;

storing the acquired state information of the I/O equipment to a state information storage space corresponding to the I/O equipment;

and the CPU accesses a state information storage space in the field programmable gate array FPGA according to a preset rule so as to acquire the state information of the I/O equipment stored in the state information storage space.

A system for acquiring status information of an I/O device, the system comprising: the system comprises a CPU, a field programmable gate array FPGA and at least one I/O device, wherein the CPU is connected with the field programmable gate array FPGA through a PCIe bus, the field programmable gate array FPGA is connected with the I/O device, and an independent state information storage space is pre-allocated to each I/O device in the field programmable gate array FPGA;

the FPGA accesses a state register in the I/O equipment connected with the FPGA to acquire the state information of the I/O equipment;

storing the acquired state information of the I/O equipment to a state information storage space corresponding to the I/O equipment;

and the CPU accesses a state information storage space in the field programmable gate array FPGA according to a preset rule so as to acquire the state information of the I/O equipment stored in the state information storage space.

The method comprises the steps that a state register in the I/O device connected with the FPGA is accessed through the FPGA to obtain state information of the I/O device, the obtained state information of the I/O device is stored in a state information storage space corresponding to the I/O device, and a CPU can access the state information storage space in the FPGA according to a preset rule to obtain the state information of the I/O device stored in the state information storage space.

Drawings

FIG. 1 is a schematic diagram of an application scenario illustrated in an exemplary embodiment of the present application;

FIG. 2 is an interaction flow diagram illustrating a method for obtaining I/O device status information according to an exemplary embodiment of the present application;

fig. 3 is a schematic diagram of a hardware structure of an I/O device status information acquiring system according to an exemplary embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

First, a method for acquiring status information of an I/O device provided in an embodiment of the present application is described, where the method may include the following steps:

the FPGA accesses a state register in the I/O equipment connected with the FPGA to acquire the state information of the I/O equipment;

storing the acquired state information of the I/O equipment to a state information storage space corresponding to the I/O equipment;

and the CPU accesses a state information storage space in the field programmable gate array FPGA according to a preset rule so as to acquire the state information of the I/O equipment stored in the state information storage space.

As shown in an application scenario diagram of fig. 1, a CPU is connected to a field programmable gate array FPGA through a PCIe bus, the field programmable gate array FPGA is connected to a plurality of I/O devices, and an independent state information storage space is allocated to each I/O device in the field programmable gate array FPGA in advance, where the state information storage space is a storage space corresponding to a base Address register of the field programmable gate array FPGA, referred to as a bar (base Address registers) space for short, and a capacity of each state information storage space may be determined according to an actual demand. The CPU is connected with the field programmable gate array FPGA through a PCIe bus, the state information of the I/O device is indirectly acquired through the field programmable gate array FPGA, the state information of the I/O device is acquired without occupying a large amount of CPU resources, and the CPU load can be effectively reduced.

As shown in fig. 2, an interaction flowchart of a method for acquiring status information of an I/O device provided in an embodiment of the present application is specifically shown, where the method specifically includes the following steps:

s201, a field programmable gate array FPGA accesses a state register in an I/O device connected with the FPGA to acquire state information of the I/O device;

referring to fig. 3, a hardware structure diagram of a system for acquiring status information of an I/O device according to an exemplary embodiment of the present application is shown, in the present application, according to a priority of each I/O device, a corresponding access module is implemented by programming, for example, an I/O device with a low priority is accessed in a polling manner, for an I/O device with a higher priority, an interrupt or interrupt is accessed in a manner of being matched with polling, and an instruction processing module is implemented by programming, processes an information reading instruction of a CPU and an interrupt signal of the access module, and is responsible for reading status information of the I/O device stored in a status storage space.

It should be noted that, between the access module and the I/O device, one-to-one access may be performed, that is, each access module corresponds to one I/O device, or one-to-many access may be performed, that is, each access module corresponds to at least one I/O device.

The FPGA accesses a state register in the I/O device connected with the FPGA to acquire the state information of the I/O device, and the specific implementation can be as follows: and a pre-configured access module in the FPGA accesses a state register in the I/O equipment connected with the FPGA according to a preset access rule so as to acquire the state information of the I/O equipment. For example, the access module 1 corresponds to the I/O device 1, the access module 2 corresponds to the I/O device 2, the access module 3 corresponds to the I/O device 3, each access module pre-configured in the field programmable gate array FPGA may access a state register in the respective corresponding I/O device to obtain state information of each I/O device, and for example, the access module 1 corresponds to the I/O device 1, the I/O device 2, and the I/O device 3, and the access module 1 pre-configured in the field programmable gate array FPGA may access a state register in the respective corresponding I/O device to obtain state information of each I/O device.

In addition, an access module which is configured in advance in the field programmable gate array FPGA accesses a state register in each I/O device which is connected with the access module to acquire the state information of the I/O device, and the state information of the I/O device can be acquired in a polling mode, an interruption mode and a polling mode.

1) The access module accesses a status register in each I/O device connected with the access module in a polling mode to acquire status information of the I/O devices: the access module accesses a status register in the I/O device connected with the access module by a task polling or time polling mode to acquire the status information of the I/O device and stores the acquired status information of the I/O device into a status information storage space corresponding to the I/O device.

2) The access module accesses a status register in each I/O device connected with the access module in an interrupt mode to acquire status information of the I/O device: the I/O device sends an interrupt signal to the access module, the format of the interrupt signal needs to refer to a communication protocol between the FPGA and the I/O device, the access module accesses a state register corresponding to the I/O device after receiving the interrupt signal so as to acquire the state information of the I/O device, and the acquired state information of the I/O device is stored in a state information storage space corresponding to the I/O device.

3) The access module accesses a status register in each I/O device connected with the access module by means of matching of interrupt and polling so as to acquire status information of the I/O devices: the method comprises the steps that an I/O device sends an interrupt signal to an access module, the problem that the I/O device continuously sends the interrupt signal and the like occurs due to the fact that the I/O device is abnormal in state or improper in use and the like, the access module is switched to a polling mode after learning that the interrupt signal is abnormal in sending, the access module accesses a state register in the I/O device connected with the access module through a task polling mode or a time polling mode to obtain state information of the I/O device, the obtained state information of the I/O device is stored in a state information storage space corresponding to the I/O device, and the access module is switched back to an interrupt mode after learning that the interrupt signal is normal in sending.

S202, storing the acquired state information of the I/O equipment to a state information storage space corresponding to the I/O equipment;

each I/O device has a state information storage space corresponding thereto in the field programmable gate array FPGA, for example, I/O device 1, I/O device 2, I/O device 3, and has a state information storage space 1, a state information storage space 2, a state information storage space 3 corresponding thereto in the field programmable gate array FPGA.

The acquired state information of the I/O device is stored in a state information storage space corresponding to the I/O device, for example, the acquired state information corresponding to the I/O device 1 is stored in a state information storage space 1 corresponding to the I/O device 1.

S203, the CPU accesses a state information storage space in the FPGA according to a preset rule to acquire the state information of the I/O device stored in the state information storage space.

The CPU accesses a state information storage space in the FPGA according to a preset rule to acquire the state information of the I/O equipment stored in the state information storage space, and the state information can be realized in two modes of polling or interruption:

1) the CPU acquires the state information of the I/O equipment stored in the state information storage space in a polling mode: the CPU sends an information reading instruction to the field programmable gate array FPGA through a PCIe bus according to a preset period; after receiving the information reading instruction, the field programmable gate array FPGA analyzes the information reading instruction to obtain a state storage space address carried in the information reading instruction, where the state storage space address may be an address of a state storage space corresponding to a certain I/O device, an address of a state storage space corresponding to some I/O devices, or an address of a state storage space corresponding to all I/O devices; reading the state information of the I/O equipment from the state storage space corresponding to the state storage space address, packaging the read state information of the I/O equipment and returning the packaged state information to the CPU; and the CPU receives the state information of the I/O equipment returned by the field programmable gate array FPGA to acquire the state information of the I/O equipment stored in the state information storage space.

2) The CPU obtains the state information of the I/O equipment stored in the state information storage space in an interrupt mode: the method comprises the steps that a Field Programmable Gate Array (FPGA) sends a PCIe interrupt signal to a Central Processing Unit (CPU), wherein the PCIe interrupt signal carries an identification of an input/output (I/O) device; the CPU receives the PCIe interrupt signal and extracts the identification of the I/O equipment carried in the PCIe interrupt signal; sending an information reading instruction to a Field Programmable Gate Array (FPGA) according to the identification of the I/O equipment; after receiving the information reading instruction, the FPGA analyzes the information reading instruction to obtain a state storage space address carried in the information reading instruction, wherein the state storage space address is a state storage space address corresponding to a state information storage space pre-allocated for the I/O device; reading the state information of the I/O equipment from the state storage space corresponding to the state storage space address, packaging the read state information of the I/O equipment and returning the packaged state information to the CPU; and the CPU receives the state information of the I/O equipment returned by the field programmable gate array FPGA to acquire the state information of the I/O equipment stored in the state information storage space.

The access module sends an Interrupt Signal to the instruction processing module, the Interrupt Signal adds an identifier of the I/O device, generally a serial number of the I/O device, to the Interrupt Signal sent by the I/O device to the access module, and the instruction processing module converts the Interrupt Signal into a PCIe Interrupt Signal and sends the PCIe Interrupt Signal to the CPU in a form of MSI (Message Signal Interrupt) Interrupt or the like. Furthermore, if the instruction processing module receives a plurality of Interrupt signals sent by the access module, the Interrupt signals need to be arbitrated, then the Interrupt signals are converted into PCIe Interrupt signals, and the PCIe Interrupt signals are sent to the CPU by means of MSI (Message Signal Interrupt) Interrupt or the like.

According to the method, the state register in the I/O device connected with the FPGA is accessed through the FPGA to obtain the state information of the I/O device, the obtained state information of the I/O device is stored in the state information storage space corresponding to the I/O device, and the CPU can access the state information storage space in the FPGA according to the preset rule to obtain the state information of the I/O device stored in the state information storage space.

Corresponding to the above method embodiment, the present application further provides a system for acquiring I/O device status information, where the system includes: the system comprises a CPU, a field programmable gate array FPGA and at least one I/O device, wherein the CPU is connected with the field programmable gate array FPGA through a PCIe bus, the field programmable gate array FPGA is connected with the I/O device, and an independent state information storage space is pre-allocated to each I/O device in the field programmable gate array FPGA;

the FPGA accesses a state register in the I/O equipment connected with the FPGA to acquire the state information of the I/O equipment;

storing the acquired state information of the I/O equipment to a state information storage space corresponding to the I/O equipment;

and the CPU accesses a state information storage space in the field programmable gate array FPGA according to a preset rule so as to acquire the state information of the I/O equipment stored in the state information storage space.

The system implementation process is detailed in the implementation process of the corresponding steps in the method, and is not described herein again.

For the system embodiment, since it basically corresponds to the method embodiment, reference may be made to the partial description of the method embodiment for relevant points. The above-described system embodiments are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.

The invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

The foregoing is directed to embodiments of the present invention, and it is understood that various modifications and improvements can be made by those skilled in the art without departing from the spirit of the invention.

Claims (4)

1. The method for acquiring the state information of the I/O equipment is characterized by being applied to an acquisition system of the state information of the I/O equipment, wherein the system comprises a CPU, a field programmable gate array FPGA and at least one I/O equipment, the CPU is connected with the field programmable gate array FPGA through a PCIe bus, the field programmable gate array FPGA is connected with the I/O equipment, and an independent state information storage space is pre-allocated to each I/O equipment in the field programmable gate array FPGA, and the method comprises the following steps:

the FPGA accesses a state register in the I/O equipment connected with the FPGA to acquire the state information of the I/O equipment;

storing the acquired state information of the I/O equipment to a state information storage space corresponding to the I/O equipment;

the CPU accesses a state information storage space in the FPGA according to a preset rule to acquire the state information of the I/O equipment stored in the state information storage space;

the method for accessing the state register in the I/O device connected with the FPGA by the FPGA to acquire the state information of the I/O device comprises the following steps:

accessing the I/O equipment with the priority not higher than the preset value in a polling mode, and accessing the I/O equipment with the priority higher than the preset value in an interruption or interruption and polling matched mode;

the method for accessing the state information storage space in the field programmable gate array FPGA by the CPU according to the preset rule to acquire the state information of the I/O device stored in the state information storage space comprises the following steps:

the CPU sends an information reading instruction to the field programmable gate array FPGA through a PCIe bus according to a preset rule;

after receiving the information reading instruction, the FPGA analyzes the information reading instruction to obtain a state storage space address carried in the information reading instruction, wherein the state storage space address is a state storage space address corresponding to a state information storage space pre-allocated for the I/O device;

reading the state information of the I/O equipment from the state storage space corresponding to the state storage space address, packaging the read state information of the I/O equipment and returning the packaged state information to the CPU;

the CPU receives the state information of the I/O equipment returned by the FPGA to acquire the state information of the I/O equipment stored in the state information storage space;

the CPU sends an information reading instruction to the FPGA through the PCIe bus according to a preset rule, and the information reading instruction comprises the following steps:

the CPU sends an information reading instruction to the field programmable gate array FPGA through a PCIe bus according to a preset period;

or the like, or, alternatively,

the method comprises the steps that a Field Programmable Gate Array (FPGA) sends a PCIe interrupt signal to a Central Processing Unit (CPU), wherein the PCIe interrupt signal carries an identification of an input/output (I/O) device; the CPU receives the PCIe interrupt signal and extracts the identification of the I/O equipment carried in the PCIe interrupt signal; and sending an information reading instruction to the field programmable gate array FPGA according to the identification of the I/O equipment.

2. The method of claim 1,

the state information storage space is a storage space corresponding to a field programmable gate array FPGA base address register.

3. A system for acquiring status information of an I/O device, the system comprising: the system comprises a CPU, a field programmable gate array FPGA and at least one I/O device, wherein the CPU is connected with the field programmable gate array FPGA through a PCIe bus, the field programmable gate array FPGA is connected with the I/O device, and an independent state information storage space is pre-allocated to each I/O device in the field programmable gate array FPGA;

the FPGA accesses a state register in the I/O equipment connected with the FPGA to acquire the state information of the I/O equipment;

storing the acquired state information of the I/O equipment to a state information storage space corresponding to the I/O equipment;

the CPU accesses a state information storage space in the FPGA according to a preset rule to acquire the state information of the I/O equipment stored in the state information storage space;

the method for accessing the state register in the I/O device connected with the FPGA by the FPGA to acquire the state information of the I/O device comprises the following steps:

accessing the I/O equipment with the priority not higher than the preset value in a polling mode, and accessing the I/O equipment with the priority higher than the preset value in an interruption or interruption and polling matched mode;

the CPU obtains the state information of the I/O device stored in the state information storage space by the following method:

the CPU sends an information reading instruction to the field programmable gate array FPGA through a PCIe bus according to a preset rule;

after receiving the information reading instruction, the FPGA analyzes the information reading instruction to obtain a state storage space address carried in the information reading instruction, wherein the state storage space address is a state storage space address corresponding to a state information storage space pre-allocated for the I/O device;

reading the state information of the I/O equipment from the state storage space corresponding to the state storage space address, packaging the read state information of the I/O equipment and returning the packaged state information to the CPU;

the CPU receives the state information of the I/O equipment returned by the FPGA to acquire the state information of the I/O equipment stored in the state information storage space;

the CPU sends an information reading instruction to the FPGA through the PCIe bus according to a preset rule, and the information reading instruction comprises the following steps:

the CPU sends an information reading instruction to the field programmable gate array FPGA through a PCIe bus according to a preset period;

or the like, or, alternatively,

the method comprises the steps that a Field Programmable Gate Array (FPGA) sends a PCIe interrupt signal to a Central Processing Unit (CPU), wherein the PCIe interrupt signal carries an identification of an input/output (I/O) device; the CPU receives the PCIe interrupt signal and extracts the identification of the I/O equipment carried in the PCIe interrupt signal; and sending an information reading instruction to the field programmable gate array FPGA according to the identification of the I/O equipment.

4. The system of claim 3,

the state information storage space is a storage space corresponding to a field programmable gate array FPGA base address register.

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