CN107590092A - A kind of PCIE based on FPGA turns EMC bridges - Google Patents
A kind of PCIE based on FPGA turns EMC bridges Download PDFInfo
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Abstract
The present invention provides a kind of PCIE based on FPGA and turns EMC bridges, belongs to digital integrated electronic circuit field, technical solution of the present invention is：Its structure includes PCIE interfaces, PCIE turns EMC logics, EMC interfaces, EMC control modules, and wherein PCIE interfaces, EMC interfaces and PCIE turn EMC logical gates using VHDL language progress behavioral scaling description, and compiling is downloaded to FPGA after forming net meter file synthesis mapping；The PCIE interfaces are connected with computer PCI E equipment, and EMC interfaces are connected with EMC control modules.The program realizes standard PCIE interfaces and configurable bit wide（8th, 16 and 32）The signal conversion of EMC interfaces；The design have the characteristics that it is simple in construction, feasible, practical and convenient, have preferably promote practical value.
Description
Technical field
The present invention relates to digital integrated electronic circuit field, more particularly to a kind of PCIE based on FPGA to turn EMC bridges.
Background technology
Current PC IE buses can provide more stable faster data interaction, be widely used in high speed circuit；Outside
The features such as portion storage expanding module EMC is practical and convenient efficient can provide bigger memory space for IC design, except branch
Hold synchronous memory module and also support the asynchronous NOR FLASH of carry and Asynchronous SRAM；FPGA is with its low-power consumption, low cost, programmable
With the construction cycle short gesture for waiting number of features to be widely applied to every field, and having gradually replacement asic chip.
The content of the invention
In order to solve the above technical problems, the present invention proposes a kind of PCIE based on FPGA and turns EMC bridges, utilize FPGA's
Configurability, the signal for completing universal standard PCIE interfaces to customized EMC interfaces are changed.
The technical scheme is that：
A kind of PCIE based on FPGA turns EMC bridges,
Its structure mainly includes PCIE interfaces, PCIE turns EMC logics, EMC interfaces, EMC control modules, wherein PCIE interfaces, EMC
Interface and PCIE turn EMC logical gates and carry out behavioral scaling description using VHDL language, after compiling forms net meter file synthesis mapping
It is downloaded to FPGA；The PCIE interfaces are connected with computer PCI E equipment, and EMC interfaces are connected with EMC control modules.
PCIE interfaces are standard PCIE interfaces；EMC interfaces are with EMC controllers by enabling control signal OEN, writing enabled control
Signal WEN processed, the enabled control signal CEN of piece choosing, address bus signal ADDR [22:0], data bus signal DATA [31:0] and
Bit width mode selection signal BITSET [1:0] transmission to control and data signal.Standard PCIE interfaces turn EMC interfaces, can prop up
Hold the data bandwidth conversion of 8,16 and 32.
The PCIE turn EMC logical gates may be selected support data buffer zone, if EMC control modules without carry outside
FLASH memory, then the logic need appropriately sized buffering area is opened up inside FPGA, if EMC control modules have outside carry
Portion's FLASH memory, then the logic can be without data buffer zone.
Wherein, FLASH memory situation is as follows outside EMC controllers carry：
1）Standard PCIE interfaces and EMC interface sections are realized by its standard using VHDL descriptions；
2）Data bit width through PCIE interfaces supply conversion logic is 32, and a width of 11 of address bit, therefore, conversion logic will solve
The certainly change of address date bit wide, it is as follows that PCIE interfaces turn EMC interface logics design implementation process：
2.1）According to BITSET [1:0] signal confirms that EMC interfaces support the bit wide of data；
2.2）Deposit DATA [31:0] and ADDR [10:0] read-write operation is issued in register group, judgement.
2.3）If write operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0]
Offset operation is done, according to（1）As a result by DATA [31:0] each field assignment.
2.4）If read operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0]
Offset operation and assignment are carried out, waits feedback data.
2.5）By control signal set under idle condition, the read-write indication signal from PCIE interfaces is detected.
Wherein 2.3）With 2.4）The conversion of address date bit wide is carried out, data 32 turn 8 and 16 need to be by corresponding address
By lt 2 and 1, and make 4 times and 2 times skews, 32 turn that assignment can be done at 32 under the premise of sequential is met, a high position is mended
0。
EMC controllers are as follows without FLASH memory situation outside carry：
1）Standard PCIE interfaces and EMC interface sections are realized by its standard using VHDL descriptions；
2）Data bit width through PCIE interfaces supply conversion logic is 32, and a width of 11 of address bit, therefore, conversion logic will solve
The certainly change of address date bit wide, it is as follows that PCIE interfaces turn EMC interface logics design implementation process：
2.1）According to BITSET [1:0] signal confirms that EMC interfaces support the bit wide of data；
2.2）Deposit DATA [31:0] and ADDR [10:0] read-write operation is issued in register group, judgement；
2.3）If write operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0] do partially
Operation is moved, according to（1）As a result by DATA [31:0] each field assignment.And the data after assignment are write into buffering area, EMC controllers
Selection continues scanning buffer data, data renewal to be had, and data read-out is now completed writing for data by EMC controllers
Operation.
2.4）If read operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0]
Carry out offset operation and assignment, EMC controllers write data into after buffering area and start interrupt signal inform main frame by data from
Buffering area is read to internal memory, completes a read operation.
2.5）By control signal set under idle condition, the read-write indication signal from PCIE interfaces is detected.
Wherein 2.3）With 2.4）The conversion of address date bit wide is carried out, data 32 turn 8 and 16 need to be by corresponding address
By lt 2 and 1, and make 4 times and 2 times skews, 32 turn that assignment can be done at 32 under the premise of sequential is met, a high position is mended
0。
The beneficial effects of the invention are as follows
FPGA (Field Programmable Gate Array) is field programmable gate array, is a kind of user according to respective
Need and the voluntarily digital integrated electronic circuit of constitutive logic function, it has the characteristics that integrated level is high, cost is low, stability is good.Adopt
With standard PCIE interfaces, the operation of asynchronous Nor flash storages can be supported；Support optional 8,16 and 32 data bandwidth
Conversion, make carry storage alternative bigger.
Brief description of the drawings
Fig. 1 is the structural representation of the present invention；
Fig. 2 is that PCIE interfaces turn EMC interface logic flow charts.
Embodiment
More detailed elaboration is carried out to present disclosure below：
As shown in Figure 1, the present invention includes PCIE interfaces, PCIE turns EMC logics, EMC interfaces, EMC control modules, PCIE interfaces
It is connected with computer PCI E equipment, EMC interfaces are connected with EMC control modules.PCIE interfaces, EMC interfaces and PCIE turn EMC logics
Part carries out behavioral scaling description using VHDL language.Fpga chip uses the model XC6SLX45T-3CSG324 of XILINX companies
Chip.Flash uses the model IC_TSOP48_XCF32PVOG48C chips of XILINX companies.
On the one hand, PCIE interfaces turn EMC interfaces and address date bit wide inconsistence problems be present, on the other hand, PCIE interfaces
It will meet strict timing Design requirement with EMC Interface designs, so, the conversion logic will meet timing Design requirement
Under the premise of carry out the conversion of address date bit wide, the present invention meets that FPGA is mapped to after design requirement to be realized by VHDL descriptions.
If accompanying drawing 2 is that PCIE interfaces turn EMC interface logic flow charts.FLASH memory situation is shown in embodiment party outside EMC controllers carry
Case 1, EMC controllers are shown in embodiment 2 without FLASH memory situation outside carry.
Embodiment 1：
1）Standard PCIE interfaces and EMC interface sections are realized by its standard using VHDL descriptions；
2）Data bit width through PCIE interfaces supply conversion logic is 32, and a width of 11 of address bit, therefore, conversion logic will solve
The certainly change of address date bit wide, it is as follows that PCIE interfaces turn EMC interface logics design implementation process：
2.1）According to BITSET [1:0] signal confirms that EMC interfaces support the bit wide of data；
2.2）Deposit DATA [31:0] and ADDR [10:0] read-write operation is issued in register group, judgement.
2.3）If write operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0]
Offset operation is done, according to（1）As a result by DATA [31:0] each field assignment.
2.4）If read operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0]
Offset operation and assignment are carried out, waits feedback data.
2.5）By control signal set under idle condition, the read-write indication signal from PCIE interfaces is detected.
Wherein 2.3）With 2.4）The conversion of address date bit wide is carried out, data 32 turn 8 and 16 need to be by corresponding address
By lt 2 and 1, and make 4 times and 2 times skews, 32 turn that assignment can be done at 32 under the premise of sequential is met, a high position is mended
0。
Embodiment 2：
1）Standard PCIE interfaces and EMC interface sections are realized by its standard using VHDL descriptions；
2）Data bit width through PCIE interfaces supply conversion logic is 32, and a width of 11 of address bit, therefore, conversion logic will solve
The certainly change of address date bit wide, it is as follows that PCIE interfaces turn EMC interface logics design implementation process：
2.1）According to BITSET [1:0] signal confirms that EMC interfaces support the bit wide of data；
2.2）Deposit DATA [31:0] and ADDR [10:0] read-write operation is issued in register group, judgement；
2.3）If write operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0] do partially
Operation is moved, according to（1）As a result by DATA [31:0] each field assignment.And the data after assignment are write into buffering area, EMC controllers
Selection continues scanning buffer data, data renewal to be had, and data read-out is now completed writing for data by EMC controllers
Operation.
2.4）If read operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0]
Carry out offset operation and assignment, EMC controllers write data into after buffering area and start interrupt signal inform main frame by data from
Buffering area is read to internal memory, completes a read operation.
2.5）By control signal set under idle condition, the read-write indication signal from PCIE interfaces is detected.
Wherein 2.3）With 2.4）The conversion of address date bit wide is carried out, data 32 turn 8 and 16 need to be by corresponding address
By lt 2 and 1, and make 4 times and 2 times skews, 32 turn that assignment can be done at 32 under the premise of sequential is met, a high position is mended
0。
It is the known technology of those skilled in the art in addition to the technical characteristic described in specification.
Claims (5)
1. a kind of PCIE based on FPGA turns EMC bridges, it is characterised in that structure includes PCIE interfaces, PCIE turns EMC logics, EMC
Interface, EMC control modules, wherein PCIE interfaces, EMC interfaces and PCIE turn EMC logical gates and carry out behavior using VHDL language
Level description, compiling are downloaded to FPGA after forming net meter file synthesis mapping；The PCIE interfaces are connected with computer PCI E equipment,
EMC interfaces are connected with EMC control modules.
2. PCIE according to claim 1 turns EMC bridges, it is characterised in that
Asynchronous controlling and data transfer are carried out by signals below between the EMC interfaces and EMC modules：Enabled control signal
OEN, write enabled control signal WEN, the enabled control signal CEN of piece choosing, address bus signal ADDR [22:0], data bus signal
DATA[31:0] and bit width mode selection signal BITSET [1:0].
3. PCIE according to claim 1 or 2 turns EMC bridges, it is characterised in that
The PCIE turns EMC logical gates and may be selected to support data buffer zone, if EMC control modules are deposited without FLASH outside carry
Reservoir, then the logic needs to open up appropriately sized buffering area inside FPGA, if EMC control modules have FLASH outside carry
Memory, then the logic can be without data buffer zone.
4. PCIE according to claim 3 turns EMC bridges, it is characterised in that
FLASH memory situation is as follows outside EMC controllers carry：
1）Standard PCIE interfaces and EMC interface sections are realized by its standard using VHDL descriptions；
2）Data bit width through PCIE interfaces supply conversion logic is 32, and a width of 11 of address bit, therefore, conversion logic will solve
The certainly change of address date bit wide, it is as follows that PCIE interfaces turn EMC interface logics design implementation process：
2.1）According to BITSET [1:0] signal confirms that EMC interfaces support the bit wide of data；
2.2）Deposit DATA [31:0] and ADDR [10:0] read-write operation is issued in register group, judgement；
2.3）If write operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0] do partially
Operation is moved, according to（1）As a result by DATA [31:0] each field assignment；
2.4）If read operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0] carry out
Offset operation and assignment, wait feedback data；
2.5）By control signal set under idle condition, the read-write indication signal from PCIE interfaces is detected；
Wherein 2.3）With 2.4）The conversion of address date bit wide is carried out, data 32 turn 8 and 16 need to be by corresponding address step-by-step
2 and 1 are moved to left, and make 4 times and 2 times skews, 32 turn that assignment can be done at 32 under the premise of sequential is met, a high position mends 0.
5. PCIE according to claim 3 turns EMC bridges, it is characterised in that
EMC controllers are as follows without FLASH memory situation outside carry：
1）Standard PCIE interfaces and EMC interface sections are realized by its standard using VHDL descriptions；
2）Data bit width through PCIE interfaces supply conversion logic is 32, and a width of 11 of address bit, therefore, conversion logic will solve
The certainly change of address date bit wide, it is as follows that PCIE interfaces turn EMC interface logics design implementation process：
2.1）According to BITSET [1:0] signal confirms that EMC interfaces support the bit wide of data；
2.2）Deposit DATA [31:0] and ADDR [10:0] read-write operation is issued in register group, judgement；
2.3）If write operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0] do partially
Operation is moved, according to（1）As a result by DATA [31:0] each field assignment；And the data after assignment are write into buffering area, EMC controllers
Selection continues scanning buffer data, data renewal to be had, and data read-out is now completed writing for data by EMC controllers
Operation；
2.4）If read operation, operating control signal is required according to EMC interface sequences, according to (1) result by ADDR [10:0] carry out
Offset operation and assignment, EMC controllers, which write data into after buffering area and start interrupt signal, informs main frame by data from buffering
Area is read to internal memory, completes a read operation；
2.5）By control signal set under idle condition, the read-write indication signal from PCIE interfaces is detected；
Wherein 2.3）With 2.4）The conversion of address date bit wide is carried out, data 32 turn 8 and 16 need to be by corresponding address step-by-step
2 and 1 are moved to left, and make 4 times and 2 times skews, 32 turn that assignment can be done at 32 under the premise of sequential is met, a high position mends 0.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117827725A (en) * | 2024-03-04 | 2024-04-05 | 山东华翼微电子技术股份有限公司 | EMC interface expansion module, system and method based on FPGA |
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Application publication date: 20180116 |