CN100375074C - AMBA** peripheral interface circuit of embedded type CPu in 8 bits - Google Patents
AMBA** peripheral interface circuit of embedded type CPu in 8 bits Download PDFInfo
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- CN100375074C CN100375074C CNB200510110254XA CN200510110254A CN100375074C CN 100375074 C CN100375074 C CN 100375074C CN B200510110254X A CNB200510110254X A CN B200510110254XA CN 200510110254 A CN200510110254 A CN 200510110254A CN 100375074 C CN100375074 C CN 100375074C
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Abstract
The present invention relates to an AMBA<TM> peripheral interface circuit aiming at an embedded type 8-bit CPU, which belongs to the technical field of integrated circuit techniques. The AMBA<TM> peripheral interface circuit aiming at an embedded type 8-bit CPU is formed by that a bus state machine, a clock control module, a data control module and an address control module are connected by circuits. The data control module, the address control module and the clock control module are cooperated with each other under control of the bus state machine so as to solve the contradictions on the aspects of a 32-bit bus and an 8-bit CPU, such as time sequence, data width, etc. An 8-bit CPU with the AMBA<TM> peripheral interface circuit aiming at an embedded type 8-bit CPU can work like a 32-bit CPU; the AMBA<TM> peripheral interface circuit aiming at an embedded type 8-bit CPU can be directly embedded into the SoC system without the corresponding modification of other modules by adopting the original instruction system; in this way, the design time can be shortened, and the IP multiplexing efficiency can be raised; the 8-bit CPU with the AMBA<TM> peripheral interface circuit aiming at an embedded type 8-bit CPU has a processing speed which is equivalent to that of a similar 8-bit embedded type CPU, but has smaller area and lower cost than a 32-bit microprocessor, and has a favorable application prospect.
Description
Technical field
The invention belongs to the integrated circuit (IC) design field, be specifically related to a kind of AMBA that is applicable to 8 embedded type CPUs
TMPeripheral interface circuit.
Background technology
Along with the widespread use of integrated circuit technique, people are more and more harsher for the requirement of Time To Market (Time-to-Market).In order to shorten design and proving period, the IP reuse technology is widely adopted, and especially in SoC (System-on-Chip SOC (system on a chip)) design, people adopt unified bus specification, embedded type CPU and each existing IP kernel are integrated on the chip piece, thus the function of realization total system.
In the SoC design, the bus specification AMBA of the SOC (system on a chip) that ARM company puts forward
TM(AdvancedMicrocontroller Bus Architecture) become the de facto standard of industry.This standard has mainly been stipulated three kinds of bus standards:
(1)AHB(Advanced?High-performance?Bus)
(2)ASB(Advanced?System?Bus)
(3)APB(Advanced?Peripheral?Bus)
In actual applications, generally adopt AHB+APB standard or ASB+APB standard.The function of AHB and APB is similar substantially, but AHB supports more function, and bigger bit wide can be provided, and owing to all operations in the AHB standard all carries out at rising edge clock, help the technology manufacturing, so general recommendation uses AHB as system bus in new design.
In SoC design, relatively Chang Yong CPU has 8 8051 and 32 MIPS, ARM7, ARM9 etc.Adopting 32 CPU is the main flow of current design, but cost is difficult to obtain utilization widely than higher.In fact, in numerous application scenarios, such as smart card, E-commerce transaction platform or the like, except requiring basic functions, people are the cost of attention location system more.So, adopt relatively inexpensive 8051 to be good selections.But existing coprocessor and bus be generally towards 32 bit CPUs, and how 8 CPU being embedded on 32 the system bus becomes a difficult problem.
Summary of the invention
The objective of the invention is to propose a kind of AMBA at 8 embedded type CPUs
TMPeripheral interface circuit can be worked 8 bit CPUs as 32 bit CPUs, can be directly embedded in the SoC system.
The AMBA that is applicable to 8 embedded type CPUs that the present invention proposes
TMPeripheral interface circuit comprises a bus state machine 11, by 12, one data control modules 13 of a clock control module and an address control module 14.Its structure is seen shown in Figure 1.Wherein, the Data Control module comprises read data controlling sub 131 and write data controlling sub 132; Clock control module 12, address control module 14, Data Control module 13 all are subjected to bus state machine controls, and are connected with CPU, and clock control module 12, Data Control module 13 are connected with address control module 14; Under the control of bus state machine, clock control module, Data Control module and address control module collaborative work are to solve 32 buses and the 8 bit CPUs contradiction at aspects such as sequential and data widths.
Among the present invention, described clock control module comprises d type flip flop 21 and Sheffer stroke gate 22 that a rising edge triggers, and d type flip flop 21 is connected with bus state machine 11 by signal wire 24, and Sheffer stroke gate 22 is connected with bus state machine 11 with trigger 21 respectively; Clock control module 12 keeps the normal instruction cycle according to the indication of bus state machine by the switch cpu clock.See shown in Figure 2.
Among the present invention, described Data Control module comprises read data and two submodules of write data, read data controlling sub 131 is by a data format converting module 31, data buffer zone 32 and MUX 33 circuit successively connect to form, MUX 33 is connected with CPU, and is subjected to bus state machine 11 controls; Read data controlling sub 131 after Data Format Transform module 31, is divided into the data from bus 4 bytes and deposits data buffer 32 in, under the control of bus state machine, is read by CPU in batches; Write data controlling sub 132 is by a moderator 41, data buffer zone 42 and output register 43 circuit successively connect to form, moderator 41 is connected with CPU, and moderator 41 and output register 43 all are subjected to bus state machine 11 controls, the data that write data controlling sub 132 is write CPU outward by moderator 41 indications, are placed on the ad-hoc location of data buffer area, after being combined into width and being 32 data, write again in the output register 43.See Fig. 3 and shown in Figure 4.
Among the present invention, described address control module 14 is by a series of latch 53, address extension module 52 and MUX 51 circuit successively connect to form, MUX 51, latch 53 are subjected to bus state machine 11 controls, the address control module is extended to 16 bit address 32 bit address of bus request, and provide the control signal that meets AHB MASTER interface standard, promptly under the control of bus state machine 11, output to selectively on the ahb bus, export the various address signals of ahb bus requirement simultaneously.See shown in Figure 5.
The present invention marks off each duty 23 of bus on the basis of analyzing the AHB agreement, comprise TNIT, REQ, ADDR, STOP, TATA etc.Design a bus state machine 11 according to the condition of its conversion.Utilize this state machine to coordinate work between clock control module, Data Control module and the address control module, and keep AMBA
TMThe sequential of peripheral interface circuit.Describe AMBA below in detail
TMThe peripheral interface circuit working method.
In view of AMBA
TMBus and the inconsistent contradiction of CPU sequential, the present invention adopts clock control module 12 to guarantee the normal execution of cpu instruction.Clock control module 12 comprises d type flip flop 21 and Sheffer stroke gate 22 that a rising edge triggers.This module is according to the indication of bus state machine, and when bus can not provide data on time, the pass clock signal 24 of gated clock was effective, and this signal is as the input of d type flip flop.At the rising edge of next clock, the clock of CPU stops saltus step, and therefore the signal of CPU inside also is maintained.By the time close clock signal 24 invalid the time, CPU opens clock more again and works on.This has just guaranteed the operate as normal of CPU and bus on sequential.
In view of CPU and AMBA
TMThe inconsistent contradiction of the data width of bus, the present invention has increased by the data communication of 13 couples of CPU of Data Control module and has been controlled.Because 8 bit CPU byte addressings, and external memory storage is pressed word addressing, so the data of CPU read-write need buffer memory.
Write data controlling sub 132 comprises a moderator 41, a data buffer zone 42 and an output register 43, from the data of CPU output at first under the indication of moderator 41, be buffered in the data buffer 42 of one 4 byte, data in the pending data buffer zone are write output register 43 after all obtaining upgrading again together.
The AMBA that the present invention proposes
TMPeripheral interface circuit need meet the interface standard of AHB MASTER, has increased the address control module for this reason.The address control module comprises 51, one address extension modules 52 of a MUX and a series of latch 53.The 16 bit address signals that CPU provides at first latch, and are extended to 32 address signal by the address extension module, under the control of bus state machine, output to selectively on the ahb bus, export the various control signals of ahb bus requirement simultaneously.
Circuit of the present invention adds 8 bit CPUs, can work as 32 bit CPUs, still adopts former order set, can be directly embedded in the SoC system, and need not other module is made corresponding modification.Shorten design time like this, improve IP reuse efficient.On performance, it is equivalent to the processing speed of similar 8 embedded type CPUs, but its area and cost have a good application prospect much smaller than 32 microprocessor.
Description of drawings
Fig. 1 is AMBA
TMThe one-piece construction of peripheral interface circuit.
Fig. 2 is the structure of clock control module.
Fig. 3 is the structure of read data control module.
Fig. 4 is the structure of write data control module.
Fig. 5 is the structure of address control module.
Fig. 6 carries out sequential for the instruction under the gated clock.
Number in the figure: 1 peripheral interface circuit, 11 bus state machines, 12 clock control module, 13 Data Control modules, 14 address control modules, 131 read data controlling sub, 132 write data controlling sub, 21D trigger, 22 Sheffer stroke gates, each state of 23 bus state machines, 24 close clock signal, 31 Data Format Transform modules, 32 data buffers, 33 MUX, 41 moderators, 42 data buffers, 43 output registers, 51 MUX, 52 address extension modules, 53 latchs.
Embodiment
The AMBA that the present invention proposes
TMPeripheral interface circuit is made up of 12, one data control modules 13 of 11, one clock control module of a bus state machine and an address control module 14.Further describe the present invention below in conjunction with accompanying drawing.
Because bus provides stable data and control signal within the instruction cycle, be the precondition of the normal operation of 8 bit CPUs.But AMBA
TMThe bus existence has little time to provide the special circumstances of data, if do not adjusted, unpredictable mistake will appear in program.The present invention has increased clock control module in peripheral interface circuit.As shown in Figure 2, bus state machine is represented bus present located state.If bus can not get data in official hour, will enter the STOP state, this moment, gate-control signal gate was effective, and clock stops saltus step, and this makes CPU keep original state constant.By the time after bus had obtained stable data, clock restarted again.In order to eliminate issuable burr in the switch clock process, in clock module, increased the d type flip flop 21 of a rising edge saltus step.
Instruction after the employing clock control module is carried out sequential as shown in Figure 6, and address latch signal mem_ale is kept low level because clock stops always.From the outside, the instruction execution cycle of CPU is extended, uses this module can reduce the efficient of execution.In fact, it is the redundant correcting module that guarantees sequential.As long as can guarantee carrying out smoothly of bus read-write, this module is in idle state always, whether needs to close clock, depends on the efficient of miscellaneous equipment on the bus fully, thereby can not become the bottleneck of system speed.
The process of CPU execution command mainly comprises read data and two kinds of operations of write data.Because 8 bit CPU byte addressings, and external memory storage is pressed word addressing, so the data of each read-write all need buffer memory.The present invention has opened up the data buffer (32 and 42) that is similar to cache on two functions in the Data Control module, in order to solve the unmatched problem of speed between processor and the storer, reduce the number of times of reference-to storage, thereby improve the efficient of read-write.The Data Control module comprises read data control and two submodules of write data control, respectively read-write is controlled, and guarantees the correctness of data.
The structure of read data controlling sub as shown in Figure 3.8 bit CPU order set are for 32 data, and common organizational form is big-endian, so need convert thereof into little-endian.From 32 bit data datain of bus at first by sending into register after the Data Format Transform module again.When CPU sent read data request read, bus entered corresponding state.From data buffer 32, read 4 bytes then successively, directly send into CPU.As seen, under the normal condition, the read data operation only needs a clock, is far smaller than instruction execution cycle.
The structure of write data controlling sub as shown in Figure 4.Here need a size is set the data buffer 42 that is 4 bytes, when 4 bytes were expired in the data buffer, whole past output register 43 was write once.The detailed process scheduling is responsible for by bus state machine.When bus state machine detects the write signal write of CPU, just enter corresponding state.Moderator 41 is called in the data of 4 bytes corresponding data buffer 42 successively.After 4 byte datas in the data buffer all obtain to upgrade, again it is sent into output register 43.When sending write order hwrite on the bus by the time, again the data of register are write on the bus.As seen, finish once write operation, need 5 clocks under the normal condition altogether, and the duration of 8 bit CPU write operations is two instruction cycles (8-24 clocks), so can not trigger gated clock to bus.
The present invention is at AMBA
TMBe provided with the address control module in the peripheral interface circuit, as Fig. 5.According to the standard of AHB MASTER, address signal and data-signal differ a clock at least.This provides address and data with regard to requiring at different clock phases.So need to distinguish each state of bus, utilize bus state machine to control whole AMBA
TMThe behavior of peripheral interface circuit.Because bus address is 32, the 16 bit address signal demands that CPU provides are extended to 32 bit address lines.For other control signal, can provide according to the corresponding state of bus.
Claims (3)
1. AMBA who is applicable to 8 embedded type CPUs
TMPeripheral interface circuit can make 8 embedded type CPUs substitute based on AMBA
TM32 bit CPUs in the SoC system of bus, it is characterized in that connecting to form by circuit by a bus state machine (11), a clock control module (12), a data control module (13) and an address control module (14), wherein, the Data Control module comprises read data controlling sub (131) and write data controlling sub (132); Clock control module (12), address control module (14), Data Control module (13) all are subjected to bus state machine controls, and be connected with CPU, clock control module (12), Data Control module (13) are connected with address control module (14), wherein, read data controlling sub (131) is connected to form by a data format converting module (31), a data buffer zone (32) and a MUX (33) circuit successively, MUX (33) is connected with CPU, and is subjected to bus state machine (11) control; Write data controlling sub (132) is connected to form by a moderator (41), a data buffer zone (42) and an output register (43) circuit successively, moderator (41) is connected with CPU, and moderator (41) and output register (43) all are subjected to bus state machine (11) control; Under the control of bus state machine, clock control module (12), Data Control module (13) and address control module (14) collaborative work, wherein, read data controlling sub (131) is the data from bus, after Data Format Transform module (31), be divided into 4 bytes and deposit data buffer (32) in, under the control of bus state machine, read in batches by CPU; The data that write data controlling sub (132) is write CPU outward, indicate by moderator (41), be placed on the ad-hoc location of data buffer area, after being combined into width and being 32 data, write again in the output register (43), to solve 32 buses and 8 bit CPUs in the contradiction aspect sequential, the data width.
2. the AMBA of 8 embedded type CPUs according to claim 1
TMPeripheral interface circuit, it is characterized in that described clock control module comprises a d type flip flop (21) and a Sheffer stroke gate (22) that a rising edge triggers, d type flip flop (21) is connected with bus state machine (11) by signal wire (24), and Sheffer stroke gate (22) is connected with bus state machine (11) with trigger (21) respectively; Clock control module (12) keeps the normal instruction cycle according to the indication of bus state machine by the switch cpu clock.
3. the AMBA of 8 embedded type CPUs according to claim 1
TMPeripheral interface circuit, it is characterized in that described address control module (14) is connected to form by a series of latch (53), an address extension module (52) and a MUX (51) circuit successively, MUX (51), latch (53) are subjected to bus state machine (11) control, address control module (14) is extended to 16 bit address 32 bit address of bus request, and under the control of bus state machine (11), output to selectively on the ahb bus, export the various address signals of ahb bus requirement simultaneously.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510110254XA CN100375074C (en) | 2005-11-10 | 2005-11-10 | AMBA** peripheral interface circuit of embedded type CPu in 8 bits |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200510110254XA CN100375074C (en) | 2005-11-10 | 2005-11-10 | AMBA** peripheral interface circuit of embedded type CPu in 8 bits |
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| CN1760849A CN1760849A (en) | 2006-04-19 |
| CN100375074C true CN100375074C (en) | 2008-03-12 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102010029349A1 (en) | 2010-05-27 | 2011-12-01 | Robert Bosch Gmbh | Control unit for exchanging data with a peripheral unit, peripheral unit, and method for data exchange |
| CN102567248A (en) * | 2010-12-31 | 2012-07-11 | 中国航空工业集团公司第六三一研究所 | Control circuit and method for avoiding access conflict of dual-port memory |
| CN104375962B (en) * | 2014-11-10 | 2017-05-10 | 中国航天科技集团公司第九研究院第七七一研究所 | Unified bit width converting method in cache and bus interface of system chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020052996A1 (en) * | 2000-09-08 | 2002-05-02 | Jahnke Steven R. | Time-out counter for multiple transaction bus system bus bridge |
| CN2671026Y (en) * | 2003-09-23 | 2005-01-12 | 南京师范大学 | Embedded observer and control system developing platform |
| US20050021896A1 (en) * | 2002-10-09 | 2005-01-27 | Jae-Hun Kim | Data bus system and method for performing cross-access between buses |
| CN1670717A (en) * | 2004-03-18 | 2005-09-21 | 联想(北京)有限公司 | Apparatus and method for allocating hardware address in embedded system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020052996A1 (en) * | 2000-09-08 | 2002-05-02 | Jahnke Steven R. | Time-out counter for multiple transaction bus system bus bridge |
| US20050021896A1 (en) * | 2002-10-09 | 2005-01-27 | Jae-Hun Kim | Data bus system and method for performing cross-access between buses |
| CN2671026Y (en) * | 2003-09-23 | 2005-01-12 | 南京师范大学 | Embedded observer and control system developing platform |
| CN1670717A (en) * | 2004-03-18 | 2005-09-21 | 联想(北京)有限公司 | Apparatus and method for allocating hardware address in embedded system |
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