The special-purpose microcontroller of a kind of RFID smart card
Technical field
The present invention relates to microcontroller field, relate in particular to a kind of microcontroller of the RFID of being applied to smart card.
Background technology
RFID is the abbreviation of Radio Frequency Identification, i.e. REID.RFID radio-frequency (RF) identification is a kind of contactless automatic identification technology, and it is automatically identified destination object and obtained related data by radiofrequency signal, and identification work need not manual intervention, can work in various rugged surroundings.RFID technology can be identified high-speed moving object and can identify a plurality of labels simultaneously, swift and convenient to operate.
Smart card (Smart Card) is a kind of common name that is embedded with the plastic clip of integrated circuit (IC) chip.By the difference of embedded chip type, IC-card can be divided three classes: storage card, and logic encryption card, CPU card, but only have the just real smart card of meaning at last of CPU card.Integrated circuit in smart card (CPU card) comprises central processing unit (CPU), programmable read only memory EEPROM, random access memory ram and is solidificated in the card internal operating system COS (Chip OperatingSystem) in read only memory ROM.General employing is integrated with the microcontroller of CPU, storer and peripheral hardware as the overhead control unit of smart card.
Microcontroller (MCU, Micro Control Unit), refer to appearance and development thereof along with large scale integrated circuit, by the CPU of computing machine, RAM, ROM, regularly number device and multiple I/O Interface integration on a slice chip, form the computing machine of chip-scale, for different application scenarios, do various combination and control.
RFID smart card is that RFID technology is incorporated to intelligent card type, is called again contact type intelligent card.Its feature is: smart card contacts without circuit with card-reading apparatus, but reads and writes by contactless read-write technology (RFID technology).RFID intelligent card chip generally adopts the microcontroller of compatible MCS-51 instruction set as its overhead control unit.But RFID intelligent card chip has very harsh requirement to microcontroller:
1. execution efficiency is high: the raising of intelligent card chip performance depends on microcontroller and has higher instruction execution efficiency
2. operation is low in energy consumption: so that the voltage of being come by radio frequency interface induction can normally be worked for chip
3. extended capability is strong: so that the peripheral hardwares such as the encryption-decryption coprocessor of smartcard internal, randomizer, data collector can be mounted in microcontroller bus,
4. chip area is little: the industrialized requirement microcontroller cost of intelligent card chip is low, and the minimizing of the chip area that lowers the requirement of cost is little.
And the microcontroller of current existing numerous compatible MCS-51 instruction set can not meet or can not all meet the harsh requirement of above-mentioned RFID intelligent card chip to microcontroller conventionally.Therefore, existing MCS-51 compatible type microcontroller is difficult to directly apply to RFID field of intelligent cards.
Summary of the invention
The present invention is directed to the deficiency that existing MCS-51 compatible type microcontroller exists, provide execution efficiency high, move low in energy consumption, extended capability is strong, chip area is little, can meet RFID intelligent card chip to the harsh requirement of microcontroller, can be applicable to the special-purpose microcontroller of a kind of RFID smart card in passive RFID intelligent card chip field.
The present invention is achieved in that the special-purpose microcontroller of a kind of RFID smart card, comprise the inner structure consisting of central processing unit (CPU) and inner peripheral hardware, described middle central processing unit mainly comprises condition generator, programmable counter, instruction fetch parts, command decoder, ALU and special function register; Inner peripheral hardware refers to the peripheral hardware that is integrated in microcontroller inside, mainly comprises timer conter and interruptable controller; The address that instruction fetch parts provide according to programmable counter is taken out instruction and is deposited in order register from program storage, 4 kinds of different conditions cycles that command decoder produces according to condition generator, instruction in order register is carried out to decoding, after decoding, from storer or special function register, take out operand, and control ALU operand is carried out to relevant arithmetic or logical operation, finally the result of computing is write back to storer or special function register.The complete compatible MCS-51 instruction set of the special-purpose microcontroller of RFID smart card of the present invention.
Described central processing unit adopts the brand-new architecture Design that is different from conventional I ntel8051, and it consists of condition generator, programmable counter, instruction fetch parts, command decoder, ALU and special function register.Central processing unit is the most crucial part of microcontroller, and its working mechanism is according to the function of each instruction, to control computing or the operation of each functional part execution appointment of microcontroller.
Described condition generator consists of 4 system Counters, for generation of the one of four states cycle sequential of each machine cycle: S1, S2, S3, S4.Its output terminal provides period of state signal for whole micro controller system.
Described programmable counter is 16 digit counters, expects 16 program storage unit (PSU) addresses of instruction fetch for depositing next instruction week.According to the instruction address in PC, central processing unit takes out the instruction that will carry out from program storage.When program is carried out in order one by one, PC adds 1 automatically, to point to the address at next instruction byte place.When carrying out redirect or call instruction, PC value can jump to destination address, thus the corresponding position of control program redirect.
When instruction fetch parts 13 are carried out in instruction, the instruction address providing according to PC is taken out instruction and is stored in order register from program storage, for command decoder decoding and control.
Command decoder 14 is core components of central processing unit of the present invention, its task be control instruction fetch, translate instruction, carry out instruction, accessing operation is counted the operations such as exclusive disjunction result, and send various microoperation control signals to other functional part, coordinate the work of each functional part.
ALU 15 for realizing the adding of 8 bit data, subtract, multiplication and division computing and with or, XOR, negate, the operation such as displacement.The present invention adopts module reuse and operational code multiplex technique, optimizes ALU system architecture, to reduce chip area.
Data space unified addressing in special function register 16 and sheet, in the address space that is distributed in 0x80 ~ 0xFF that they are discrete, wherein low three of byte address is ' 000 ' register has bit addressing function.The special function register relating to of the present invention mainly contains: totalizer ACC, B-register, program status word register PSW, stack pointer SP, data pointer DPTR0, DPTR1, data pointer mask register DPS, page address register MPAGE etc.
Inner peripheral hardware refers to the peripheral hardware that is integrated in microcontroller inside, mainly timer conter and interruptable controller, consists of, to realize timer counter function and interrupt control function with priority orders.
Described timer conter, inner integrated 2 of microcontroller of the present invention, is programmable 16 bit timing counters, can work in timing mode or external counting pattern.Because each machine cycle of the present invention was comprised of 4 clock period, so timer conter is while working in timing mode, and the source of its count pulse also should be 4 fractional frequency signals of system clock mutually, and non-traditional 8051 12 fractional frequency signals.
The interrupt system that described interruptable controller is realized, has 4 interrupt sources and 2 interrupt priority levels, can realize 2 grades of breaks in service nested.Because RFID central processing unit need to be at the inner integrated serial port of microcontroller, therefore the not integrated serial port of microcontroller of the present invention, does not dispose accordingly the serial ports interruption of tradition 8051 yet and controls in interrupt system.
The present invention adopts the design of Double Data pointer, improves the efficiency of the movement of data block.The present invention contains normal data pointer DPTR0, also increases data pointer DPTR1 simultaneously.Valid pointer is selected in SEL position in DPTR mask register DPS: SEL value is to use DPTR0 at 0 o'clock, is that DPTR1 is selected in instruction in 1 o'clock, can carry out quick DPTR switching by " INC DPS ".Double Data pointer can obviously be raised the efficiency when long data block mobile.
Compared with prior art, the advantage having of the present invention is: execution efficiency is high, moves low in energy consumptionly, and extended capability is strong, and chip area is little, can meet RFID intelligent card chip to the harsh requirement of microcontroller, can be applicable to passive RFID intelligent card chip field.
Accompanying drawing explanation
Fig. 1 is the entire block diagram of the special-purpose microcontroller of a kind of RFID smart card of the present invention;
Fig. 2 is the door control unit structural drawing of the gated clock of the special-purpose microcontroller of a kind of RFID smart card of the present invention;
Fig. 3 is the sequential chart (the outer RAM of the sheet of take writes sequential as example) of the special-purpose microcontroller of a kind of RFID smart card of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the special-purpose microcontroller of a kind of RFID smart card of the present invention is further elaborated.
The special-purpose microcontroller of RFID smart card, can complete compatible MCS-51 instruction set, forms its inner structure, as shown in Figure 1 by central processing unit 10 and inner peripheral hardware 20.Wherein central processing unit 10 is mainly comprised of condition generator 11, programmable counter 12, instruction fetch parts 13, command decoder 14, ALU 15 and special function register 16.Inner peripheral hardware 20 refers to the peripheral hardware that is integrated in microcontroller inside, mainly timer conter 21 and interruptable controller 22, consists of.The groundwork flow process of microcontroller is: the address that instruction fetch parts 13 provide according to programmable counter 12 is taken out instruction and deposited in order register from program storage, 4 kinds of different conditions cycles that code translator 14 produces according to condition generator 21, instruction in order register is carried out to decoding, after decoding, from storer or special function register 16, take out operand, and control 15 pairs of operands of ALU and carry out relevant arithmetic or logical operation, finally the result of computing is write back to storer or special function register 16.
Central processing unit 10 is the most crucial parts of microcontroller, and its working mechanism is according to the function of each instruction, to control computing or the operation of each functional part execution appointment of microcontroller.Central processing unit of the present invention adopts the brand-new architecture Design that is different from conventional I ntel8051, and it consists of condition generator 11, programmable counter 12, instruction fetch parts 13, command decoder 14, ALU 15 and special function register 16.
Condition generator has 4 system Counters to form, for generation of the one of four states cycle sequential of each machine cycle: S1, S2, S3, S4.Its output terminal provides period of state signal for whole micro controller system.
Programmable counter is 16 digit counters, expects 16 program storage unit (PSU) addresses of instruction fetch for depositing next instruction week.According to the instruction address in PC, central processing unit takes out the instruction that will carry out from program storage.When program is carried out in order one by one, PC adds 1 automatically, to point to the address at next instruction byte place.When carrying out redirect or call instruction, PC value can jump to destination address, thus the corresponding position of control program redirect.
When instruction fetch parts 13 are carried out in instruction, the instruction address providing according to PC is taken out instruction and is stored in order register from program storage, for command decoder decoding and control.
Command decoder 14 is core components of central processing unit of the present invention, its task be control instruction fetch, translate instruction, carry out instruction, accessing operation is counted the operations such as exclusive disjunction result, and send various microoperation control signals to other functional part, coordinate the work of each functional part.
ALU 15 for realizing the adding of 8 bit data, subtract, multiplication and division computing and with or, XOR, negate, the operation such as displacement.The present invention adopts module reuse and operational code multiplex technique, optimizes ALU system architecture, to reduce chip area.
Data space unified addressing in special function register 16 and sheet, in the address space that is distributed in 0x80 ~ 0xFF that they are discrete, wherein low three of byte address is ' 000 ' register has bit addressing function.The special function register relating to of the present invention mainly contains: totalizer ACC, B-register, program status word register PSW, stack pointer SP, data pointer DPTR0, DPTR1, data pointer mask register DPS, page address register MPAGE etc.
Inner peripheral hardware 20 refers to the peripheral hardware that is integrated in microcontroller inside, mainly timer conter 21 and interruptable controller 22, consists of, to realize timer counter function and interrupt control function with priority orders.
Timer conter 21, inner integrated 2 of microcontroller, for programmable 16 bit timing counters, can work in timing mode or external counting pattern.Because each machine cycle of the present invention was comprised of 4 clock period, so timer conter is while working in timing mode, and the source of its count pulse also should be 4 fractional frequency signals of system clock mutually, and non-traditional 8051 12 fractional frequency signals.
The interrupt system that interruptable controller 22 is realized, has 4 interrupt sources and 2 interrupt priority levels, can realize 2 grades of breaks in service nested.Because RFID central processing unit need to be at the inner integrated serial port of microcontroller, therefore the not integrated serial port of microcontroller of the present invention, does not dispose accordingly the serial ports interruption of tradition 8051 yet and controls in interrupt system.
The present invention adopts Double Data pointer to design to improve the efficiency of the movement of data block.The present invention contains normal data pointer DPTR0, also increases data pointer DPTR1 simultaneously.Valid pointer is selected in SEL position in DPTR mask register DPS: SEL value is to use DPTR0 at 0 o'clock, is that DPTR1 is selected in instruction in 1 o'clock, can carry out quick DPTR switching by " INC DPS ".Double Data pointer can obviously be raised the efficiency when long data block mobile.
The present invention has following beneficial effect:
Efficient timing Design of the present invention: nearly 12 of the system clock cycle numbers that each machine cycle of tradition 8051 comprises, cause instruction execution efficiency low, program execution speed is slow.The present invention adopts the new high efficiency timing Design that is different from tradition 8051, the eliminate redundancy clock period, the system clock cycle number that each machine cycle is comprised reduces to 4, makes microcontroller under same systems clock, can reach the instruction execution speed of 8051 approximately 3 times of tradition.Microcontroller sequential organization of the present invention is (the outer data storage area of the sheet write operation sequential of take is example) as shown in Figure 3, each machine cycle is divided into 4 period of state (S1, S2, S3, S4), each period of state is only comprised of 1 clock period, at different period of state, carries out different bus activity.
Low power dissipation design of the present invention: for passive RFID intelligent card chip, low power dissipation design is a vital factor, and too high power consumption can cause chip normally to work.Except adopting the low power dissipation design of traditional microcontrolled park mode, the present invention also adopts Clock Gating Technique to reduce microcontroller operation power consumption.Adopt gated clock, can significantly reduce the switch activity of circuit and clock network, by keeping apart sequential element in idle condition and clock network reduces power consumption.In the present invention, for storer, adopt the method for exampleization door control unit in RTL code to add gated clock to ROM and RAM.For register, after front end adds enable signal to the register in RTL code, in rear end, utilize eda tool Power Compiler invoke script automatically to add gated clock.The door control unit that gated clock adopts is not realized by unity logic door simply, but is jointly comprised of latch and logic gate, as shown in Figure 2, can effectively avoid adding the burr phenomena that may occur after gated clock.
Peripheral hardware expansion design of the present invention: general parallel communication interface or the serial communication interface expanding peripherals of adopting of tradition 8051, its extended capability is limited, and when having a large amount of peripheral hardwares to expand, it is extremely complicated that expansion work will become.Microprocessor of the present invention is not integrated with parallel port and serial ports, but by by outside special function register bus (xsfr_bus) and the overhanging peripheral hardware expansion bus that is used as of external data memory bus (xdat_bus).The outer special function register bus access speed of sheet, but address space is limited; The outer data ram bus address space of sheet is abundant, but access speed is slower.The present invention proposes dual bus peripheral hardware expansion scheme, for the variety classes register of peripheral hardware, adopts different bus expansions, and two kinds of buses advantage is separately given full play to.For example, the higher control register of rate request and status register are adopted to the outer special function register bus expansion of sheet at a high speed, space hold more data register in address is adopted to the outer data ram bus expansion of the sufficient sheet of address space.Compare with traditional parallel or serial port expansion, this expansion scheme makes the peripheral hardware of microcontroller expand more horn of plenty and flexible.
Low-cost design of the present invention: the low-cost design of chip is by reducing chip area, also reduce that the shared hardware resource consumption of chip realizes.The methods such as the present invention passes through module reuse, and operational code is multiplexing, redundant component cutting are simplified and optimize microcontroller architecture, reduce chip and realize cost.Module reuse and operational code are multiplexing to be narrated while having introduced ALU above.The cutting of redundant component is mainly for those standard 8051 standard configurations, but the functional part that RFID intelligent card chip need not be used, such as parallel communication interface, serial communication interface, watchdog circuit etc.Guaranteeing, under the prerequisite that RFID intelligent card chip can normally be worked, these redundant components to be cropped to reduce hardware resource consumption, thereby reduce chip, realize cost.