CN115080494B

CN115080494B - SPI slave circuit, SPI communication method, interface and chip

Info

Publication number: CN115080494B
Application number: CN202210881133.9A
Authority: CN
Inventors: 张华秋; 白鑫; 宋霜; 柯凌云; 常胜; 乔宁
Original assignee: Shanghai Shizhi Technology Co ltd; Shenzhen Shizhi Technology Co ltd
Current assignee: Shanghai Shizhi Technology Co ltd; Shenzhen Shizhi Technology Co ltd
Priority date: 2022-07-26
Filing date: 2022-07-26
Publication date: 2022-12-27
Anticipated expiration: 2042-07-26
Also published as: CN115080494A

Abstract

The invention discloses an SPI slave circuit, an SPI communication method, an interface and a chip. In order to solve the technical problem of high power consumption of the traditional synchronous SPI slave machine, the SPI slave machine circuit comprises: the event-driven generation module generates events and instructions based on signals from the host; the state machine updates the state based on the event and the instruction; and the read-write control circuit executes read operation or write operation based on the event and the instruction. The SPI slave machine has novel structure and less hardware resource consumption, can effectively play the advantage of low power consumption of an asynchronous circuit, reduces the power consumption to 25 percent of that of a synchronous circuit under the same condition, and has higher real-time property. The invention is suitable for the field of brain-like chips.

Description

SPI slave circuit, SPI communication method, interface and chip

Technical Field

The invention relates to an SPI slave machine circuit, an SPI communication method, an interface and a chip, in particular to an SPI slave machine circuit, an SPI communication method, an interface and a chip which are designed and developed based on an asynchronous circuit in an EDA tool and have ultra-low power consumption.

Background

Serial Peripheral Interface (SPI) is a high-speed Serial communication Interface, which operates in a master-slave manner and generally includes a master (master) and a plurality of slaves (slave).

Fig. 1 is a schematic diagram of a classic SPI structure, where a master and a Slave communicate with each other by using a clock line CLK, a master output Slave input line MOSI, a chip Select SS (Slave Select), and a master input Slave output line MISO, where the MOSI is transmitted in a serial manner from the master to the Slave activated by a chip Select signal, and since serial transmission is adopted, encoded data is transmitted in bits (bit), and if 4-bit encoded data is transmitted, an effective clock signal of at least 4 cycles is required.

In the prior art, the SPI is usually developed based on a synchronous circuit technology and is implemented by using a shift register. However, in the synchronous SPI, both the transmitting and receiving devices need to maintain complete synchronization, and the receiving and transmitting devices need to use the same clock, which is from the same clock source, and all registers of the slaves are updated based on the unified clock. However, when the wiring is laid out, the lengths of the clock lines are different due to different positions of different modules, and the delays of the clock signals transmitted through the clock lines to different modules are different, which affects the synchronization among the modules. In addition, the large number of clock lines increases chip area and power consumption.

To avoid the disadvantages of synchronous circuits, academia have attempted SPI design using asynchronous circuits, however, since asynchronous circuits include complex paths such as combinatorial cycles, commercial Electronic Design Automation (EDA) tools cannot directly support asynchronous circuit design, and designing asynchronous circuits in commercial EDA tools faces many challenges.

Some approaches perform asynchronous SPI circuit design based on Relative Timing (RT) constraints, as shown in fig. 2. The RT constraint, which requires the data of the data path to stabilize before the control signal of the control path arrives, i.e. the latch L, achieves the required ordering without a clock network _i+1 The data input of (a) needs to be stable before its clock input arrives to ensure that the complete valid data is sampled at the valid edge of the clock.

In the prior art 1, makar G H, badenas F J, simone R G, et al, low Power SPI Design Based on Relative Timing Techniques [ C ]//2019 26th IEEE International Conference on Electronics, circuits and Systems (ics) IEEE, 2019: 166-169 "uses Relative Timing (RT) Based asynchronous circuit Design SPI, but the circuit architecture designed by the document is not optimized enough, the area and the Power consumption are also high, and the Low Power consumption advantage of the asynchronous circuit is not really exerted.

In prior art 2, bhaddra D, steps K s, design of a low power, relative timing based asynchronous MSP430 microprocessor [ C ]// Design, automation & Test in Europe Conference & exception (DATE), 2017, IEEE, 2017: 794-799", a state machine is used to implement an asynchronous circuit Design based on RT constraint, the state machine includes two HS control signals, the two HS control signals mutually provide an excitation request signal req and mutually provide a response signal ack. Once the state machine works, handshake is repeated, a clock control signal CLK is continuously generated and circulated, and a large amount of power consumption is generated; meanwhile, synchronization with other signals cannot be guaranteed, and the state of the state machine is possibly changed, but other data are still in the last state and are not in one beat. Therefore, the circuit performance is not stable enough.

Therefore, an SPI architecture that can be developed based on conventional commercial EDA tools and that exerts the advantage of low power consumption of asynchronous circuits is needed to achieve stable, efficient, and low-power consumption data transmission.

Disclosure of Invention

In order to solve or alleviate some or all of the above technical problems, the present invention uses an asynchronous circuit to design a new SPI slave, which is specifically realized by the following technical scheme:

an SPI slave circuit comprising: the event driving generation module at least receives an SPI clock from the host and the input signal of the slave output by the host to generate an event and an instruction; the state machine updates the state based on the event and the instruction; the state machine is used for controlling the event driving generation module and the read-write control circuit to execute operation corresponding to the state of the state machine; and the read-write control circuit executes read operation or write operation based on the event and the instruction.

In some kind of embodiments, the event-driven generation module and/or the state machine and/or the read-write control circuit are asynchronous circuits.

In some class of embodiments, the event driven generation module comprises an event generation unit and a first register set, the first register set comprising at least one register; the event generation unit includes: the asynchronous counter and the comparator as well as the first AND gate; the asynchronous counter counts the negated SPI clock; the comparator compares the count value of the asynchronous counter with a reference sequence; the first AND gate is used for AND-operating the output of the comparator and the SPI clock and outputting an event; and the first register group receives the input and output instruction of the host output slave machine based on the event.

In some embodiments, the event generating unit further includes a second and gate having an input terminal connected to the chip select signal and the SPI clock, and an output terminal connected to the input terminal of the asynchronous counter via an inverter.

In certain embodiments, the instruction includes a read/write flag bit and a burst _ len, which indicates the length of consecutive addresses for a read or write operation, and a start address.

In one class of embodiments, the state machine comprises: the first C unit receives the event and is coupled with the first register control unit through a handshake protocol; the first register control unit outputs a first control signal, and the first control signal is coupled with a clock end of the state conversion unit; and the state transition unit is used for calculating the next state based on the instruction and performing state transition on the effective edge of the first control signal.

In some class of embodiments, the state transition unit includes combinational logic and a second register bank, the second register bank including at least one register; the input end of the combinational logic is coupled with the output end of the second register group, and the output end of the combinational logic is coupled with the input end of the second register group; the combinational logic calculates a next state based on the instruction, and updates a current state of the second register set register at an active edge of the first control signal.

In some class of embodiments, the state machine includes an endpoint unit coupled with the first register control unit via a handshake protocol.

In certain class of embodiments, the handshake protocol is a four-phase bonded data handshake protocol or a two-phase bonded data handshake protocol.

In some class of embodiments, the SPI slave is designed based on relative timing.

In one class of embodiments, the read-write control circuitry includes: a second C unit receiving the event; the second register control unit is coupled with the second C sending unit through the first handshake signal and outputs a second control signal; the third register control unit is coupled with the second register control unit through a second handshake signal and outputs a third control signal; the third control signal is a clock signal for read or write operation; the cross merging module is coupled with the third register control unit through a third handshake signal and outputs an address signal based on the instruction; a third register, a clock terminal of which is coupled to the second control signal, and registers the address signal on an active edge of the second control signal; the read-write control circuit executes read-write operation based on the clock signal of the read-write operation and the address registered by the third register.

In some class of embodiments, the third handshake signal comprises a third request and a third acknowledge signal;

in some class of embodiments, the cross-merge module includes a first module and a second module; the first module and the second module are both coupled to a third request, an acknowledgement signal returned by the first module and an acknowledgement signal returned by the second module are respectively coupled to a first input terminal and a second input terminal of a third C unit, and the third C unit outputs a third acknowledgement signal; in the latest state of the state machine, based on a third request, the first module decrements the burst _ len length of the instruction or/and the second module increments the start address of the instruction, wherein the incremented address is coupled to the input terminal of the third register.

In a certain class of embodiments, the cross-merge module further comprises two endpoint units coupled to the first module and the second module, respectively, via a handshake protocol.

In some class of embodiments, the SPI slave circuitry is coupled to a plurality of memory spaces; and during the writing operation, selecting one of the plurality of storage spaces, and writing data into the corresponding address of the selected storage space or reading data from the corresponding address of the selected storage space based on the address signal and the clock signal of the reading or writing operation.

In some type of embodiment, a delay unit is added in the request path of the handshake to delay the request in the corresponding handshake path.

In some class of embodiments, the delay cells are programmable cells.

In some embodiments, any register input data in the SPI slave circuit is stable before its clock signal arrives.

In some embodiments, any element of the first through third registers is replaced with a latch; or/and any one of the first to second register sets is replaced by a latch set.

When any slave is activated, the activated slave receives an SPI clock from the master and the master outputs a slave input signal to generate an event and a command; updating a state of a state machine based on the event and the instruction; the state machine is used for controlling the activated slave machine to execute a function corresponding to the state of the state machine; in a current state, a read operation or a write operation is performed based on the event and the instruction.

In some embodiments, the activated slave receiving the SPI clock from the master and the master output slave input signal to generate the event and the command comprises: counting the negated SPI clock by using an asynchronous counter; comparing the count value of the asynchronous counter with the reference sequence to obtain a comparison value; performing AND operation on the comparison value and an SPI clock, and outputting an event; and the event is input into a clock end of the first register group, and controls the receiving host to output the input of the slave and output the instruction.

In some class of embodiments, the state of the state machine; the state machine includes a first data path that computes a next state of the state machine based on the instruction and a first control path that generates a first control signal based on the event;

updating a current state of a state machine based on the next state upon arrival of the first control signal

In some class of embodiments, said performing a read operation or a write operation based on said event and said instruction comprises: handshaking with a second control unit after the first request is generated based on the event, wherein the second control unit generates a second control signal; the second control unit handshakes with a third control unit, and the third control unit outputs a third control signal; the third control signal is a clock signal for a read or write operation; the third control unit handshakes with a cross-merge module, which outputs an address signal based on the instruction; the second control signal is coupled with a clock end of a third register and controls the third register to register the address signal; the read-write control circuit executes read or write operation based on the third control signal and the address registered by the third register.

In some class of embodiments, the slaves communicate based on a handshake protocol that is a four-phase bundled data handshake protocol or a two-phase bundled data handshake protocol.

In some type of embodiment, a delay is added in the request path of the handshake to delay the request in the corresponding handshake path.

In some class of embodiments, the delay is a programmable delay.

In some embodiments, either of the first and second registers is replaced with a latch, or/and the first set of registers is replaced with a set of latches.

An SPI interface comprising an SPI slave circuit as described above, or a method of communicating with an SPI master as described above.

A chip comprising an SPI slave circuit as described above or communicating with a host using a method of communicating with an SPI host as described above.

In certain embodiments, the chip is a brain-like chip.

Some or all embodiments of the invention have the following beneficial technical effects:

1) The SPI slave machine adopts an asynchronous circuit design, has a better framework and less hardware resource consumption, and can effectively play the advantage of low power consumption of the asynchronous circuit.

2) The state machine of the invention only generates the clock control signal when the state is switched, namely only generates when needed, and does not always circulate, and the clock end of the register has low turnover frequency, so the power consumption of the state machine (FSM) is lower.

3) The asynchronous counter in the event generating circuit counts the SPI clock after negation, the design is simple, the realization is easy, the hardware consumption is low, the burr interference is effectively reduced, and the area and the power consumption are saved. The existing synchronous counter also has an adder, and the ripple counter used by the invention does not need the adder.

4) The asynchronous SPI slave machine can be in butt joint with an SPI host machine which accords with a standard protocol.

5) Compared with the traditional SPI slave machine of a synchronous circuit, the asynchronous SPI slave machine has the advantages that the area is almost the same, and the total power consumption is only about 1/4 under the condition of large working load. In addition, under the same design environment, simulation environment and process, the asynchronous slave machine provided by the invention can run faster, has a wider range and is stronger in applicability.

6) The asynchronous SPI slave machine can be designed based on the traditional commercial EDA, and the design efficiency is improved.

Further advantages will be further described in the preferred embodiments.

The technical solutions/features disclosed above are intended to be summarized in the detailed description, and thus the ranges may not be completely the same. The technical features disclosed in this section, together with technical features disclosed in the subsequent detailed description and parts of the drawings not explicitly described in the specification, disclose further aspects in a mutually rational combination.

The technical scheme combined by all the technical features disclosed at any position of the invention is used for supporting the generalization of the technical scheme, the modification of the patent document and the disclosure of the technical scheme.

Drawings

FIG. 1 is a schematic diagram of a classical SPI architecture;

FIG. 2 is a prior art asynchronous SPI circuit based on Relative Timing (RT) constraints;

FIG. 3 is a schematic diagram of an asynchronous SPI slave in an embodiment of the present invention;

FIG. 4 is a schematic diagram of an event driven generation module in accordance with a preferred embodiment of the present invention;

FIG. 5 is an example of a ripple counter;

FIG. 6 is a state machine of an improved embodiment of the present invention;

FIG. 7 is a schematic view of the C cell;

FIG. 8 is a state machine of a preferred embodiment of the present invention;

FIG. 9 is an end point unit structure;

FIG. 10 is a read-write control circuit of a preferred embodiment of the present invention;

FIG. 11 is a circuit diagram of a cross-merge (Fork/Join) module in accordance with a preferred embodiment of the present invention;

fig. 12 is a comparison of the performance of the asynchronous slave and the synchronous slave according to the present invention.

Detailed Description

Since various alternatives cannot be exhaustively described, the following will clearly and completely describe the main points in the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. It is to be understood that the invention is not limited to the details disclosed herein, which may vary widely from one implementation to another.

Unless defined otherwise, a "/" at any position in the present disclosure means a logical "or". The ordinal numbers "first," "second," etc. in any position of the invention are used merely as distinguishing labels in description and do not imply an absolute sequence in time or space, nor that the terms in which such a number is prefaced must be read differently than the terms in which it is prefaced by the same term in another definite sentence.

The present invention may be described in terms of various elements combined into various embodiments, which may be combined into various methods, articles of manufacture. In the present invention, even if the points are described only when introducing the method/product scheme, it means that the corresponding product/method scheme explicitly includes the technical features.

When a step, a module or a feature is described as being present or included in any position of the present invention, it is not implied that the presence is exclusive and only exists, and other embodiments can be fully realized by the technical solution disclosed by the present invention and other technical means. The embodiments disclosed herein are generally for the purpose of disclosing preferred embodiments, but this does not imply that the opposite embodiment to the preferred embodiment is excluded/excluded from the present invention, and it is intended to cover the present invention as long as such opposite embodiment solves at least some technical problem of the present invention. Based on the point described in the embodiments of the present invention, those skilled in the art can completely apply the means of substitution, deletion, addition, combination, and order change to some technical features to obtain a technical solution still following the concept of the present invention. Such a configuration without departing from the technical idea of the present invention is also within the scope of the present invention.

The clock different from all SPI slaves (slave) in the synchronous technology is generated by a unified clock source (clock signal is generated by using a crystal oscillator). The asynchronous SPI slave machine has no unified clock source, the clock signal is generated by the driving source, each slave machine generates its own clock/control signal, and the modules realize communication by using handshake protocol. The present invention provides for stabilizing the data before the handshake signals reach each stage by defining or setting the necessary timing assumptions.

A synchronization circuit: the change of state of all flip-flops is synchronized with the applied clock signal.

An asynchronous circuit: the circuit has no unified clock, the trigger time of different computing units is directly caused by the change of external input, and the fixed causal relationship among clocks/drivers does not exist. Communication is typically via a handshake protocol.

Handshake protocol: comprising a data line (data), a request signal (req) identifying the validity of the data and a reply signal (ack) indicating that the data has been accepted. The communication links are also referred to as handshake channels, each implementing a silicon oscillator whose operating frequency is matched to the delay of the associated data path. The asynchronous circuit of the present invention may use a four-phase binding data handshake protocol, or a two-phase binding data handshake protocol, etc., which is not limited by the present invention. Regardless of the protocol used, the core of the asynchronous circuit of the present invention is that the data is stabilized before the clock CLK of the register control unit is pulled up.

Relative Timing (RT): in a timing constraint in a combinational or asynchronous circuit, the data passed by the data path needs to arrive before the signal passed by the spatio-temporal/control path before the register can correctly store the data. The RT constraint is the focus of time sequence verification of asynchronous circuit design, and is a method for realizing a four-phase binding data handshake protocol.

Unit C: the circuit is a state holding element in asynchronous circuit design, and the output state is kept unchanged when two inputs are different.

Fig. 3 is a schematic diagram of an asynchronous SPI slave of the present invention, including an event driven generation module, a finite state machine, and a read-write control circuit. Like a traditional SPI slave, the asynchronous SPI slave at least comprises an input port, namely an SPI clock (SPI CLK, the following is the same), an MOSI (master output slave input, the following is the same), and an output port MISO (master input slave output, the following is the same). The SPI clock is only one input of the asynchronous SPI slave of the present invention, or referred to as a driving source, and is different from the clock of the synchronous circuit in nature.

The event driving generation module at least receives an SPI clock and MOSI signals from a host, when a slave is activated, the slave generates an event (event) based on the SPI clock, registers the MOSI and generates a command (instruction for short) required by a subsequent module based on the event and a state value output by a state machine.

The state machine performs state transition based on the event and the instruction instr output by the event driving generation module under the influence of Combinatorial Logic (CL), and updates the current state of the state machine.

In the current state, when an event arrives, the read-write control circuit performs a read or write operation under the influence of the instruction instr.

Alternatively, some parts or modules of the asynchronous SPI slave of the present invention may be implemented using synchronous circuit technology, and preferably all modules of the SPI slave of the present invention are asynchronous circuits to achieve extremely low power consumption.

The event-driven generation module of the invention comprises an event generation unit and a register set. An event generating unit comprising: the travelling wave counter is used for counting the SPI clock after negation; a comparator that compares the count value of the ripple counter with a reference sequence; the first AND gate is used for AND-operating the comparison value of the comparator and the SPI clock and outputting an event; and the first register group receives the MOSI and outputs an instruction based on the event generated by the event generating unit.

Fig. 4 is a schematic diagram of an event driven generation module according to a preferred embodiment of the present invention, further, the event generation unit further includes a second and gate having inputs connected to the chip select signal and the SPI clock, and an output connected to an input of the ripple counter through an inverter, and when the chip select signal corresponding to the slave is in an active state, the slave is activated to respond to a master command. In addition, the input end of the first and gate may be connected to the SPI clock or the output of the second and gate, which is not limited in the present invention.

Alternatively, the selection of the target slave machine of the invention can be selected by identification check instead of chip selection signal line, and for the case of multiple slave machines, the invention can not need to configure a chip selection signal line for each slave machine, specifically refer to chinese patent CN 202210115740.4 (grant No. CN 114138703B), so the invention reduces the complexity of wiring and layout; in addition, for target slaves with the number of 2 or more, one or more chip selection signal lines can be arranged, or no chip selection signal lines can be arranged, and the chip selection signal lines have strong universality and flexibility.

Compared with the prior art 1, the invention increases the time delay of half clock cycle by counting after negating the SPI clock, so that the generation of event signals is delayed by half clock cycle, noise interference such as burrs and the like can be reduced, and data stability is facilitated. Compared with the prior art 1, the invention does not need to add a delay line and a C unit behind the comparator, thereby reducing the design complexity, avoiding consuming redundant hardware resources and further saving the area and the power consumption. In one embodiment, the chip selection signal and the SPI clock output gating signals through an AND gate, and then are input into an asynchronous counter after being inverted by an inverter; in a preferred embodiment, the asynchronous counter is a ripple counter (ripple counter), which is not limited in the present invention.

The traveling wave counter counts the SPI clock after negation, and the numerical value is gradually increased from 0; the comparator compares the count value of the ripple counter with a reference value, which is not a number but a numerical sequence, such as 0,1,2,3 … …, and outputs the result of the comparison. The output of the comparator is sampled at an active edge of the SPI clock, e.g., a rising or falling edge, and a valid event (also referred to herein as an event) is generated when the sampling result is 1. In one embodiment shown in fig. 4, sampling of the comparator output using the SPI clock is accomplished using a first and gate.

The event is used as a clock control signal of the register set, and when an effective event exists, the register set receives an MOSI signal from the host and outputs an instruction instr. Specifically, when the count value is 0, event [0] is pulled high to 1, at which time the other bit of the event (event) is 0, the register reg0 registers the MOSI signal; when the count value is 1, event [1] is pulled high to 1, and the other bit of the event [ event ] is 0, the register reg1 registers the MOSI signal; when the count value is 2, event 2 is pulled high to 1, at which time the other bit of the event is 0, register reg2 registers the MOSI signal, and so on.

The instruction instr may include a plurality of segments, such as a read/write flag bit, a start address addr0, a burst _ mode for indicating whether to enter a burst mode, i.e., a continuous operation mode, a burst _ len for indicating a length of a readable and writable continuous address, for example, a read instruction reads 5 continuous addresses (burst _ len is equal to 5) to save bandwidth, and a data. The instruction instr structure is flexibly configurable, which is not a limitation of the present invention.

Alternatively, the present invention may use a synchronous counter for counting, but the use of a synchronous counter does not optimize power consumption. Preferably, the present invention uses an asynchronous counter to significantly reduce power consumption.

FIG. 5 is an example of a ripple counter, and the ripple counter structure is not limited by the present invention. The ripple counter of the present invention can adopt any structure and use any number of bits, if the current count value of the ripple counter is 2, the ripple counter is compared with the reference value at the reference end of the 5-bit combination comparator, the value of the bit corresponding to the reference value 2 (i.e. the bit combination 00010) is pulled high, and then the ripple counter is logically AND-ed with the SPI clock, so as to generate an effective event at the next rising edge of the SPI clock.

The SPI bus does not have a physical layer frame structure of fixed channel coding, and different frame structures can be adopted for different slave devices. In some embodiments, the ripple counter is cleared or reset after counting one frame of instructions for the received MOSI signal. In other embodiments, the ripple counter is cleared or reset after counting the read/write flag bits in only one frame of instructions, so as to save the ripple counter bits. Similarly, the ripple counter is cleared or reset after counting any segment of the frame data structure to reduce the counter bandwidth. In a preferred embodiment, the ripple counter length is the same as the longest segment in the frame data structure.

The register set includes at least one register, and in a preferred embodiment, the number of registers is the same as the length of instruction instr, or the length of the longest segment in instruction instr.

Fig. 6 is a state machine structure of an embodiment of the present invention, the state machine comprising: the first C unit receives the event and is coupled with the first register control unit through a handshake protocol; the first register control unit outputs a first control signal, and the first control signal is coupled with a clock end of the state conversion unit; and the state transition unit is used for calculating the next state based on the instruction and performing state transition on the effective edge of the first control signal.

The state machine is an important component of an asynchronous SPI slave. The traditional state machine updates the state value based on a clock, the state machine adopts an asynchronous circuit design, the state values of the state machines are updated based on events, the state machines work independently and asynchronously, and each state machine is provided with an independent asynchronous handshake controller (namely a register controller referred to as the following description) and a request response channel so as to realize a clock line similar to a synchronous state machine. The state machine of the invention only comprises one register control unit, so that one event (event) is generated only once without repeated handshake, therefore, the clock end of the register is lower in turnover frequency, and the state machine has lower power consumption compared with the existing asynchronous state machine like accurate gating.

C-unit 601 receives events and communicates with register control unit 604 via a handshake protocol, and further, a delay unit 602 is coupled to C-unit 601 and register control unit 604 for delaying the request req to ensure that the data path has sufficient settling time. The register control unit 604 generates a control signal to control the state transition unit to update the current state.

The C cell is a logic circuit with two inputs a, b and one output y, representing the sign and input-output relationship as shown in fig. 7. The C unit is a state holding element, and when two inputs are different, the output state remains unchanged, and the relationship between the input and the output can be expressed as: y is _n =ab+(a+b)y _n-1 Wherein n is a positive integer, y ₀ And =0. The C-unit has the advantage that even if the event is short, it can be recorded, and if there is an event (event) it generates a request signal req for a timely response.

As illustrated in fig. 6, the state transition unit includes a register 605 and a combinational logic 606. An input of the combinational logic 606 is coupled to an output of the register 605 and an output of the combinational logic 606 is coupled to an input of the second register 605.

Register 605 stores the current state value and updates the current state with the next state under the action of register control unit 604 after the next state calculation is completed.

The next state is calculated according to the state function, the state function is a simple combinational function, the calculation is realized based on the combinational logic circuit 606, and the combinational logic circuit 606 is a gate circuit, can be configured, is easy to modify and debug, and has the characteristics of low power consumption and small size.

The working principle of the state machine in fig. 6 is: if req and ack default to low, high is active. One input end of the C unit 601 receives an event (event value is 1) generated by the event driving generation module to generate a valid request signal req, the request signal req1 is input to the register control unit 604 after being delayed, the first register control unit 604 generates a clock control signal clk1, and the register 605 updates the current state value to the new state calculated by the combinational logic at the valid edge of the clock control signal clk 1. The register control unit generates a response signal ack while generating the clock control signal clk1, and the response signal ack is input to the other input terminal of the C unit 601 through the inverter 603.

The state machine determines the state of the slave, which affects whether each module circuit of the slave performs a corresponding operation or function. Specifically, the state machine is used for controlling the updating of the event driving generation module and the read-write control circuit. The state of the state machine affects the register set of the event driving generation module to register the MOSI, affects when to update the value in the register in the read-write control circuit, and the like, and different states and counter values tell the circuit which register to store information. For example, in the state 1, a register for registering burst _ len in the read/write control circuit is mainly updated, and in the state 2, a register for registering an address (address) in the read/write control circuit is mainly updated.

The state conversion unit comprises at least one register, and the number of the registers required by the state conversion unit can be flexibly configured. For example, if the state machine uses 4 bits to represent its state, 4 registers and at least one logic combination circuit are required for the corresponding. Fig. 8 shows that the state machine uses 4 bits to represent the state, including 4 registers.

In a preferred embodiment, the state machine further comprises an endpoint unit 607 coupled to the register control unit 604 and then communicating with the register control unit 604 via a handshake protocol, wherein if the data in the register control unit 604 is stable, a request signal req' is generated to the endpoint unit to inform the endpoint unit that the data is available. The endpoint unit is used to indicate the termination at the node to enable multiplexing of the register control unit without separately designing the register control unit used at the termination node.

The terminal unit structure is shown in fig. 9 and includes a C unit 901 and an inverter 902, one input terminal req of the C unit 901, the C unit outputs a response signal ack, and the response signal ack output by the C unit is inverted by the inverter 902 and fed back to the other input terminal of the C unit 901.

FIG. 10 is a read-write control circuit according to a preferred embodiment of the present invention, including: a second C unit 1001 receiving the event; a second register control unit 1003 coupled to the second parasitic C unit 1001 via the first handshake signals (req 1, ack 1), and outputting a control signal ctrl2; a third register control unit 1005 coupled to the second register control unit via second handshake signals (req 2, ack 2) and outputting a control signal ctrl3, where the control signal ctrl3 is a clock signal for a read or write operation; the cross combination module, also called Fork/Join module, is coupled with the third register control unit through a third handshake signal, and outputs an address signal based on the instruction;

a third register 1018, having a clock terminal coupled to ctrl2, registers the address signal at the active edge of ctrl 2. The read-write control circuit executes the read-write operation based on the clock signal of the read-write operation and the address registered by the third register.

In the current state, communication is performed via a handshake protocol after an event has come. The event-based request req1 of the C unit 1001 is delayed by the delay unit 1002 and transmitted to the register control unit 1003, and the register control unit 1003 generates a control signal ctrl3 for controlling the register 1018 to output the address signal addr _ out.

The second register control unit 1003 generates the control signal ctrl2 and returns a response signal ack1, and the response signal ack1 is fed back to the other end of the C unit through the inverter 1019. The register control unit 1003 generates req2, the req2 is delayed by the delay unit 1004 and then transmitted to the register control unit 1005, and the register control unit 1005 generates a control signal ctrl3, wherein the control signal ctrl3 is a clock control signal Clk _ ctrl for read/write operations. The register control unit 1005 returns a response signal ack2 to the register control unit 1003 while generating the control signal ctrl 3.

The third register control unit 1005 is coupled via handshake signals (req 3, ack 3). In a modified embodiment, a delay unit 1006 is coupled between the register control unit 1005 and the cross-merge module for delaying the request signal to satisfy the Relative Timing (RT) constraint. In fig. 10, the register control unit 1005 sends out a request signal req3, which is delayed by the delay unit 1006 and then transmitted to the register control unit of the cross merge module.

The cross merging module comprises two groups of tasks which are executed in parallel, wherein one group carries out burst _ len control, and the other group carries out address addr control. Specifically, the Fork/Join module circuit structure is shown in fig. 11, and includes a first module, a second module, and a C cell 1017.

The first module includes a register control unit 1008, a register 1007, and a logic unit 1011 to decrement from a preset burst _ len length. The register control unit 1008 receives the request req3 delayed by the delay unit 1006, generates a control signal ctrl4 to control the input terminal of the register 1007 to receive and output a preset burst _ len length, and the logic unit 1011 decrements the output of the register 1007 (the length value is decreased by 1) and feeds the decremented length value back to the input terminal of the register 1007, and outputs the decremented length value when the register control unit 1008 generates the control signal ctrl4 next time.

The second module includes a register control unit 1009, a register 1010, and a logic unit 1014 to increment from a preset address addr. The register control unit 1009 receives the request req3 delayed by the delay unit 1006, generates the control signal ctrl5 to control the input terminal of the register 1010 to receive the initial address addr0 and output the address addr, and the logic unit 1014 increments the output of the register 1010 (adds 1 to the address value) and feeds the incremented address value back to the input terminal of the register 1010, and outputs the incremented address value when the register control unit 1009 generates the control signal ctrl5 next time.

Meanwhile, the addr output terminal of the register 1010 is coupled to the input terminal of the register 1018, and outputs the registered address addr _ out when the register control unit 1003 outputs the control signal ctrl 2. And the read-write control circuit executes read/write operation under the instruction instr based on the obtained clock and address.

In a modified embodiment, the first module comprises an endpoint unit 1012, the first module being coupled with the endpoint unit 1012 via a handshake protocol. Similarly, the second module includes an endpoint unit 1013, the second module being coupled with the endpoint unit 1013 via a handshake protocol. The structure of the end point unit is shown in fig. 9.

In some embodiments, the read/write control circuit is coupled to the plurality of memory spaces, and can select at least one of the plurality of memory spaces to perform a read or write operation according to actual requirements.

In a modified embodiment, during writing operation, a demultiplexer is used for selecting one of a plurality of storage spaces and writing data in an address corresponding to the selected storage space; in a read operation, one of the memory spaces is selected by the multiplexer, and data is read from an address corresponding to the selected memory space.

In an exemplary embodiment, the read/write control circuit is coupled to the first and second memory spaces, and the address addr _ out of the read/write control circuit obtains the signal MEM1_ addr indicating the address of the first memory space or the signal MEM2_ addr indicating the address of the second memory space via the first demultiplexer demux1, as shown in fig. 10. Wherein the first or/and second memory space may be RAM, cache or Registers (Registers).

Meanwhile, the clock control signal ctrl3 or Clk _ ctrl gets the clock MEM1_ Clk controlling the first memory space or the clock MEM2_ Clk controlling the second memory space via the second demultiplexer demux 2.

In addition, during a write operation, the data segment in the instruction instr generates a signal MEM1_ wdata written in the first memory space or a signal MEM2_ wdata written in the second memory space via the third demultiplexer demux 3.

In a read operation, the data MEM1_ rdata read from the first memory space or the data MEM2_ rdata read from the second memory space is selected by the multiplexer mux1023, and then the read data RD _ data is output. And generating MOSI of the SPI slave to return to the host on the basis of the read data RD _ data.

In a modified embodiment, the clock control signals Clk _ ctrl and/or MEM1_ Clk, MEM1_ Clk required for the read operation and the write operation are generated later than the data signals (data segment, RD _ data, MEM1_ wdata, MEM2_ wdata, MEM1_ rdata, MEM2_ rdata in the instruction) and addresses (addr _ out, MEM2_ addr1, MEM1_ addr 2) required for the corresponding operations, so as to ensure that the required configuration information is stabilized during the read/write operation, which is beneficial to improving the signal quality and reducing the glitches.

In fig. 10, the

delays

1002, 1004, and 1006 are added to further delay the control signal generated by the control path to improve noise and stability, and in some embodiments, the delay elements may not be needed, as long as they ensure that the data transmitted by the data path is stable before the control signal transmitted by the control path arrives.

The SPI slave machine adopts the design idea of an asynchronous circuit, is different from the traditional synchronous SPI slave machine, and gives a corresponding clock control signal only when an event is triggered, namely read/write operation needs to be executed. Meanwhile, the asynchronous slave machine of the invention is provided with a standard interface and can be butted with any SPI host machine which conforms to a standard protocol, such as an asynchronous host machine or a synchronous host machine.

In a modified embodiment, the delay unit in the present invention is programmable, producing a programmable delay. Further, a delay in the data path is created based on the current state value of the state machine. Although additional delay in the control path can improve stability, too long a delay can increase the burden and affect the speed of the circuit, while longer a delay means more buffers (buffers) and waste area. In a preferred embodiment, the settling time between two stages of registers is used as the delay time of the delay unit.

The invention also relates to a method for communicating with an SPI master, comprising at least one slave. When any slave is activated, the activated slave receives an SPI clock and an MOSI signal from a host to generate an event and an instruction; updating a state of a state machine based on the event and the instruction; the state machine is used for controlling the activated slave machine to execute a function corresponding to the updated state; in a current state, a read operation or a write operation is performed based on the event and the instruction.

In a preferred embodiment, the activated slave receiving the SPI clock and MOSI signal from the master to generate the event and the command specifically includes: counting the negated SPI clock by using a travelling wave counter; comparing the count value of the travelling wave counter with the reference sequence to obtain a comparison value; performing AND operation on the comparison value and an SPI clock, and outputting an event; and the event is input into a clock end of the first register group, and controls to receive the MOSI and output an instruction.

In a preferred embodiment, updating the state of the state machine based on the event and the instruction specifically includes: the state machine includes a first data path that computes a next state of the state machine based on the instruction, and a first control path that generates a first control signal based on the event, and updates a current state of the state machine when the first control signal of the control path arrives at the stage.

In a preferred embodiment, the performing a read operation or a write operation based on the event and the instruction specifically includes: handshaking with a second control unit after the first request is generated based on the event, wherein the second control unit generates a second control signal; the second control unit handshakes with a third control unit, and the third control unit outputs a third control signal; the third control signal is a clock signal for a read or write operation; the third control unit handshakes with a cross-merge module, which outputs an address signal based on the instruction; the second control signal is coupled with a clock end of a third register and controls the third register to register the address signal; the read-write control circuit executes read or write operation based on the third control signal and the address registered by the third register.

Fig. 12 is a comparison of the area, power consumption and speed of the asynchronous slave and the synchronous slave according to the present invention, which is performed in the same design environment and simulation environment. The asynchronous slave machine and the synchronous slave machine are designed based on a 40nm process, the simulation time is 500us, the working clock frequency of the synchronous slave machine is 100MHz, and the performance of the asynchronous slave machine and the performance of the synchronous slave machine are compared under a scene with a large load (SRAM (random access memory), which is read and written repeatedly).

Under the same conditions: the SPI clock rate from the host is 6.25MHz, and compared with the SPI slave machine of the traditional synchronous circuit, the asynchronous SPI slave machine has almost the same area and only about 1/4 of the total power consumption.

Meanwhile, the speed of the asynchronous slave can reach 25MHz as fast as possible, namely the SPI clock range of the asynchronous slave is 0-25 MHz, while the speed of the synchronous slave is only 6.25MHz as fast as possible, and the SPI clock range of the synchronous slave is 0-6.25 MHz. Therefore, under the same design environment, simulation environment and process, the asynchronous slave can run faster, has a wider range and has stronger applicability.

The asynchronous circuit of the invention may use a four-phase bundled-data (four-phase bundled-data) handshake protocol, a two-phase bundled-data (two-phase bundled-data) handshake protocol, or the like, which is not limited in this respect. The invention is beneficial to representing the time sequence constraint of asynchronous circuit design by formalized time sequence constraint, and converts the timing constraint of a four-phase binding data handshake protocol or a two-phase binding data handshake protocol into SDC (synchronization design constraints) description in the synthesis stage so as to constrain the time sequence, the area and the power consumption of the circuit, thereby being capable of using the traditional commercial EDA to design the asynchronous circuit, and utilizing the advantages of EDA tools to improve the design efficiency. In a preferred embodiment, the asynchronous SPI slave of the present invention is designed based on RT constraints.

The asynchronous SPI slave machine can be used for any type of chip to reduce power consumption.

For example, the SPI slave machine has extremely low power consumption and is suitable for a brain-like chip. The pulse neural network is the third generation artificial intelligence, realizes reasoning with low power consumption, and the asynchronous circuit is very suitable for the realization of a brain-like chip (also called a neuromorphic chip). Due to the high difficulty of the asynchronous circuit, some teams (Qinghua, zhejiang and the like) mostly realize the brain-like chip through the synchronous circuit based on the clock, however, the biological brain does not have the concept of unified clock in reality, so the brain-like chip realized by the synchronous circuit is not bionic. The international mainstream teams (Intel, IBM, etc.) all use a more biomimetic event-driven asynchronous circuit design.

The asynchronous slave of the present invention may be manufactured using any process and is not limited to this example. Alternatively, the register or register group in the asynchronous slave of the present invention can be replaced by a latch or latch group, but the register stability is better and glitches are not easily generated compared to the latch.

While the present invention has been described with reference to particular features and embodiments thereof, various modifications, combinations, and substitutions may be made thereto without departing from the invention. The scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, and it is intended that the method, means, and method may be practiced in association with, inter-dependent on, inter-operative with, or after one or more other products, methods.

Therefore, the specification and drawings should be considered simply as a description of some embodiments of the technical solutions defined by the appended claims, and therefore the appended claims should be interpreted according to the principles of maximum reasonable interpretation and are intended to cover all modifications, variations, combinations, or equivalents within the scope of the disclosure as possible, while avoiding an unreasonable interpretation.

To achieve better technical results or for certain applications, a person skilled in the art may make further improvements on the technical solution based on the present invention. However, even if the partial improvement/design is inventive or/and advanced, the technical idea of the present invention is covered by the technical features defined in the claims, and the technical solution is also within the protection scope of the present invention.

Several technical features mentioned in the attached claims may be replaced by alternative technical features or the order of some technical processes, the order of materials organization may be recombined. Those skilled in the art can easily understand the alternative means, or change the sequence of the technical process and the material organization sequence, and then adopt substantially the same means to solve substantially the same technical problems to achieve substantially the same technical effects, so that even if the means or/and the sequence are explicitly defined in the claims, the modifications, changes and substitutions shall fall within the protection scope of the claims according to the equivalent principle.

The method steps or modules described in connection with the embodiments disclosed herein may be embodied in hardware, software, or a combination of both, and the steps and components of the embodiments have been described in a functional generic manner in the foregoing description for the sake of clarity in describing the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention as claimed.

Claims

1. An asynchronous SPI slave circuit, comprising:

the event driving generation module at least receives an SPI clock from the host and a host output slave input signal to generate an event and a command;

the state machine updates the state based on the event and the instruction; the state machine is used for controlling the event driving generation module and the read-write control circuit to execute operation corresponding to the state of the state machine;

and the read-write control circuit executes read operation or write operation based on the event and the instruction.

2. The asynchronous SPI slave circuit according to claim 1, wherein:

the event-driven generation module comprises an event generation unit and a first register set, wherein the first register set comprises at least one register;

the event generation unit includes: the asynchronous counter and the comparator are connected with the first AND gate;

the asynchronous counter counts the SPI clock after negation;

the comparator compares the count value of the asynchronous counter with a reference sequence;

the first AND gate is used for AND-operating the output of the comparator and the SPI clock and outputting an event;

and the first register group receives the input and output instruction of the host output slave machine based on the event.

3. The asynchronous SPI slave circuit according to claim 1, wherein said state machine comprises:

the first C unit receives the event and is coupled with the first register control unit through a handshake protocol; the first C unit is a state holding element, and the output state is kept unchanged when two inputs of the first C unit are different;

the first register control unit outputs a first control signal, and the first control signal is coupled with a clock end of the state conversion unit;

and the state transition unit is used for calculating the next state based on the instruction and performing state transition on the effective edge of the first control signal.

4. The asynchronous SPI slave circuit according to claim 3, characterized in that:

the state transition unit comprises combinational logic and a second register set, wherein the second register set comprises at least one register;

the input end of the combinational logic is coupled with the output end of the second register group, and the output end of the combinational logic is coupled with the input end of the second register group;

the combinational logic calculates a next state based on the instruction, and updates a current state of the second register set register at a valid edge of the first control signal.

5. The asynchronous SPI slave circuit according to claim 1, wherein said read-write control circuit comprises:

a second C unit receiving the event; the second C unit is a state holding element, and the output state is kept unchanged when the two inputs of the second C unit are different;

the second register control unit is coupled with the second C unit through a first handshake signal and outputs a second control signal;

the third register control unit is coupled with the second register control unit through a second handshake signal and outputs a third control signal; the third control signal is a clock signal for a read or write operation;

the cross merging module is coupled with the third register control unit through a third handshake signal and outputs an address signal based on the instruction;

a clock terminal of the third register is coupled with the second control signal, and the address signal is registered on the effective edge of the second control signal;

the read-write control circuit executes read-write operation based on the clock signal of the read-write operation and the address registered by the third register.

6. The asynchronous SPI slave circuit of claim 5, characterized in that:

the instruction comprises a reading-writing flag bit, a burst _ len and an initial address, wherein the burst _ len is used for indicating the length of continuous addresses of reading or writing operation;

the third handshake signals comprise a third request and a third acknowledgement signal;

the cross-merge module comprises a first module and a second module;

the first module and the second module are both coupled to a third request, an acknowledgement signal returned by the first module and an acknowledgement signal returned by the second module are respectively coupled to a first input terminal and a second input terminal of a third C unit, and the third C unit outputs a third acknowledgement signal;

in the latest state of the state machine, based on a third request, the first module decrements the burst _ len length of the instruction or/and the second module increments the start address of the instruction, wherein the incremented address is coupled to the input terminal of the third register.

7. The asynchronous SPI slave circuit of claim 6, characterized in that:

the cross-merge module further includes two endpoint units coupled to the first module and the second module, respectively, via a handshake protocol.

8. The asynchronous SPI slave circuit according to any one of claims 1 to 6, characterized in that:

a delay unit is added in a request path of the handshake to delay the request in the corresponding handshake path.

9. The asynchronous SPI slave circuit according to any one of claims 1 to 6, characterized in that:

the event driving generation module or/and the state machine or/and the read-write control circuit are asynchronous circuits.

10. The asynchronous SPI slave circuit according to claim 2, characterized in that:

the event generating unit also comprises a second AND gate, the input end of the second AND gate is connected with the chip selection signal and the SPI clock, and the output end of the second AND gate is connected with the input end of the traveling wave counter through a phase inverter.

11. The asynchronous SPI slave circuit according to claim 3, wherein:

the state machine includes an endpoint unit coupled to the first register control unit via a handshake protocol.

12. The asynchronous SPI slave circuit according to any one of claims 1 to 7, wherein:

the host is an asynchronous host or a synchronous host.

13. The asynchronous SPI slave circuit of claim 5, characterized in that:

and when the SPI is operated from the computer, selecting one of the storage spaces, and writing data into the corresponding address of the selected storage space or reading data from the corresponding address of the selected storage space based on the address signal and the clock signal of the reading or writing operation.

14. The asynchronous SPI slave circuit according to claim 8, wherein:

the delay unit is a programmable unit.

15. The asynchronous SPI slave circuit according to any one of claims 1 to 7, 10-11, 13, wherein:

the data at the input end of any register in the asynchronous SPI slave circuit is stabilized before the clock end signal of the register arrives.

16. An SPI communication method comprising at least one asynchronous slave, characterized by:

when any asynchronous slave is activated, the activated asynchronous slave receives an SPI clock from the host and a slave input signal output by the host to generate an event and an instruction;

updating a state of a state machine based on the event and the instruction; the state machine is used for controlling the activated slave machine to execute a function corresponding to the state of the state machine;

in a current state, a read operation or a write operation is performed based on the event and the instruction.

17. The SPI communication method according to claim 16, wherein said updating the state of the state machine based on said events and said instructions comprises:

the state machine includes a first data path that computes a next state of the state machine based on the instruction and a first control path that generates a first control signal based on the event;

updating a current state of the state machine based on the next state upon arrival of the first control signal.

18. The SPI communication method according to claim 16, wherein said performing a read or write operation based on said event and said instruction comprises:

generating a first request based on the event and then handshaking with a second control unit, wherein the second control unit generates a second control signal;

the second control unit handshakes with a third control unit, and the third control unit outputs a third control signal; the third control signal is a clock signal for a read or write operation;

the third control unit handshakes with a cross-merge module, which outputs an address signal based on the instruction;

the second control signal is coupled with a clock end of a third register and controls the third register to register the address signal;

and performing a read or write operation based on the third control signal and the address registered by the third register.

19. The SPI communication method according to claim 16, wherein the activated asynchronous slave receives an SPI clock from the master and a master output slave input signal to generate events and commands, comprising:

counting the negated SPI clock by utilizing a travelling wave counter;

comparing the count value of the travelling wave counter with the reference sequence to obtain a comparison value;

performing AND operation on the comparison value and an SPI clock, and outputting an event;

and the event is input into a clock end of the first register group, and controls the receiving host to output the input of the slave and output the instruction.

20. The SPI communication method according to claim 18, wherein:

the instruction comprises a read-write flag bit, a burst _ len and a starting address, wherein the burst _ len is used for indicating the length of a continuous address of a read or write operation.

21. The SPI communication method according to claim 18, wherein:

the slave communicates based on a four-phase handshake protocol or a two-phase handshake protocol.

22. The SPI communication method according to claim 20, characterized by:

a delay is added in the request path of the handshake to delay the request in the corresponding handshake path.

23. The SPI communication method according to claim 22, wherein:

the delay is a programmable delay.

24. The SPI communication method according to claim 18, wherein:

either register of the first and second register sets is replaced with a latch.

25. The SPI communication method according to any one of claims 16 to 24, characterized by:

the host is an asynchronous host or a synchronous host.

26. An interface, characterized by:

the interface comprises an asynchronous SPI slave circuit according to any one of claims 1 to 15 or uses an SPI communication method according to any one of claims 16 to 25.

27. A chip, characterized by:

the chip comprises an asynchronous SPI slave circuit according to any one of claims 1 to 15, or uses an SPI communication method according to any one of claims 16 to 25.