CN209690908U

CN209690908U - A kind of SPI serial ports based on FPGA turns the structure of the parallel port EBC

Info

Publication number: CN209690908U
Application number: CN201920896716.2U
Authority: CN
Inventors: 王果山; 刘洋; 王培培
Original assignee: Shandong Chaoyue CNC Electronics Co Ltd
Current assignee: Shandong Chaoyue CNC Electronics Co Ltd
Priority date: 2019-06-14
Filing date: 2019-06-14
Publication date: 2019-11-26
Anticipated expiration: 2029-06-14

Abstract

The utility model discloses a kind of, and the SPI serial ports based on FPGA turns the structure of the parallel port EBC, including FLASH chip, fpga chip and the TCM chip for reading the parallel port EBC, FLASH chip is equipped with the SPI serial ports of Quad IO read-write mode, SPI serial ports connects fpga chip, fpga chip is equipped with the FIFO buffer for storing change data, and FIFO buffer connects TCM chip by the parallel port EBC；The fpga chip of the utility model design is the control unit of core, improve the flexibility of system, realize conversion of the SPI serial ports to the parallel port EBC, pass through data buffer storage, the rate for substantially increasing read-write is able to achieve the output of different bit wide data by the flexible control of fpga chip, read-write protocol is completely customized, has very strong expansion.

Description

A kind of SPI serial ports based on FPGA turns the structure of the parallel port EBC

Technical field

The utility model relates to technical field of circuit design, and in particular to a kind of SPI serial ports based on FPGA turns the parallel port EBC Structure.

Background technique

Computer BIOS starting configuration file is generally all stored in onboard FLASH chip, and CPU needs to measure when booting Data in FLASH chip.Recently as the high speed development of computer technology, requirement of the people to speed is higher and higher, certain In a little situations, the speed that CPU measures BIOS data by way of common SPI serial ports is not able to satisfy the needs of system, needs to lead to The mode of serioparallel exchange is crossed, measurement rate is improved.It is designed using fpga chip and realizes the conversion of SPI serial ports to EBC parallel interface, With considerable flexibility and expansibility, the rate of TCM chip measurement BIOS can be greatly improved, there is preferable practical valence Value.

Utility model content

Aiming at the problems existing in the prior art, the purpose of this utility model is to provide a kind of, and the SPI based on FPGA goes here and there Mouth turns the structure of the parallel port EBC.

The technical scheme adopted by the utility model to solve the technical problem is as follows: a kind of SPI serial ports based on FPGA turns EBC The structure of parallel port, including the first chip, the second chip and the third chip for reading the parallel port EBC, first chip is equipped with Quad The SPI serial ports of read-write mode, SPI serial ports connect the second chip, and the second chip is equipped with the buffer for storing change data, delay Storage connects third chip by the parallel port EBC.

Particularly, serial line interface IO0, IO1, IO2, IO3 on first chip and the second chip two-way communication, the CS shift register pin and CLK clock pins and the second chip one-way communication on one chip, the first chip and third chip Two-way communication.

Particularly, the SPI serial ports uses standard Quad SPI communication agreement between the second chip and the first chip Serial line interface.

Particularly, the parallel port EBC between the second chip and third chip using customized EBC communication protocol and Line interface.

Particularly, first chip uses Quad SPI FLASH chip, and the Quad read-write mode of the first chip When for maximum 70MHz clock frequency, read and write rate 280MHz.

Particularly, second chip is field programmable gate array, and it is every that the second chip, which converts the parallel port EBC output data, 16 bytes of second, transfer rate are 4MB per second.

Particularly, second chip uses fpga chip, and third chip uses TCM chip.

Particularly, the buffer is FIFO buffer.

The utility model has the following beneficial effects:

The fpga chip of the utility model design is the control unit of core, improves the flexibility of system, realizes SPI Conversion of the serial ports to the parallel port EBC substantially increases the rate of read-write by data buffer storage, by the flexible control of fpga chip, It is able to achieve the output of different bit wide data, read-write protocol is completely customized, has very strong expansion.

Detailed description of the invention

Fig. 1 is the structural block diagram that the SPI serial ports based on FPGA turns the parallel port EBC.

Specific embodiment

Below with reference to the attached drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out Clearly and completely further details of explanation.Based on the embodiments of the present invention, those of ordinary skill in the art are not having Every other embodiment obtained under the premise of creative work is made, is fallen within the protection scope of the utility model.

Quad SPI mode: it can be divided into three categories: indirect pattern, status poll mode, Memory Mapping；Every three categories Mode is owned by signaling interface read-write protection mode, it can be divided into single SPI, double SPI, four SPI, SDR, DDR, double flash memories again；Its Middle indirect pattern is all to operate the Quad SPI register for being all, usually with this mode when to FLASH register configuration.

The abbreviation of FIFO:First Input First Output, First Input First Output, this is a kind of traditional sequentially to hold Row method, the instruction being introduced into first are completed and retire from office, and Article 2 instruction is and then just executed；It is a kind of data buffer storage of first in first out The difference of device, it and normal memory is that do not have exterior read-write address wire, uses so very simple, but disadvantage is exactly Data can be sequentially written in, data are sequentially read, data address adds 1 completion by inside read-write pointer automatically, cannot be as commonly depositing Reservoir can be determined to read or be written some specified address like that by address wire.

English abbreviation annotation in embodiment: FPGA- field programmable gate array；FLASH- memory；SPI- serial line interface Communication protocol；EBC- parallel interface communication protocol；TCM- safety chip；FIFO- buffer；Tetra- input and output of Quad IO- are serial Interface；Tetra- input and output serial interface communication agreement of Quad SPI-；IO0, IO1, IO2, IO3- serial communication interface.

As shown in Figure 1, a kind of SPI serial ports based on FPGA turns the structure of the parallel port EBC, including FLASH chip, fpga chip With the TCM chip for reading the parallel port EBC, FLASH chip is equipped with the SPI serial ports of Quad IO read-write mode, and SPI serial ports connects FPGA Chip, fpga chip are equipped with the FIFO buffer for storing change data, and FIFO buffer connects TCM core by the parallel port EBC Piece.

Serial line interface IO0, IO1, IO2, IO3 and fpga chip two-way communication in FLASH chip, in FLASH chip CS shift register pin and CLK clock pins and fpga chip one-way communication, fpga chip and TCM chip two-way communication.

SPI serial ports uses the serial line interface of standard Quad SPI communication agreement between fpga chip and FLASH chip； The parallel port EBC uses the parallel interface of customized EBC communication protocol between fpga chip and TCM chip；FLASH chip uses Quad SPI FLASH chip, and the Quad IO read-write mode of FLASH chip be maximum 70MHz clock frequency when, read and write rate For 280MHz；Fpga chip is field programmable gate array, and fpga chip converts the parallel port EBC output data as 16 byte per second, biography Transmission rate is 4MB per second.

Four road serial i O port communications modes of enabled FLASH chip, serial i O signal are pulled up by resistance, fpga chip By the data conversion of reading at the parallel data of customized bit wide, it is sent on piece FIFO buffer, TCM chip is waited to pass through EBC Parallel data is finally sent to TCM chip by the parallel port EBC by the enable signal that parallel port is read, fpga chip.

The utility model is not limited to above embodiment, anyone, which should learn, makes under the enlightenment of the utility model Structure change, it is all that there is same or similar technical solution with the utility model, each fall within the protection scope of the utility model Within.

Technology that the utility model is not described in detail, shape, construction portion are well-known technique.

Claims

1. the structure that a kind of SPI serial ports based on FPGA turns the parallel port EBC, it is characterised in that: including the first chip, the second chip and The third chip of the parallel port EBC is read, first chip is equipped with the SPI serial ports of Quad read-write mode, and SPI serial ports connects the second core Piece, the second chip are equipped with the buffer for storing change data, and buffer connects third chip by the parallel port EBC.

2. the structure that the SPI serial ports according to claim 1 based on FPGA turns the parallel port EBC, it is characterised in that: described first Serial line interface IO0, IO1, IO2, IO3 and the second chip two-way communication on chip, the CS shift register on the first chip draw Foot and CLK clock pins and the second chip one-way communication, the first chip and the two-way communication of third chip.

3. the structure that the SPI serial ports according to claim 1 based on FPGA turns the parallel port EBC, it is characterised in that: the SPI Serial ports uses the serial line interface of standard Quad SPI communication agreement between the second chip and the first chip.

4. the structure that the SPI serial ports according to claim 1 based on FPGA turns the parallel port EBC, it is characterised in that: the EBC Parallel port uses the parallel interface of customized EBC communication protocol between the second chip and third chip.

5. the structure that the SPI serial ports according to claim 1 based on FPGA turns the parallel port EBC, it is characterised in that: described first Chip use Quad SPI FLASH chip, and the Quad read-write mode of the first chip be maximum 70MHz clock frequency when, read and write Rate is 280MHz.

6. the structure that the SPI serial ports according to claim 1 based on FPGA turns the parallel port EBC, it is characterised in that: described second Chip is field programmable gate array, and it is 16 byte per second, transfer rate to be per second that the second chip, which converts the parallel port EBC output data, 4MB。

7. the structure that the SPI serial ports according to claim 1 based on FPGA turns the parallel port EBC, it is characterised in that: described second Chip uses fpga chip, and third chip uses TCM chip.

8. the structure that the SPI serial ports according to claim 1 based on FPGA turns the parallel port EBC, it is characterised in that: the caching Device is FIFO buffer.