WO2021089303A1

WO2021089303A1 - Protocol translator module system and method using said protocol translator module system

Info

Publication number: WO2021089303A1
Application number: PCT/EP2020/079235
Authority: WO
Inventors: Uwe Porst; Daniel Jakschik
Original assignee: Shenzhen GOODIX Technology Co., Ltd.
Priority date: 2019-11-05
Filing date: 2020-10-16
Publication date: 2021-05-14
Also published as: CN114641763A; CN114641763B

Abstract

The invention relates to a protocol translator module system and a method for an optimized translation between a common bus protocol and a SPI protocol using the protocol translator module system. The object to establish a high performance chip-internal bus protocol to SPI protocol translator module system which eliminates the disadvantages in the prior art will be solved by a protocol translator module system which is configured to translate a chip- internal bus read or write transfer to a corresponding SPI bus read or write transfer using a virtual address-map which is a result of an ADDR-signal of the protocol translator module system, wherein the protocol translator module system comprises at least a virtual address decoder configured to interpret the ADDR-signal of the chip-internal bus into slices which define SPI transfer parameters and a SPI state machine configured to manage SPI transfers according to selected SPI transfer parameters, whereas at least one slice of the ADDR-signal of 1-bit width defines an end of transfer, END, which de-assert a SS_N line after transfer if said END-bit is set, otherwise keep SS_N line asserted.

Description

Protocol translator module system and method using said protocol translator module system

The invention discloses a protocol translator module system and a method for an optimized translation between a common bus protocol and a SPI protocol using the protocol translator module system.

The Serial Peripheral Interface (SPI) (see "Serial peripheral interface," 2019. [Online]. Available: https://en.wikipedia.org/wiki/ Serial_Peripheral_Interface) is a standardized interface for data exchange between local devices. The standard configuration includes 4 lines:

'SCLK' Clock Line, driven by SPI master, consumed by SPI slave, 'MOSI Master-Out Slave-In, Data, driven by SPI master, consumed by SPI slave,

'MISO' Master-In Slave-Out, Data, driven by SPI slave, consumed by SPI master,

'SS N^f Slave-Select Not, Slave enable, driven by SPI master, consumed by SPI slave.

A Single Write SPI transfer is shown in figure 1. The master asserts SS_N, creates a given number of clock cycles on SCLK, sends the data bits on MOSI and de-asserts SS_N. Whenever SS N line is asserted data bit can be transferred. There are different implementation details:

'CPOL' Clock polarity, it defines whether the posedge or negedge of SCLK is evaluated as leading edge, 'CPHA' Clock phase, it defines whether the signal update and/or sampling is done on the leading or trailing edge .

Extended variants of the SPI protocol make use of more (2- Double, 4-Quad, 8-Oct) data lines, but use them bi directional in half-duplex mode. The data rate multiplies with the number of data lines. A Quad SPI transfer is depicted in figure 2. It starts with asserting SS_N and ends with de-asserting SS_N. Every data line transmits one bit per clock cycle. In case of 4 data lines, 32 bit are transmitted in 32/4 = 8 clock cycles.

Chip-internal components of a System-on-Chip (SoC) are typically linked via a standardized bus system, hence a chip-internal bus protocol (i.e. AHB - "Advanced microcontroller bus architecture," 2019. [Online].

Available : https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_A rchitecture or Wishbone - "Wishbone (computer bus)," 2019. [Online]. Available: https://en .wikipedia.org/wiki/Wishbone_ (computer_bus)).

There are various standards and implementations of chip- internal bus protocols. All of them have a common minimum set of signals. The name of the signals might vary from standard to standard, the functionality is similar. 'CLK' Clock Line, driven by a clock source,

'ADDR/ Address, vector of BUSAWID bits (i.e. 32), driven by bus master, consumed by bus slave,

WRITE Read-Write, selects between read or write transfer, driven by bus master, consumed by bus slave,

'TRANS' Transfer, signaling the beginning of a new bus operation, driven by bus master, consumed by bus slave,

WDATA Data To Write, vector of BUSDWID bits (i.e. 32), driven by bus master, consumed by bus slave,

'RDATA' Read Data, vector of BUSDWID bits (i.e. 32), driven by bus slave, consumed by bus master,

READY Ready, signaling the end of a bus operation, driven by bus slave, consumed by bus master.

Figure 3 depicts a single read transfer. The bus master applies ADDR, WRITE, TRANS and waits for READY to become high. Therewith the read data RDATA is valid.

Figure 4 depicts a single write transfer. The bus master applies ADDR, WRITE, TRANS, WDATA and waits for READY to become high.

The exact signal timing according to a chip-internal bus protocol varies from standard to standard. Next to the listed signals, there are the following important common facts:

- A transfer always includes an address and is a read or a write operation.

- Read operations transfer data from the slave to the master. - Write operations transfer data from the master to the slave.

- A transfer has a defined start, initiated by the bus master.

- A transfer has a defined end, defined/delayed by the bus slave.

- The most significant bits (MSBs) of the ADDR signal are used to select between slaves.

- The least significant bits (LSBs) of the ADDR signal are used within the slave according to their needs.

Some bus protocols also support transfer sizes different than the data width (BUSDWID). The minimum required transfer granularity for the present invention is BUSDWID.

A chip-internal bus infrastructure has the following attendees:

'Master' modules, which can initiate bus transfers,

'Slave' modules, which respond to bus transfers.

A master module can be i. e. a microcontroller or a Direct Memory Access (DMA) module. A slave module can be a memory which is a full matrix of words readable and/or writable or a register file which is a single vector or vectors of readable and/or writable flip- flops. These flip-flops control or observe hardware signals. These flip-flops are bus-accessible at one or multiple addresses. There are also other slave modules, i. e. a FLASH controller and so on.

Nearly every chip-internal microcontroller of a System-on- Chip (SoC) has a bus master interface, which initiates bus protocol compliant read and write transfers. The firmware just reads and writes an address.

A typical processor instruction set, requires two processor instructions for a read transfer: 1. Load address constant to processor register A

2. Load from address in processor register A, store read value to processor register B

Write transfers require three processor instructions: 1. Load address constant to processor register A

2. Load data constant to processor register B

3. Store content of processor register B at address of processor register A.

Multiple transfers always require an update instruction of the address register A, before the next load instruction or store instruction. In some cases, even more. There are multiple ways to mitigate these issues: bus burst transfers, processor pipelining, etc.

In burst mode transfers a device is transmitting data repeatedly without going through all the steps required to transmit each piece of data in a separate transaction. The usual reason for having a burst mode capability, or using burst mode, is to increase data throughput.

Processor pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps performed by different processor units with different parts of instructions processed in parallel. It allows faster CPU throughput than would otherwise be possible at a given clock rate, but may increase latency due to the added overhead of the pipelining process itself.

The main problem is that the chip-internal bus protocol of a SoC and the SPI protocol are quite different. Firmware, which wants to initiate SPI transfers via the chip-internal bus, needs to make use of a protocol translator module system (see figure 5). As the SPI protocol used on a SPI bus 6 between a SPI master 4 and a SPI slave 5 is standardized and is always the same, the chip-internal bus protocol used on an internal bus 7 of a SoC between chip-internal components can be quite different among different chip implementations .

For the communication between a chip-internal bus master to a SPI slave using a SPI protocol a protocol translator module system is necessary. Transfers are part of the processor program. Any translations between a chip-internal bus master to a SPI slave require a bunch of read and write transfers. Every bus read and write operation takes a bunch of clock cycles, limiting the maximum SPI transfer speed significantly.

It is therefore the object of the present invention to establish a high performance chip-internal bus protocol to SPI protocol translator module system which eliminates the named disadvantages in the prior art.

The object of the invention will be solved by a protocol translator module system which is configured to translate a chip-internal bus read or write transfer to a corresponding SPI bus read or write transfer using a virtual address-map which is a result of an ADDR-signal interpretation of the protocol translator module system, wherein the protocol translator module system comprises at least a virtual address decoder configured to interpret the ADDR-signal of the chip-internal bus into slices which define SPI transfer parameters and a SPI state machine configured to manage SPI transfers according to selected SPI transfer parameters, whereas at least one slice of the ADDR-signal of 1-bit width defines an end of transfer, END, which de-assert a SS_N line after transfer if said END-bit is set, otherwise keep SS_N line asserted.

The virtual addressing encodes/interpret the different SPI modes and SPI operations in an efficient way, resulting in a virtual address-map. Complex read and write transfer sequences with different modes are simply assembled by accessing specific addresses in the virtual address-map also called addressing window of the chip-internal bus. The protocol translator module system uses the LSBs of the ADDR- signal to distinguish different SPI interacting modes. The slices are extracted from the ADDR-signal at the beginning of every bus transfer by the virtual address decoder, which defines therewith the SPI transfer parameters.

The SPI state machine manages the SPI transfers according to the selected and extracted transfer parameters of the ADDR- signal. The slices derived from the ADDR-signal of the chip-internal bus correspond to a pre-defined (virtual) address-map. A bus master of the SoC can initiate SPI transfers to an external component of any length, whereas it is only necessary to finish a transfer by setting the END bit which de-asserts the SS_N line. All further operation modes of the SPI protocol are defined by the other slices of the ADDR-signal or are stored statically in a register file.

Another advantage of the inventive protocol translator module system is that the bus master of the SoC can write up to pre-defined number of BUSDWID bits on the SPI bus with one bus transfer and the bus master can read up to BUSDWID bits on the SPI bus also with only one bus transfer. Hence, the inventive protocol translator module system reduces the number of required microcontroller instructions and therewith program memory and execution time. As mentioned above, a bunch of transfers are needed if no protocol translator module system is used. So, it is the benefit of the invention that only one transfer is needed.

Due to the inventive protocol translator module system, all possible control combinations can be addressed with a very small hardware effort, so that a very large range can be covered. This makes it possible to use one and the same protocol translator module system for different, e. g. FLASH components. Due to the inventive protocol translator module system it is no longer necessary to use a plurality of protocol translator module systems, each of which performs the translation from a specific chip-internal bus protocol to SPI protocol.

In a variant of the inventive protocol translator module system, another slice of the ADDR-signal defines a SPI transfer data width (DWID), which specifies a number of data bits to be transferred via SPI. This slice has a width of a pre-defined constant b(BUSWID), whereas b(n) calculates a number of bits that is required to encode n different values. A value of 0 represents 1 bit that has to be transferred. A value of 31 specifies 32 bit as data width, if for example a 32-bit microprocessor of the SoC is used. This slice is optional, if only one transfer size between a chip-internal bus protocol and SPI protocol is needed. In another variant of the inventive protocol translator module system, another slice of the ADDR-signal defines a parallel mode (PMOD), which specifies a number of SPI bi directional data lines. This slice has a width of b (b (SPIDWID)), whereas b(n) calculates the number of bits that is required to encode n different values, b (n) is the rounding up of a log2 operation on n. For example, a value of 0 is equivalent to a single mode, which means for a 32- bit data width 32 bits are transferred using just one data line in 32 clock cycles. A value of 1 means double mode, whereas 32 bits are transferred over two data lines in 16 clock cycles, a value of 2 means quad mode, whereas 32 bits are transferred over four data lines in 8 clock cycles, and a value of 3 means octal mode, whereas 32 bits are transferred over eight data lines in 4 clock cycles.

In a further variant of the inventive protocol translator module system, another slice of the ADDR-signal defines a clock division factor (CLKDIV), which specifies the clock ratio of CLK of a chip-internal clock to SCLK of a SPI clock. This slice has a width of CLKDIVWID. For example, a value of 4 means that the SPI clock (SCLK) runs on a quarter of the chip-internal clock (CLK). This slice is optional and might be static in the register file. Different SPI devices support different maximum speeds, and also different commands / SPI sequences of the same device can support different speeds. For the inventive protocol translator module system speed switching is easy.

In another further variant of the inventive protocol translator module system, another slice of the ADDR-signal defines a slave select (SS_N), which specifies a number of SPI slaves, whereas each SPI slave has its own SS_N signal. This slice has a width of SPISSWID. Each bit selects one slave. Addressing multiple slaves at once is allowed. This slice is optional and should be skipped if only one SPI slave is present. This can be specified in a constant called SPISSWID, which is defined in a design-time of the protocol translator module system and explained later.

In a variant of the inventive protocol translator module system another slice of the ADDR-signal defines a pause {PAUSE), which ensures a pause between two SPI transfers for a given number of SPI clocks. This slice can be of any width. This slice is optional and might be static in the register file. Some rare devices need these kind of gaps.

In another variant of the inventive protocol translator module system another slice of the ADDR-signal defines a clock polarity (CPOL), which selects the clock-polarity SPI protocol implementation detail and has a 1-bit width. This slice is optional and might be static in the register file.

In a further variant of the inventive protocol translator module system another slice of the ADDR-signal defines a clock phase {CPHA), which selects the clock-phase SPI protocol implementation detail and has a 1-bit width. This slice is optional and might be static in the register file.

The slices and their combination of set or defined values for said slices define virtual address windows of a virtual address-map. Each of the addresses of the virtual address- map can be read or write via the chip-internal bus. The inventive protocol translator module system converts them to corresponding SPI read or write transfers. In a variant of the inventive protocol translator module system, the protocol translator system further comprises a bus data stage configured to capture or present write or read data from or to the chip-internal bus, a bus state machine configured to capture the chip-internal bus transfer and to control the bus data stage and to interact with the SPI state machine, a SPI clock generator configured to create the SCLK signal according to the selected CLKDIV and the SPI shift register configured to create or capture the SPI data signals for write or on read according to the selected transfer mode (PMODE), clock polarity (CPOL), and clock phase (CPHA).

The bus data stage captures write data from the chip- internal bus and presents read data to the chip-internal bus. The bus state machine captures the chip-internal bus transfers, generates bus protocol conform responses, controls the bus data stage and interacts with the SPI state machine. The SPI clock generator creates the SCLK signal according to the select CLKDIV. The SPI shift register creates the SPI data signals for write or captures the SPI data signals on read according to the selected transfer mode, clock polarity and clock phase. The SPI state machine manages the SPI transfers according to the selected transfer parameters, controls the SPI clock and the SPI shift register and creates the SS_N signals.

In a further variant of the inventive protocol translator module system, at design-time of the protocol translator module system following symbols are defined assuming a function b(n)= \log_2(ji)], which calculates a number of bits required to encode n different values: SPIDWID defining a maximum number of SPI bi-directional data lines, SPISSWID defining a number of SPI slaves, BUSDWID defining a chip- internal bus data width, BUSAWID defining a chip-internal bus address width and CLKDIVWID defining a clock division specifier which supports a clock division up to 2^CLKDIVWID-1.

It is necessary to define at design-time of the inventive protocol translator system some constants, whereas it is advantageous to assume a function b(n)= \log₂(ji)], which calculates the number of bits required to encode n different values. Necessary constants are SPIDWID which should be preferably a power of 2, SPISSWID, whereas every slave has its own SS_N signal, BUSDWID which should be preferably a multiple of 8, BUSAWID and CIKDIVWID.

The object will also be solved by a method for optimized protocol translation between a common chip-internal bus protocol running on a system-on-chip (SoC) and a SPI protocol running on an external component using the protocol translator module system according to the former claims, the method comprising the following steps for a read operation: transferring an ADDR-signal from the bus master to the virtual address decoder of the protocol translator module system and extracting the SPI transfer parameters which are provided to the SPI state machine; sampling MISO pins of the protocol translator module system as it is a read transfer; and copying a bus read value of the SPI shift register into the bus data stage when all bits are read and presenting the read value on the chip-internal bus on a RDATA line; finishing with a high-level on READY.

For a write operation the following steps have to be performed : transferring an ADDR-signal from the bus master to the virtual address decoder of the protocol translation module system and extracting the SPI transfer parameters which are provided to the SPI state machine; transferring a WDATA-signal through the bus data stage into the SPI shift register; and shifting out the data bits on MOSI pins of the protocol translator module system as it is a write transfer. The invention will be explained in more detail using exemplary embodiments.

The appended drawings show

Fig. 1 SPI Serial Interface - Single Write Transfer (prior art); Fig. 2 SPI Serial Interface - Quard Transfer (prior art); Fig. 3 Bus Read Transfer (prior art); Fig. 4 Bus Write Transfer (prior art); Fig. 5 Protocol Translation from chip-internal bus to SPI bus; Fig. 6 Block diagram of the inventive protocol translator module;

Fig. 7 ADDR-signal interpretation according to the invention;

Fig. 8 Virtual address-map windows according to the invention; Fig. 9 Protocol Translation - Word Read according to a first embodiment of the invention;

Fig. 10 Protocol Translation - Word Write according to a second embodiment of the invention; Fig. 11 Protocol Translation - Double Word Read Transfer according to a third embodiment of the invention;

Fig. 12 Protocol Translation - Consecutive Word Write Transfers with PM0DE=2 according to a fourth embodiment of the invention. Figure 6 shows a block diagram of the inventive protocol translator module system 1, especially as an example an AHB to SPI protocol translator module system using Virtual Address Windows. The protocol translator module system 1 comprises the following components: A Virtual Address Decoder 8 which splits the ADDR-signal into the slices of table 1 shown in figure 7 and defines therewith the SPI transfer parameter. The bus state machine 10 captures the chip-internal bus transfers, generates bus protocol conform responses, controls the bus data stage and interacts with the SPI state machine 9. The bus data stage 11 captures write data from the chip-internal bus and presents read data to the chip-internal bus. The SPI state machine 9 manages the SPI transfers according to the selected transfer parameters, controls the SPI clock and the SPI shift register 12 and creates the SS_N signals. The SPI clock generator 13 creates the SCLK signal according to the select CLKDIV and the SPI shift register creates the SPI data signals for write or captures the SPI data signals on read according to the selected transfer mode, clock polarity and clock phase.

An example address slicing of table 1 of figure 7 results in the example virtual address windows in table 2 shown in figure 8. The selected LSBs for the different slices is only an example. Every bit selection or mapping can be used. The order of slicing in table 1 of figure 7 is up to the implementation. Each of the addresses can be read or write via the chip-internal bus. The protocol translator module system 1 converts them to corresponding SPI read or write transfers. For instance, a chip-internal bus write on sub address OxOOFC will be translated to single 32-bit SPI write shown in figure 1. A chip-internal bus read or write on sub address window 0x0280-0x02FF will be translated to quad SPI read and write operation shown in figure 2.

Figure 9 details the protocol translation of a chip-internal bus read on sub address OxOOFC to a single 32-bit SPI read operation. The slices (see table 1 in figure 7) of the ADDR- signal define the SPI transfer details.

• ADDR [6:2] defines DWID to 31, therefore the SPI transfer size is 32 bit.

• ADDR[7] defines END to 1, therefore SS_N is set to 1 at the end.

• ADDR [9:8] defines PMODE to 0, therefore the transfer uses only one data line, here MISO.

• ADDR[13:10] defines CLKDIV to 0, therefore the SCLK is identical to CLK.

As it is a read transfer, the MISO pin is sampled and shifted into the bus read value. As soon as all 32-bits are read, the read value is presented on the chip-internal bus on RDATA, together with a high-level on READY. The first seven diagram lines of figure 9 represent the levels on the chip-internal bus and the last four diagram lines of figure 9 represent the levels on the SPI bus. The same applies to figures 10 to 12.

Figure 10 shows the corresponding chip-internal bus write, which is translated to a single 32-bit SPI write operation. The write data is presented on the MOSI pin and shifted out. The chip-internal bus signal READY stays at high-level, as the write data is just taken over. Therewith the chip- internal bus is freed-up and the bus master can continue on other tasks, while the protocol translator module system assembles the SPI write transfer.

The exact bus timing might vary from standard to standard. The SPI signal timing (clock polarity and/or clock phase) might vary also. In general:

• The slice DWID of ADDR defines the number of data bits to be transferred. If DWID is not a multiple of SPIDWID, unused bits are filled with 0. SCLK has \(DWID + 1)/ 2^pmode]clock cycles.

• The slice END of ADDR defines the value of SS_N at the end of the SPI transfer (clock 35 in figure 9).

• Leaving SS_N asserted (low) enables SPI-transfers wider than BUSDWID (clock 35 and following in figure 11). · A bus read operation is ended by the protocol translator module system via READY as soon as the last data bits have been sampled from MISO.

• A bus write operation does not insert any wait-cycles. READY is asserted immediately. A consecutive write operation inserts wait-cycles until the previous operation is completed (see figure 12).

The ADDR[7] slice END can be used to concatenate single chip-internal bus transfers to a larger SPI transfer. Figure 11 shows a 64-bit SPI read transfer. END is 0 in the first chip-internal bus transfer and 1 in the successive. The first chip-internal bus read operation reads the first 32 bit. The successive chip-internal bus read operation reads the next 32 bit. The END indicator can be used to assemble any SPI transfer length, independent of the maximum chip- internal bus transfer size. Figure 12 shows the concatenation of a 64-bit SPI write transfer. Additionally, this one runs in quad mode (PMODE=2).

The SPI protocol has a high variety in implementation. A generic SPI master should be compliant to all of them. Any not covered implementation detail can be integrated in the address decoding.

The bus master needs not to be a microcontroller. Any other bus master can make use of the protocol translation likewise.

Some bus protocols support different transfer sizes. The DWID slice may be derived directly from the transfer size. But this limits the transfer size to a subset — multiple of bytes typically. Some protocols support burst reads and writes. The END slice may be derived directly from the burst length. But this limits the transfer size to a subset. The burst length is often determined by hardware (i.e. cache structure) and is therefore hard to control in firmware. Protocol translator module system and method using said protocol translator module system

List of Reference Signs 1 Protocol translator module system

2 Bus master of the System-on-Chip

3 Bus slave of the System-on-Chip

4 SPI Master

5 SPI Slave 6 SPI bus using SPI protocol

7 Bus using chip-internal bus protocol

8 Virtual address decoder

9 SPI state machine

10 Bus state machine 11 Bus data stage

12 SPI Shift register

13 SPI clock generator

Claims

Claims 1.A protocol translator module system (1) which is configured to translate a chip-internal bus read or write transfer to a corresponding SPI bus read or write transfer using a virtual address-map which is a result of an ADDR-signal interpretation of the protocol translator module system (1), wherein the protocol translator module system (1) comprises at least a virtual address decoder (8) configured to interpret the ADDR-signal of the chip-internal bus (7) into slices which define SPI transfer parameters and a SPI state machine (9) configured to manage SPI transfers according to selected SPI transfer parameters, whereas at least one slice of the ADDR-signal of 1-bit width defines an end of transfer, END, which deassert SS_N line after transfer if said bit is set otherwise keep SS_N line asserted.

2. The protocol translator module system (1) according to claim 1, wherein another slice of the ADDR-signal defines a SPI transfer data width, DWID, which specifies a number of data bits to be transferred via SPI.

3. The protocol translator module system (1) according to claim 1, wherein another slice of the ADDR-signal defines a parallel mode, PMOD, which specifies a number of SPI bi-directional data lines.

4. The protocol translator module system (1) according to claim 1, wherein another slice of the ADDR-signal defines a clock division factor, CLKDIV, which specifies the clock ratio of CLK of the chip-internal clock to SCLK of the SPI clock.

5. The protocol translator module system (1) according to claim 1, wherein another slice of the ADDR-signal defines a slave select, SS, which specifies a number of SPI slaves (5), whereas each SPI slave (5) has its own SS_N signal.

6. The protocol translator module system (1) according to claim 1, wherein another slice of the ADDR-signal defines a pause, PAUSE, which ensures a pause between two SPI transfers for a given number of SPI clocks.

7. The protocol translator module system (1) according to claim 1, wherein another slice of the ADDR-signal defines a clock polarity, CPOL, which selects the clock-polarity SPI protocol implementation detail and has a 1-bit width.

8. The protocol translator module system (1) according to claim 1, wherein another slice of the ADDR-signal defines a clock phase, CPHA, which selects the clock- phase SPI protocol implementation detail and has a 1- bit width.

9. The protocol translator module system (1) according to one of the former claims, wherein the protocol translator system (1) further comprises a bus data stage (11) configured to capture or present write or read data from or to the chip-internal bus (7), a bus state machine (10) configured to capture the chip- internal bus transfer and to control the bus data stage (11) and to interact with the SPI state machine (9), a SPI clock generator configured to create the SCLK signal according to the select CLKDIV and the SPI shift register (12) configured to create or capture the SPI data signals for write or on read according to the selected transfer mode, PMODE, clock polarity, CPOL, and clock phase, CPHA.

10. The protocol translator module system (1) according to one of the former claims, wherein at design-time of the protocol translator module system (1) following symbols are defined assuming a function bin)= \log₂(n)], which calculates a number of bits required to encode n different values: SPIDWID defining a maximum number of SPI bi-directional data lines, SPISSWID defining a number of SPI slaves, BUSDWID defining a chip-internal bus data width, BUSAWID defining a chip-internal bus address width and CLKDIVWID defining a clock division specifier which supports a clock division up to 2^CLKDIVWID-1.

11. A method for optimized protocol translation between a common chip-internal bus protocol running on a system-on-chip, SoC, and a SPI protocol running on an external component using the protocol translator module system (1) according to the former claims, the method comprising the following steps for a read operation: transferring an ADDR-signal from the bus master (2) to the virtual address decoder (8) of the protocol translation module system (1) and extracting the SPI transfer parameters which are provided to the SPI state machine (9); sampling MISO pins of the protocol translator module system (1) as it is a read transfer; and - copying a bus read value of the SPI shift register

(12) into the bus data stage (11) when all bits are read and presenting the read value on the chip- internal bus (7) on a RDATA line; finishing with a high-level on READY. 12. A method for optimized protocol translation between a common chip-internal bus protocol running on a system-on- chip, SoC, and a SPI protocol running on an external component using the protocol translator module system (1) according to the former claims, the method comprising the following steps for a write operation:

- transferring an ADDR-signal from the bus master (2) to the virtual address decoder (8) of the protocol translation module system (1) and extracting the SPI transfer parameters which are provided to the SPI state machine (9);

- transferring a WDATA-signal through the bus data stage (11) into the SPI shift register (12); and shifting out the data bits on MOSI pins of the protocol translator module system (1) as it is a write transfer.