JP4160808B2 - Memory read / write control circuit, contactless memory card, read / write device, and contactless memory card read / write system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory read / write control circuit, a non-contact memory card, a read / write device, and a non-contact memory card read / write system suitable for large capacity and high-speed access.
[0002]
[Prior art]
A conventional contactless memory card has the following configuration. The card includes a power / clock coil for supplying power and a synchronous clock from the read / write device, and a read / write signal coil for inputting / outputting a read / write signal from the main device through the read / write device. The basic configuration includes a command coil for inputting a command from the main device through the read / write device.
[0003]
That is, when power and a synchronous clock are supplied to the contactless memory card through the power supply / clock coil, the card is energized to be operable. In this state, when the write command is input through the command coil, the write data similarly input through the write signal coil is recorded in the memory, while when the read command is input through the command coil, the memory is recorded. The recorded data is read out and output through a read signal coil (see, for example, Patent Publication 1).
[0004]
[Patent Publication 1]
Japanese Patent Laid-Open No. 62-8281 (FIG. 1)
[0005]
[Problems to be solved by the invention]
However, in the case of the conventional example, the following problems have been pointed out. First, since the power and the synchronous clock are supplied to the contactless memory card through one power source / clock coil, the circuit characteristics become unstable if the frequency of the synchronous clock is changed according to the type of memory as needed. Sometimes. Therefore, the frequency of the synchronous clock is set according to the memory with the slowest access speed, not the memory with the fastest access speed, and it is difficult to realize high-speed access in this respect.
[0006]
However, if read / write data and the like are input in parallel from the read / write device, it is possible to achieve high-speed access as much as it is not necessary to perform serial / parallel conversion in the memory card. Not only does this increase the data reliability, but the size and current consumption of the memory card increase, making it difficult to reduce the size and cost of the card.
[0007]
In addition, when a non-contact memory card is equipped with a flash memory whose access protocol is much more complicated than that of S-RAM, etc., when generating control signals at the time of address setting and data setting in the non-contact memory card, Since the apparatus is involved each time, it is very difficult to achieve high-speed access in this respect. On the other hand, when a CPU is mounted on a contactless memory card, high-speed access can be achieved, but power consumption increases, making it difficult to reduce the thickness and cost of the contactless memory card. Yes. In addition, a control program for changing the access protocol according to the type of memory is required, which also increases the cost.
[0008]
Furthermore, when transferring 1-byte data to the memory, the memory is accessed only once during one cycle period, and the other periods are a wait. This is also a major factor that hinders high-speed access.
[0009]
The present invention has been created under the above-described background, and its object is to provide a memory read / write control circuit, a contactless memory card, and a read / write device capable of solving the above-described problems. And a read / write system for a contactless memory card.
[0010]
[Means for Solving the Problems]
The memory read / write control circuit of the present invention has a register circuit for holding various data including at least the address, data and control data transferred from the main device, and based on the various data. For memory A control unit for performing control necessary for the read / write operation; A data output circuit that is connected to the subsequent stage of the register circuit and outputs data on the register circuit to a memory in response to an instruction from a control unit; The control unit comprises If the control data on the register circuit contains a code related to data fix selection, the data on the register circuit is set to be output to the memory, while the control data on the register circuit is selected for data change. When the code related to the data is included, the write data transferred from the main device without passing through the register circuit has a function of setting so that the memory is sequentially written to the memory. It is composed
[0011]
When various data and write data are transferred in a time-sharing manner from the main apparatus using a common line, the following read / write control circuit may be used. That is, it has a register circuit for holding various data including at least the address, data and control data transferred from the main device, and based on the various data For memory A control unit for performing control necessary for the read / write operation; Based on the select data provided in the previous stage of the register circuit and transferred separately from the various data from the main unit Various data transferred from the main unit The output destination from the register circuit to the memory A data input switching circuit; A data output circuit connected to a subsequent stage of the register circuit and receiving a command from the control unit and outputting data on the register circuit to a memory; The control unit comprises When the control data on the register circuit includes a code related to data fixing selection, the data on the register circuit is set to be output to the memory, while the control data on the register circuit changes data. When the code relating to the selection is included, the write data transferred from the main unit without passing through the register circuit has a function of setting to sequentially write to the memory. It has a configuration.
[0012]
Preferably, the controller is Write selection for control data on register circuit Concerning When a code is included, the memory is set to be written. When the control data on the register circuit includes a code related to read selection, the memory is read. Had the function to set It is desirable to use a configuration.
Further, it is preferable to provide an address output circuit that receives an instruction from the control unit, generates an address signal, and outputs the address signal to the memory. In this case, when the control data on the register circuit includes a code related to the address setting, the control unit sets the bit length of the address bus line between the address output circuit and the memory according to the setting. It has a configuration with a function to It is desirable to use one.
Further, the control unit can hold various data sequentially transferred from the main apparatus in n (n ≧ 1) register circuits 1, 2,... N, and based on the various data on the register circuit 1. Has a function of sequentially performing the control necessary for the read / write operation to the memory based on various data on the register circuit 2... N. Composition It is desirable to use what is present.
[0013]
Preferably, the controller is When the read / write operation is repeated It has a counter circuit that counts the number of read / write processes, and the control data on the register circuit is a code related to one-time processing. But Included When it is While the read / write operation performed based on the various data is performed only once, On the register circuit Code for continuous processing in control data But Included Is In some cases, it is desirable to use a configuration having a function of performing a read / write operation performed based on the various data as many times as the number of counts included in the various data.
[0014]
Preferably, the control unit includes a code related to the address set in the control data on the register circuit. But Including Rarely When you are Concerned For control data Included Address setting, selection of presence / absence of address mask, selection of number of address sets, selection of mask address, selection of presence / absence of transfer of data indicating memory attribute to main device, and selection of output of various control signals (CS Clock synchronization output / always output selection) The address set for the memory is set according to the control code, and when the control data on the register circuit includes a code related to the data set, it is included in the control data. Address setting, memory control setting, data change / fixed setting, selection of whether or not to output various control signals (including selection of CS clock synchronous output / always output), and R / B signal main unit Code for selecting whether or not to transfer Set the data set for the memory according to It is desirable to use a configuration having a function.
[0015]
Preferably, the type of memory to be used among the applicable memories is set and input. The switch outputs the setting result as a signal to the control unit Mode switching circuit and attribute input circuit that generates data indicating the memory attribute based on the memory type setting It is good to have. in this case, The control unit is a code related to the output of various control signals to the control data on the register circuit. But Including Rarely When the control signal to be output to the memory is activated, the code relating to the transfer of the data indicating the attribute of the memory to the control data to the main device is activated. But Including Rarely If it is, it is desirable to use one having a function of transferring data generated by the attribute input circuit to the main device.
[0016]
The control unit is a code related to the output of the spare control signal to the control data on the register circuit. But Including Rarely When it is, it is desirable to use a device having a function of activating the control signal to be output to the memory.
[0017]
The contactless memory card of the present invention includes a power supply coil for inputting power from a read / write device, a synchronous clock coil for inputting a synchronous clock from the read / write device, and a read / write device from the main device. A selection coil for inputting select data transferred through the serial device in a serial format, an input coil for inputting various data transferred from the main device through the read / write device in a serial format, and a read / write device. And an output coil for outputting read data to be transferred to the main device in a serial format.
[0018]
A read / write device of the present invention is a device connected to a main device and in which the contactless memory card is set, a power supply coil for supplying power to the contactless memory card, a contactless The synchronous clock coil for supplying the synchronous clock to the memory card and the select data transferred from the main unit Above Select coil for serial output to contactless memory card, output coil to output various data transferred from main device to contactless memory card in serial format, and main device from contactless memory card And an input coil for inputting at least the read data transferred to the terminal in a serial format.
[0019]
A contactless memory card read / write system according to the present invention includes the contactless memory card, the read / write device, and a main device connected to the read / write device. Select data for switching between a preprocessing stage for holding various data in the register circuit in the memory card and a main operation stage for performing preprocessing and read / write operations based on the various data held in the register circuit. It is transferred to the contactless memory card through the read / write device. Separately, various data is generated in the preprocessing stage and transferred to the contactless memory card through the read / write device. Read data is generated and transferred to a contactless memory card through a read / write device, while read And it has a configuration for inputting at least read data transferred from the non-contact memory card via the read / write device to.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a read / write system of a contactless memory card, FIG. 2 is an explanatory diagram showing a memory and its bus line applicable to the contactless memory card, and FIG. 3 is transferred from the main device to the contactless memory card. 4 is an explanatory diagram showing the contents of various types of data, FIG. 4 is an explanatory diagram showing the contents of controls 1 and 2 used for the type of memory shown in FIGS. 2B and 2C, and FIG. 5 is FIG. FIG. 6 to FIG. 17 are diagrams for explaining an example of the read / write operation of the read / write control circuit mounted on the contactless memory card. It is.
[0021]
The non-contact memory card read / write system shown here includes a main device 300, a read / write device 200, and a non-contact memory card 100 as shown in FIG. The contactless memory card 100 reads / writes data from / to the memory 130 mounted on the card 100 while being set in the read / write device 200. Such a read / write is controlled by the main device 300 interconnected to the read / write device 200 via the CPU bus 301.
[0022]
The main device 300 is a computer that reads / writes data from / to the contactless memory card 100 and performs predetermined processing as a whole, and has the following basic configuration. That is, in the stage of performing a data read / write operation on the contactless memory card 100 (referred to as this operation stage), write data is generated at the time of writing and the contactless memory card 100 is read through the read / write device 200. On the other hand, at the time of reading, read data transferred from the contactless memory card 100 through the read / write device 200 is input. As preparations before performing this operation stage, various data (details will be described later) including addresses, data, count numbers, and controls 1 and 2 (control data) are generated and contactless through the read / write device 200. The data is transferred to the memory card 100 and held in a register circuit 1221 described later (this stage is referred to as a preprocessing stage). In order to switch between the preprocessing stage and the main operation stage in the contactless memory card 100, select data is generated and transferred to the contactless memory card 100 through the read / write device 200 separately from various data. Yes.
[0023]
The read / write device 200 is a device that serves as an interface between the main device 300 and the contactless memory card 100 in a state where the contactless memory card 100 is set. In order to supply a synchronous clock and to transfer data to and from the contactless memory card 100, a total of five coils having a sheet shape or a coil shape are provided.
[0024]
That is, the read / write device 200 includes a power supply coil 201 for inputting power to the contactless memory card 100, a synchronization clock coil 202 for inputting a synchronization clock to the contactless memory card 100, and a main device. Select coil 203 for outputting select data transferred from 300 to contactless memory card 100 in a serial format and various data transferred from main device 300 to contactless memory card 100 in a serial format An output coil 204 and an input coil 205 for inputting read data transferred from the contactless memory card 100 toward the main device 300 in a serial format are provided.
[0025]
In addition to the coils 201 to 205, the following circuits are provided. That is, in order to supply power to the contactless memory card 100, the coil drive circuit 210 that pulses the power supply voltage and outputs it to the power supply coil 201, and generates a synchronization clock to be supplied to the contactless memory card 100 to generate the synchronization clock The timing circuit 220 for outputting to the coil 202 and the main device 300 are connected to the main device 300 through the CPU bus 301, and the on / off of the coil driving circuit 210 and the synchronous clock frequency of the timing circuit 220 are controlled according to the command output from the main device 300. A control circuit 230, a register circuit 250 that latches various data input from the main apparatus 300 through the CPU bus 301 and the data input switching circuit 240, and a select input from the main apparatus 300 through the CPU bus 301 and the data input switching circuit 240. Day Parallel / serial conversion circuit 260 for parallel / serial conversion and output to select coil 203, and parallel / serial conversion circuit for parallel / serial conversion of various data output from register circuit 250 and output to output coil 204 270 and a serial / parallel conversion circuit 280 that converts the read data or the like input through the input coil 205 to serial / parallel and outputs the data to the main device 300 via the CPU bus 301.
[0026]
In the read / write device 200 configured as described above, most of the circuits other than the coils 201 to 205 are formed by a gate array.
[0027]
On the other hand, the contactless memory card 100 includes a memory 130 and a read / write control circuit 120, and has a total of five sheets or coils corresponding to the coils 201 to 205 of the read / write device 200. A coil is provided. That is, the power supply coil 101 for inputting power from the read / write device 200, the synchronous clock coil 102 for inputting the synchronous clock from the read / write device 200, and the main device 300 through the read / write device 200. A selection coil 103 for inputting the transferred select data in a serial format, an input coil 104 for inputting various data transferred from the main device 300 through the read / write device 200 in a serial format, An output coil 105 is provided for outputting read data and the like to be transferred to the main device 300 through the write device 200 to the read / write device 200 in a serial format.
[0028]
The contactless memory card 100 includes the following circuits in addition to the memory 130, the read / write control circuit 120, and the coils 101 to 105. That is, a rectifier circuit 106 that generates a power supply voltage based on the output current of the power supply coil 101 and supplies power to each circuit, and a timing circuit 107 that supplies a synchronous clock input through the synchronous clock coil 102 to each circuit. A serial / parallel conversion circuit 108 that performs serial / parallel conversion on select data input through the select coil 103 and outputs it to the read / write control circuit 120; and various data input through the input coil 104 are serial / parallel. The serial / parallel conversion circuit 109 that converts and outputs to the read / write control circuit 120, and the parallel / serial that converts the read data and the like output from the read / write control circuit 120 into parallel / serial and outputs to the output coil 105 A conversion circuit 110 and the like are provided.
[0029]
In the read / write device 200 configured as described above, most of the circuits other than the coils 101 to 105 are formed by a gate array. Hereinafter, the configuration of the read / write control circuit 120 will be described in detail.
[0030]
The read / write control circuit 120 operates based on the selection data input through the selection coil 103 and the serial / parallel conversion circuit 108 and the various data input through the input coil 104 and the serial / parallel conversion circuit 109. Thus, the basic configuration for reading / writing data from / to the memory 130 is provided.
[0031]
The read / write control circuit 120 is provided in the preceding stage of the control unit 122 that performs a control necessary for the read / write operation based on various data, and the register circuit 1221 of the control unit 122, and receives various data from the main device 300. A circuit for switching the output destination of input data based on select data transferred separately, in which various data transferred from the main device 300 are stored in the register circuit 1221, and write data transferred from the main device 300 are stored in the memory 130. It has a data input switching circuit 121 for outputting each. In addition, a mode switching circuit 123, an address output circuit 124, a data output circuit 125, a control signal circuit 126, a general-purpose control signal circuit 127, a data input circuit 128, a general-purpose input circuit 129, an attribute input circuit 1231, and a data output switching circuit 1211 are provided. It has the composition that it has.
[0032]
The read / write control circuit 120 can be adapted to the three types of memories shown in FIG. FIG. 2A illustrates a type of memory in which an address bus and a data bus are shared and a special control signal is required. A typical example is a NAND flash memory. 2B and 2C are types of memory in which an address bus and a data bus are separated and a special control signal is unnecessary, and typical examples include a NOR flash memory and an S-RAM. However, for convenience of explanation, a NAND flash memory is shown as the memory 130 in FIG.
[0033]
Hereinafter, the detailed configuration of each circuit constituting the read / write control circuit 120 will be described.
[0034]
The data input switching circuit 121 is a select circuit that operates based on input select data. The data input switching circuit 121 distributes various input data to the register circuit 1221 and the memory 130 and outputs them. As a result, various data is output to the register circuit 1221 in the preprocessing stage, and write data is output to the memory 130 in the operation stage.
[0035]
The control unit 122 includes a plurality of register circuits 1221 that sequentially hold various types of input data, and a counter circuit 1222 that counts the number of read / write processes in the process of performing a read / write operation. The circuit configuration is such that an instruction is given to the address output circuit 124 and the like based on various data on the register circuit 1221 to control these circuits. Here, assuming that the various data 1 to 5 are sequentially input to the register circuit 1221 and the registers respectively holding the various data 1 to 5 are represented as registers 1 to 5 for convenience of explanation, the basics of the control unit 122 are described. The typical functions are as follows.
[0036]
That is, preprocessing for read / write operation is performed based on various data 1 on the register 1, and in this state, write data transferred from the main device 300 without passing through the register circuit 1221 is written to the memory 130 during writing. On the other hand, at the time of reading, data or the like recorded in the memory 130 is read and transferred to the main apparatus 300. Thus, preprocessing and read / write operations are performed based on the various data 1, and when this is completed, the preprocessing and read / write operations are sequentially performed in the same manner based on the various data 2-5 on the registers 2-5. To do. Then, by repeating such a series of processing (each processing based on various data 1 to 5), the memory 130 is continuously read / written.
[0037]
In other words, the control unit 122 can hold a plurality of various data in the register circuit 1221, and the preprocessing and the read / write operation are sequentially and repeatedly performed based on these various data. The same is true when there is only one piece of various data held in the register circuit 1221. Preprocessing and read / write operations based on the various data 1 held in the register 1 are performed, and then the same read / write operation is performed. The operation is repeated so that the memory 130 is continuously read / written.
[0038]
The various data transferred from the main apparatus 300 and held in the register circuit 1221 have the contents as shown in FIG. 3 and become a digital value of a total of 9 bytes composed of address, data, number of counters, and controls 1 and 2. Yes. The address indicates the setting of the first address when reading / writing is repeatedly performed on the memory 130. Data indicates the setting of the content of data to be written to the memory 130. The count number indicates the setting of the number of read / write processes. Control 1 selects address 24 or 32 bits (address setting), selection of presence / absence of attribute read (selection of presence / absence of transfer of data indicating memory attribute to main device), selection of continuous processing / single processing (continuous) Processing / one-time processing setting), data or address selection (address set / data set setting), data input or general-purpose port input selection (selection of presence / absence of transfer of read data to main device, R / B signal) Bit code group related to settings such as selection of whether or not data is transferred to the main device), data fixation or change selection (data change / fixed setting), write, read or write / read selection (memory control setting), etc. Is shown. Control 2 is general-purpose control signal control (selection of whether or not various control signals are output (including selection of CS clock synchronous output / always output), selection of counter 16 or 24 bits (setting of count bit length of counter circuit) The bit code group regarding the setting of is shown.
[0039]
As described above, when various data is held in the register circuit 1221, the contents of the preprocessing performed based on the various data, and thus the contents of the read / write operation, are determined. However, the contents of the controls 1 and 2 are partially different depending on the type of the memory 130.
[0040]
In the case where the controls 1 and 2 are the type of memory shown in FIG. 2B typified by a NOR type flash memory and the type of memory shown in FIG. The contents are as shown in. On the other hand, in the case of a memory of the type shown in FIG. 2A with a NAND flash memory as a representative example, the contents are as shown in FIG.
[0041]
In the case of the type of memory shown in FIG. 2 (A), unlike the type shown in FIGS. 2 (B) and 2 (C), the control 1 has a bit code relating to the setting of the address set / data set. Each bit code includes a bit code regarding each selection of whether or not various control signals are output (including selection of CS synchronous output / always output). In particular, when the control 1 includes a bit code related to the setting of the address set, that is, when the address set is set, the selection of the presence / absence of the address mask, the selection of the number of address sets, the selection of the mask address, and the main data indicating the memory attribute Each bit code related to the selection of whether or not to transfer to the device is included. On the other hand, when the control 1 includes a bit code related to data set setting, that is, at the time of data set setting, memory control setting, data change / fixed setting (during writing), transfer of read data to the main unit Selection of presence / absence of data (when reading), selection of presence / absence of transfer of R / B signal to main device (when reading), setting of continuous processing / single processing, and transfer of data indicating memory attributes to main device Each bit code related to presence / absence selection is included.
[0042]
Hereinafter, the configuration of the mode switching circuit 123 and the like will be described, and details of preprocessing performed by the control unit 122 will be described.
[0043]
The mode switching circuit 123 is a group of switches used to set and input the type of the memory 130 mounted on the contactless memory card 100, and outputs the setting result as a signal to the control unit 122. Yes.
[0044]
The address output circuit 124 is a circuit that receives an instruction from the control unit 122, generates an address signal, and outputs it to the memory 130. The following preprocessing is performed in relation to the circuit.
[0045]
The bit length of the address bus line between the address output circuit 124 and the memory 130 is set to 24 bits or 34 bits through the bit code regarding “selection of address 24 or 32 bits” of the control 1.
[0046]
A bit read / write operation for the memory 130 is performed once through the bit code related to “selection of one-time processing” of the control 1, and the address is set to increase by one after the processing is completed.
[0047]
Through the bit code relating to “selection of continuous processing” of the control 1, data read / write operation to the memory 130 is performed for the number of counts on the register circuit 1221, and in this process, the address is sequentially increased by the number of times. Is set as follows.
[0048]
The following preprocessing is performed only when the setting of the type of the memory 130 indicates the type of memory shown in FIG. That is, the address is set to be output to the memory 130 through the bit code regarding “address selection” of the control 1. In addition, the address set number is set to a 1/2/3 byte address through a bit code related to “selection of the number of address sets”. That is, when the control 1 includes a bit code related to “address selection”, the address on the register circuit 1221 is set to be written to the memory 130 by the number of address sets in units of 1 byte. Further, the presence / absence of an address mask is set through a bit code related to “selection of presence / absence of address mask”. The address to be masked is set to A10 / A9 / A8 through the bit code relating to “selection of mask address”.
[0049]
Note that the count bit length of the counter circuit 1222 is set through a bit code related to “selection of the counter 16 or 24 bits” of the control 2.
[0050]
The data output circuit 125 is a circuit that receives data from the control unit 122 and outputs data on the register circuit 1222 to the memory 130. The following preprocessing is performed in relation to the circuit.
[0051]
The data on the register circuit 1221 is set to be output to the memory 130 through the bit code related to “selection of data fixation” of the control 1. On the other hand, the write data transferred from the main device 300 without passing through the register circuit 1221 is set to be output to the memory 130 through the bit code related to “selection of data change”.
[0052]
The following preprocessing is performed only when the setting of the type of the memory 130 indicates the type of memory shown in FIG. That is, the data on the register circuit 1221 or the write data transferred from the main device 300 is set to be output to the memory 130 through the bit code related to “data selection” of the control 1.
[0053]
The control signal circuit 126 receives a command from the control unit 122 and generates control signals for CS (memory chip select), OE (output enable), and WE (memory write enable) that are essential for various types of memories. The circuit that outputs to the memory 130. The following preprocessing is performed in relation to the circuit.
[0054]
The CS and WE control signals are activated through the bit code relating to “write selection” of the control 1 so that the memory 130 is written. Through the “read selection”, the CS and OE control signals become active and the WE control signals become inactive, and the memory 130 is read. Through the “write / read selection”, the setting is such that writing and reading with respect to the memory 130 change every cycle period, and reading / writing is repeated.
[0055]
However, when the setting of the type of the memory 130 indicates a memory of the type shown in FIG. 2A, the bit code relating to “selection of CS clock synchronous output / always output” of control 2 for the CS control signal. Is pre-processed through. That is, the CS control signal is set to be active in synchronization with the synchronous clock (CLKP) through the bit code related to “selection of CS clock synchronous output”. On the other hand, the control signal of CS becomes active through the bit code related to “selection of CS always output”, and this state is set to be maintained.
[0056]
The general-purpose control signal circuit 127 is a circuit that receives a command from the control unit 122, generates special control signals such as ALE (memory address latch enable), CLE (memory command latch enable), and outputs the special control signals to the memory 130. The ALE and CLE control signals are necessary for the memory of the type shown in FIG. 2A, but a spare control signal is generated to make it adaptable to other types of memory. A function for outputting to the memory 130 is also included. That is, when a plurality of new bus lines are prepared in advance between the general-purpose control signal circuit 127 and the memory 130 and a new type of memory is used, a new control signal that needs to be output to the memory is sent to the bus line. Outputs above. The following preprocessing is performed in relation to the circuit.
[0057]
The general-purpose control signal circuit 127 can operate when the setting of the type of the memory 130 indicates a memory of the type shown in FIG. 2A, and relates to “selection of CLE control signal output” of the control 2 The CLE control signal is set to be active through the bit code. Similarly, the CLE control signal is set to be active through a bit code related to “selection of CLE control signal output”. Further, the spare control signal is set to be active through the bit code regarding “selection of spare control signal output”.
[0058]
The data input circuit 128 is a circuit that outputs read data read from the memory 130 to the data output switching circuit 1211.
[0059]
The general-purpose input circuit 129 is a circuit that outputs an R / B (ready / busy) signal output from the memory 130 to the data output switching circuit 1211.
[0060]
The attribute input circuit 1231 is a circuit that generates data indicating the attributes of the memory 130 (such as the type and capacity of the memory 130) based on the setting of the type of the memory 130 and outputs the data to the data output switching circuit 1211.
[0061]
The data output switching circuit 1211 receives each data output from the data input circuit 128, the general-purpose input circuit 129, and the attribute input circuit 1231, and selects these data in response to a command from the control unit 122. This is a circuit for outputting to the parallel / serial conversion circuit 110. The following preprocessing is performed in relation to the circuit.
[0062]
The output of the data input circuit 128 is selected by the data output switching circuit 1211 through the bit code relating to “selection of data input” of the control 1, and as a result, the read data read from the memory 130 is mainly transmitted through the read / write device 200. It is set to be transferred to the device 300.
[0063]
The output of the general-purpose input circuit 129 is selected by the data output switching circuit 1211 through the bit code relating to “selection of general-purpose port input” of the control 1, and as a result, the R / B signal of the memory 130 is transmitted through the read / write device 200 to the main device. 300 is set to be transferred. Similarly, the output of the attribute input circuit 1231 is selected by the data output switching circuit 1211 through the bit code related to “selection with attribute read”, and as a result, the data indicating the attribute of the memory passes through the read / write device 200 to the main device 300. Set to be forwarded to.
[0064]
Hereinafter, an example of the read / write operation of the read / write control circuit 120 configured as described above will be described with reference to FIGS.
[0065]
6 and 7 are diagrams showing an example of a write operation for the memory of the type shown in FIG. 2A with a NAND flash memory as a representative example. 6A shows the contents of various data on the register circuit 1221. FIG. 6B shows the contents of bit codes included in the controls 1 and 2 included in the various data. FIG. 7 shows reading based on the various data. / Timing charts of control signals and the like when the write control circuit 120 operates are shown.
[0066]
In the case of this write operation example, five kinds of data 1 to 5 are transferred from the main device 300 and held in the register circuit 1221 (registers 1 to 5).
[0067]
The addresses, data, and counts held on the register 1 are 12345678h, 80h (program command), and 0200h. Controls 1 and 2 include “address 32-bit selection”, “data selection”, “write selection”, “data fixed selection”, “CS constant output selection”, and “CLE output selection”. And so on.
[0068]
Therefore, the bit length of the address bus is set to 32 bits by the bit code related to “selection of 32-bit address”. The count bit length of the counter circuit 1222 is set to 16 bits by the bit code related to “selection of 16 bits of counter”. The bit code relating to “data selection” and “data fixed selection” is set to a state in which data on the register 1 is output to the memory 130. The CS control signal is activated by the bit code relating to “CS always output selection”, and this state is maintained thereafter. The CLE control signal is activated by the bit code related to “selection of CLE output”. The WE control signal is activated by the bit code relating to “selection of light”.
[0069]
As a result, 80h (program command) as data on the register 1 is written to the memory 130 (1-1 in FIG. 7). When such preprocessing and write operation based on the register 1 are completed, the processing shifts to processing based on the register 2.
[0070]
The address held on register 2 is 12345678h. Controls 1 and 2 include “address selection”, “selection with address mask”, “selection of number of address sets (3 bytes)”, “selection of mask address (A8)”, “selection of constant output of CS” ”And“ ALE output selection ”and the like are included.
[0071]
Therefore, the bit code related to “address selection” is set to a state in which the address on the register circuit 2 is output to the memory 130. The mask address is set to A8 by the bit code regarding “selection with address mask” and “selection of mask address (A8)”. The CS control signal is subsequently activated by the bit code relating to “CS always output selection”. The ALE and WE control signals are activated three times in succession by the bit code of “selection of ALE output” and “selection of number of address sets (3 bytes)”.
[0072]
As a result, 1Ah, 2Bh, and 78h masking 12345678h that is the address on the register 2 are sequentially written to the memory 130 (2-1 to 2-3 in FIG. 7), and the address 121A2B78h is set to the memory 130. . When such pre-processing and write operation based on the register 2 are completed, the process proceeds to processing based on the register 3.
[0073]
The count number held on the register 3 is 0200h. Controls 1 and 2 include bit code groups related to “data selection”, “write selection”, “data change selection”, “continuous processing selection”, “CS continuous output selection”, and the like. .
[0074]
Therefore, the bit code related to “data selection” and “data change selection” is set so that the write data transferred from the main device 300 without being passed through the register circuit 1221 is output to the memory 130. The CS control signal is subsequently activated by the bit code of “CS always output selection”. The WE control signal is activated once every cycle period by the bit code of “write selection” and “continuous processing selection”, and this is continued for the number of counts 0200h on the register 3, while in this process The address in the memory 130 is incremented sequentially.
[0075]
As a result, 512 pieces of write data transferred from the main device 300 are sequentially written from the addresses 121A2B78h to 121A2D77h of the memory 130 every cycle period (3-1 to 3-512 in FIG. 7). When such pre-processing and write operation based on the register 3 are completed, the process proceeds to processing based on the register 4.
[0076]
The data held on the register 4 is 10h (program command). Controls 1 and 2 include bit code groups related to "Data selection", "Write selection", "Data fixed selection", "CS constant output selection", "CLE output selection", etc. ing.
[0077]
Therefore, the bit code related to “data selection” and “data fixed selection” is set to a state in which data on the register 4 is output to the memory 130. The CS control signal is subsequently activated by the bit code relating to “CS always output selection”. The CLE control signal is activated by the bit code related to “selection of CLE output”. The WE control signal is activated by the bit code relating to “selection of light”.
[0078]
As a result, 10h (program command) as data on the register 4 is written to the memory 130 (4-1 in FIG. 7). When such pre-processing and write operation based on the register 4 are completed, the process proceeds to processing based on the register 5.
[0079]
Controls 1 and 2 held in the register 5 include bit codes related to “data selection”, “read selection”, “general port input selection”, “CS always output selection”, and the like. Yes.
[0080]
Therefore, the CS control signal is subsequently activated by the bit code relating to “CS always output selection”. The R / B signal of the memory 130 is sequentially sent to the main unit 300 every cycle period according to bit codes related to “data selection”, “read selection”, “selection of one-time processing”, and “selection of general-purpose port input”. Transferred.
[0081]
As a result, the R / B signal of the memory 130 is sequentially transferred to the main apparatus 300 through the general-purpose input circuit 129, the data output switching circuit 1211 and the like every cycle period (5-1 and 5-2 in FIG. 7). The R / B signal is in a busy state at the time indicated by 5-1 in FIG. 6C, but the R / B signal is at the time indicated by 5-2 in FIG. Since the state is changed to the ready state, the processing based on the register 5 is ended at this point.
[0082]
Thus, when the preprocessing and the read / write operation based on the registers 1 to 5 are finished, the first loop processing is finished. After that, the process again proceeds to the process based on the register 1, and the processes based on the registers 1 to 5 are sequentially performed in the same manner as described above. When the second loop processing is performed, the address of the memory 130 is not the address on the registers 1 to 5, but a value obtained by adding the count value of the counter circuit 1222 for counting the number of times of processing to this. Since such loop processing is repeatedly performed, as a result, the write data sequentially transferred from the main device 300 is written in order from the address 121A2B78h to the memory 130, and this write operation is continuously performed.
[0083]
FIG. 8 and FIG. 9 are diagrams showing an example of the read operation for the memory of the type shown in FIG. 2A with a NAND flash memory as a representative example. 8A shows the contents of various data on the register circuit 1221. FIG. 8B shows the contents of bit codes contained in the controls 1 and 2 contained in the various data. FIG. 9 shows reading based on the various data. / Timing charts of control signals and the like when the write control circuit 120 operates are shown.
[0084]
In the case of this read operation example, five various data 1 to 5 are transferred from the main device 300 and held in the register circuit 1221 (registers 1 to 5).
[0085]
The addresses, data, and counts held on the register 1 are 12345678h, 00h (program command), and 0200h. Controls 1 and 2 include “address 32-bit selection”, “data selection”, “write selection”, “data fixed selection”, “CS clock synchronous output selection”, “CLE output selection” ”And“ counter 16 bit selection ”and the like are included.
[0086]
Therefore, the bit length of the address bus is set to 32 bits by the bit code related to “selection of 32-bit address”. The count bit length of the counter circuit 1222 is set to 16 bits by the bit code related to “selection of 16 bits of counter”. The bit code relating to “data selection” and “data fixed selection” is set to a state in which data on the register 1 is output to the memory 130. The CS control signal becomes active in synchronization with the synchronous clock (CLKP) by the bit code relating to “selection of CS clock synchronous output”. The CLE control signal is activated by the bit code related to “selection of CLE output”. The WE control signal is activated by the bit code relating to “selection of light”.
[0087]
As a result, 00h (program command) as data on the register 1 is written to the memory 130 (1-1 in FIG. 9). When such preprocessing and write operation based on the register 1 are completed, the processing shifts to processing based on the register 2.
[0088]
The address held on register 2 is 12345678h. Controls 1 and 2 include “address selection”, “selection with address mask”, “selection of number of address sets (3 bytes)”, “selection of mask address (A8)”, “CS clock synchronous output” A bit code group related to “selection” and “selection of ALE output” is included.
[0089]
Therefore, the bit code relating to “address selection” is set so that the address on the register 2 is output to the memory 130. The mask address is set to A8 by the bit code regarding “selection with address mask” and “selection of mask address (A8)”. The CS control signal becomes active in synchronization with the synchronous clock (CLKP) by the bit code relating to “selection of CS clock synchronous output”. According to the bit code of “selection of ALE output” and “selection of number of address sets (3 bytes)”, the ALE control signal becomes active and the WE control signal becomes active three times in succession.
[0090]
As a result, 1Ah, 2Bh, and 78h masking 12345678h, which is the address on register 2, are sequentially written to memory 130 (2-1 to 2-3 in FIG. 9), and address 121A2B78h is set to memory 130. . When such pre-processing and write operation based on the register 2 are completed, the process proceeds to processing based on the register 3.
[0091]
Controls 1 and 2 held in the register 3 include bit code groups related to “data selection”, “read selection”, “general port input selection”, “CS clock synchronous output selection”, and the like. ing.
[0092]
Therefore, the CS control signal becomes active in synchronization with the synchronous clock by the bit code relating to “selection of CS clock synchronous output”. The bit code relating to “data selection”, “read selection”, and “general-purpose port input selection” is set so that the R / B signal of the memory 130 is sequentially transferred to the main device 300 every cycle period. .
[0093]
As a result, the R / B signal of the memory 130 is transferred to the main device 300 through the general-purpose input circuit 129, the data output switching circuit 1211, etc. (3-1 in FIG. 9). Since the R / B signal is ready at the time indicated by 3-1 in FIG. 9, the processing based on the register 3 ends at this time, and the processing based on the register 4 is started.
[0094]
The count number held on the register 4 is 0200h. Controls 1 and 2 include bit code groups related to “data selection”, “read selection”, “data change selection”, “continuous processing selection”, “CS constant output selection”, etc. Yes.
[0095]
Therefore, the read data of the memory 130 is set to a state to be transferred to the main device 300 by the bit code related to “data selection”, “data change selection”, and “read selection”. The CS control signal is activated by the bit code relating to “CS always output selection”, and this state is continued thereafter. The WE control signal is kept inactive by the “read selection” and “continuous processing selection” bit codes, while the OE control signal becomes active once every cycle period, and this is stored in the register 4. For the number of times of 0200h. In this process, the address in the memory 130 is sequentially incremented.
[0096]
As a result, the data recorded in the memory 130 is sequentially read from the address 121A2B78h to 121A2D77h for each cycle period (FIGS. 94-1 to 4-512), and the main device 300 through the data input circuit 128, the data output switching circuit 1211, and the like. Are sequentially transferred. When such pre-processing and read operation based on the register 4 are completed, the process proceeds to processing based on the register 5.
[0097]
Controls 1 and 2 held in the register 5 include bit codes related to “data selection”, “read selection”, “general port input selection”, “CS clock synchronous output selection”, and the like. ing.
[0098]
Therefore, the CS control signal becomes active in synchronization with the synchronous clock (CLKP) by the bit code relating to “selection of CS clock synchronous output”. The bit code relating to “data selection”, “read selection”, and “general-purpose port input selection” is set so that the R / B signal of the memory 130 is sequentially transferred to the main device 300 every cycle period. .
[0099]
As a result, the R / B signal of the memory 130 is sequentially transferred to the main apparatus 300 through the general-purpose input circuit 129, the data output switching circuit 1211, and the like every cycle period (5-1 and 5-2 in FIG. 9). The R / B signal is in the busy state at the time indicated by 5-1 in FIG. 9, but the R / B signal has changed to the ready state at the time indicated by 5-2 in FIG. At this time, the processing based on the register 5 is completed.
[0100]
Thus, when the preprocessing and the read / write operation based on the registers 1 to 5 are finished, the first loop processing is finished. Thereafter, the process again proceeds to the processing based on the register 1, and the processing based on the registers 1 to 5 is performed in the same manner as described above. When the second loop processing is performed, the address of the memory 130 is not the address on the registers 1 to 5, but the value obtained by adding the count value of the counter circuit 1222 for counting the number of processing times. Since the loop processing is repeatedly performed as described above, as a result, data recorded in the memory 130 is sequentially read from the address 12345678h and sequentially transferred to the main device 300, and this read operation is continuously performed.
[0101]
FIG. 10 and FIG. 11 are diagrams showing an example of byte write operation for the type of memory shown in FIG. 2B, with a NOR flash memory as a representative example. FIG. 10A shows the contents of various data on the register circuit 1221. FIG. 10B shows the contents of bit codes included in the controls 1 and 2 included in the various data. FIG. 11 shows reading based on the various data. / Timing charts of control signals and the like when the write control circuit 120 operates are shown.
[0102]
In the case of this byte write operation example, two kinds of data 1 and 2 are transferred from the main device 300 and held in the register circuit 1221 (registers 1 and 2).
[0103]
The addresses, data, and counts held on the register 1 are 12345678h, 40h (program command), and 0001h. Controls 1 and 2 include bit code groups related to “address 32-bit selection”, “write selection”, “data fixed selection”, “counter 16-bit selection”, and the like.
[0104]
Therefore, the bit length of the address bus is set to 32 bits by the bit code related to “selection of 32-bit address”. The count bit length of the counter circuit 1222 is set to 16 bits by the bit code related to “selection of 16 bits of counter”. The bit code relating to “selection of data fixed” is set so that the data on the register 1 is output to the memory 130. The CS and WE control signals are activated by the bit code relating to “selection of light”.
[0105]
As a result, 40h (program command) as data on the register 1 is written to the memory 130 (1-1 in FIG. 11). When such preprocessing and write operation based on the register 1 are completed, the processing shifts to processing based on the register 2.
[0106]
The addresses and count numbers held on the register 2 are 12345678h and 0001h. The controls 1 and 2 include bit code groups related to “selection of continuous processing”, “selection of data change”, “selection of write”, and the like.
[0107]
Therefore, the bit code related to “selection of data change” is set so that the write data transferred from the main device 300 without being passed through the register circuit 1221 is output to the memory 130. Although the CS and WE control signals are activated every cycle period by the bit codes of “write selection” and “continuous processing selection”, the count number on the register 3 is 0001h. The control signal is active only once, and the address of the memory 130 is only incremented by one.
[0108]
As a result, one write data transferred from the main device 300 is written to the address 12345678h of the memory 130 (2-1 in FIG. 11).
[0109]
When the preprocessing and the write operation based on the registers 1 and 2 are finished, the first loop processing is finished. Thereafter, the process again proceeds to the process based on the register 1, and the process based on the registers 1 and 2 is performed in the same manner as described above. When the second loop processing is performed, the address of the memory 130 is not the address on the registers 1 and 2, but a value obtained by adding the count value of the counter circuit 1222 for counting the number of times of processing to this. As a result, 40h (program command) and write data are recorded in the memory 130 by the second loop processing (1-2, 2-2 in FIG. 11), and the third, fourth, fifth,. 40h (program command) and write data are sequentially recorded (1-3, 2-3 in FIG. 11). That is, the write data is sequentially recorded from the address 12345678h of the memory 130, and this write operation is continuously performed.
[0110]
FIG. 12 and FIG. 13 are diagrams showing an example of page write operation for the type of memory shown in FIG. 2B, with a NOR flash memory as a representative example. 12A shows the contents of various data on the register circuit 1221. FIG. 12B shows the contents of bit codes included in the controls 1 and 2 included in the various data. FIG. 13 shows reading based on the various data. / Timing charts of control signals and the like when the write control circuit 120 operates are shown.
[0111]
In the case of this page write operation example, four kinds of data 1 to 4 are transferred from the main device 300 and held in the register circuit 1221 (registers 1 to 4).
[0112]
The address, data, and count number held on the register 1 are 12345678h, E8h (program command), and 0020h. Controls 1 and 2 include bit code groups relating to “address 32-bit selection”, “write selection”, “data fixed selection”, “counter 16-bit selection”, and the like.
[0113]
Therefore, the bit length of the address bus of the memory 130 is set to 32 bits by the bit code related to “selection of 32-bit address”. The count bit length of the counter circuit 1222 is set to 16 bits by the bit code related to “selection of 16 bits of counter”. The bit code relating to “selection of data fixed” is set so that the data on the register 1 is output to the memory 130. The CS and WE control signals are activated by the bit code relating to “selection of light”.
[0114]
As a result, E8h (program command), which is data on the register 1, is written to the memory 130 (1-1 in FIG. 13). When such preprocessing and write operation based on the register 1 are completed, the processing shifts to processing based on the register 2.
[0115]
The data held on the register 2 is 1Fh (data number 32 bytes). Controls 1 and 2 include a bit code group related to “selection of write” and “selection of data fixation”.
[0116]
Therefore, the bit code relating to “data fixed selection” is set to a state in which the data on the register 1 is output to the memory 130. The CS and WE control signals are activated by the bit code relating to “selection of light”.
[0117]
As a result, 1Fh (data count of 32 bytes), which is data on the register 1, is written to the memory 130 (2-1 in FIG. 13). When such pre-processing and write operation based on the register 2 are completed, the process proceeds to processing based on the register 3.
[0118]
Addresses and count numbers held on the register 3 are 12345678h and 0020h. Controls 1 and 2 include bit code groups relating to “selection of continuous processing”, “selection of data change”, “selection of write”, and the like.
[0119]
Therefore, the bit code related to “selection of data change” is set so that the write data transferred from the main device 300 without being passed through the register circuit 1221 is output to the memory 130. The CS and WE control signals are activated a total of 32 times per cycle period by the “write selection” and “continuous processing selection” bit codes. In this process, the address of the memory 130 is sequentially incremented.
[0120]
As a result, the 32 write data transferred from the main device 300 are sequentially written from the address 12345678h to 1234569h of the memory 130 (3-1 to 3-32 in FIG. 13). When such pre-processing and write operation based on the register 3 are completed, the process proceeds to processing based on the register 4.
[0121]
The data held on the register 4 is D0h (program command). Controls 1 and 2 include a bit code group related to “selection of write” and “selection of data fixation”.
[0122]
Therefore, the data on the register 4 is set to be output to the memory 130 by the bit code related to “data fixed selection”. The CS and WE control signals are activated by the bit code relating to “selection of light”.
[0123]
As a result, D0h (program command), which is data on the register 4, is written to the memory 130 (4-1 in FIG. 13), and the preprocessing and write operation based on the register 4 are completed at this point.
[0124]
In this way, when the preprocessing and the read / write operation based on the registers 1 to 4 are completed, the first loop processing is completed. Thereafter, the process again proceeds to the process based on the register 1, and the process based on the registers 1 to 4 is performed in the same manner as described above. When the second loop processing is performed, the address of the memory 130 is not the address on the registers 1 to 4, but a value obtained by adding the count value of the counter circuit 1222 that counts the number of times of processing to this. Since such a loop process is repeatedly performed, as a result, the write data transferred from the main device 300 is sequentially written in the memory 130 from the address 12345678h, and this write operation is continuously performed.
[0125]
14 and 15 are diagrams showing an example of a read operation for the type of memory shown in FIGS. 2B and 2C, in which a NOR flash memory is a representative example. 14A shows the contents of various data on the register circuit 1221. FIG. 14B shows the contents of bit codes contained in the controls 1 and 2 contained in the various data. FIG. 15 shows reading based on the various data. / Timing charts of control signals and the like when the write control circuit 120 operates are shown.
[0126]
In the case of this read operation example, one piece of various data 1 is transferred from the main device 300 and held in the register circuit 1221 (register 1).
[0127]
The addresses and count numbers held on the register 1 are 12345678h and 1234h. Controls 1 and 2 include bit code groups related to "32-bit address selection", "continuous processing selection", "data change selection", "read selection", "counter 16-bit selection", etc. Yes.
[0128]
Therefore, the bit length of the address bus of the memory 130 is set to 32 bits by the bit code related to “selection of 32-bit address”. The count bit length of the counter circuit 1222 is set to 16 bits by the bit code related to “selection of 16 bits of counter”. The bit code relating to “selection of data change” and “selection of read” is set so that the read data of the memory 130 is transferred to the main device 300. The WE control signal is maintained inactive by the “read selection” and “continuous processing selection” bit codes, while the CS and OE control signals become active once every cycle period. It continues for the number of counts 1234h above 1. In this process, the address of the memory 130 is sequentially incremented.
[0129]
As a result, the data recorded in the memory 130 is sequentially read from the address 12345678h every cycle period (1-1 to 1-6 in FIG. 15), and the main device through the data input circuit 128, the data output switching circuit 1211, and the like. 300 are sequentially transferred.
[0130]
When the preprocessing and the read operation based on the register 1 are completed, the first loop process is completed. Thereafter, the process again proceeds to the processing based on the register 1, and a similar read operation is performed. When the second loop processing is performed, the address of the memory 130 is not the address on the register 1 but a value obtained by adding the count value of the counter circuit 1222 for counting the number of times of processing to this. Since such loop processing is repeatedly performed, as a result, data recorded in the memory 130 is sequentially read from the address 12345678h every cycle period, and this read operation is continuously performed.
[0131]
FIG. 16 and FIG. 17 are diagrams showing an example of the write operation for the memory of the type shown in FIG. 16A shows the contents of various data on the register circuit 1221. FIG. 16B shows the contents of bit codes included in the controls 1 and 2 included in the various data. FIG. / Timing charts of control signals and the like when the write control circuit 120 operates are shown.
[0132]
In the case of this write operation example, one piece of various data 1 is transferred from the main device 300 and held in the register circuit 1221 (register 1).
[0133]
The addresses and count numbers held on the register 1 are 12345678h and 1234h. Controls 1 and 2 include bit code groups related to “32-bit address selection”, “continuous processing selection”, “data change selection”, “write selection”, “counter 16-bit selection”, etc. Yes.
[0134]
Therefore, the bit length of the address bus of the memory 130 is set to 32 bits by the bit code related to “selection of 32-bit address”. The count bit length of the counter circuit 1222 is set to 16 bits by the bit code related to “selection of 16 bits of counter”. The bit code relating to “selection of data change” and “selection of write” is set so that the write data transferred from the main device 300 is written to the memory 130. The CS and WE control signals are activated once every cycle period by the “write selection” and “continuous processing selection” bit codes, and this is continued for the number of counts 1234h on the register 1. In this process, the address of the memory 130 is sequentially incremented.
[0135]
As a result, the write data transferred from the main device 300 is sequentially written into the memory 130 from the address 12345678h every cycle period (1-1 to 1-6 in FIG. 17).
[0136]
When such preprocessing and write operation based on the register 1 are completed, the first loop processing is completed. Thereafter, the process again proceeds to the processing based on the register 1, and a similar write operation is performed. When the second loop processing is performed, the address of the memory 130 is not the address on the register 1 but a value obtained by adding the count value of the counter circuit 1222 for counting the number of times of processing to this. Since such loop processing is repeatedly performed, as a result, the write data transferred from the main device 300 is sequentially written to the memory 130 from the address 12345678h every cycle period, and this write operation is continuously performed.
[0137]
Note that for a read operation example of the type of memory shown in FIG. 2C using S-RAM as a representative example, FIG. 2B showing the NOR flash memory shown in FIG. 14 and FIG. 15 as a representative example. The description of the type of memory shown in FIG.
[0138]
The basic operation of the contactless memory card read / write system configured as described above will be described below.
[0139]
First, when the contactless memory card 100 is set in the read / write device 200, the coils 201 to 205 of the read / write device 200 and the coils 101 to 105 of the contactless memory card 100 face each other. At the same time, the read / write device 200 operates according to a command output from the main device 300. Along with this, the power supply voltage and the synchronous clock generated by the read / write device 200 are supplied to the contactless memory card 100, and the card enters an operating state.
[0140]
The main device 300 transfers various data having a bit code related to “selection with attribute read” to the contactless memory card 100 in order to prepare for reading / writing data to the contactless memory card 100. . When transferring this control data, separately from this transfer, select data is transferred to the contactless memory card 100 so that various data are held in the register circuit 1221. Then, data indicating the attribute of the memory generated by the attribute input circuit 1231 is transferred to the main device 300 through the data output replacement circuit 1211 or the like by the bit code related to “selection with attribute read”.
[0141]
If the current synchronous clock frequency is not optimal for the memory 130 mounted on the contactless memory card 100 as judged from the data indicating the memory attribute, the read / write device 200 is informed of the synchronous clock. Issue a command to change the frequency. Then, the frequency of the synchronous clock supplied to the contactless memory card 100 changes, and as a result, the frequency of the synchronous clock supplied to the contactless memory card 100 is optimized.
[0142]
Further, since the type of the memory 130 mounted on the contactless memory card 100 can be determined from the data of the memory attribute, in the pre-processing stage, it matches with the type of the memory and the original read / write is performed. Various data is generated and transferred to the contactless memory card 100. In this operation stage, while maintaining the synchronization with the contactless memory card 100, the write data is transferred at the time of writing, while read from the memory 130 at the time of reading. Input the read data. In the pre-processing stage, select data for transferring various data to the register circuit 1221 of the contactless memory card 100 is transferred. On the other hand, in this operation stage, write data / read data is exchanged with the contactless memory card 100. The select data for mutual transfer is transferred.
[0143]
As described above, the read / write control circuit 120 of the contactless memory card 100 performs the read / write on the memory 130 based on various data held on the register circuit 1221. Further, since the contents of the controls 1 and 2 can be switched through the setting of the mode switching circuit 123, it becomes possible to adapt to any type of memory 130 shown in FIG. ing.
[0144]
In particular, by combining various data on the register circuit 1221, processing that has been simple but has required a lot of time in the past, for example, writing and reading fixed data, writing a count number with fixed data, for the same address Processing such as setting a plurality of program commands or control data can be easily performed. It is also possible to easily perform address setting, data setting, etc. for a NAND flash memory that uses an address bus and a data bus separately.
[0145]
In the case of the non-contact memory card read / write system configured as described above, when various data is transferred from the main device 300 to the non-contact memory card 100, preprocessing on the read / write operation is performed based on the various data. To do. Therefore, the address, data, control signal and / or memory control given to the memory 130 can be arbitrarily set or changed, and the memory 130 can be accessed a plurality of times within one cycle period. Become. In addition, for a NOR type flash memory that needs to be provided with a program command, it is also possible to arbitrarily set the method of giving the program command.
[0146]
According to the conventional example, when transferring 1-byte data to the flash memory, the actual access to the memory is only 4 clock periods during the 16 clock period, and the subsequent 12 clock periods are a wait. On the other hand, according to the proposed system, processing can be performed even during the wait period, and high-speed access can be realized. In addition, since it is possible to perform processing that has conventionally required a lot of time with simple contents in a short time, a large speed access can be realized in this respect.
[0147]
In the case of the conventional example, when a non-contact memory card is equipped with a flash memory whose access protocol is much more complicated than S-RAM, the main device needs to perform processing necessary for access to the memory each time. Therefore, it has been very difficult to achieve high-speed access in this respect. On the other hand, according to the proposed system, the main device 300 does not need to perform processing necessary for access to the memory 130 each time. This is because the main device 300 only transfers various data, and the pre-processing for the read / write operation is performed in the contactless memory card 100, and then the write data is transferred at the time of writing and the read data is input at the time of reading. Because you only need to do it. In this respect, high speed access can be realized. Further, since the CPU is not mounted on the contactless memory card 100, power consumption is small, and the contactless memory card can be reduced in thickness and cost. In addition, while being adaptable to various types of memories, a control program for changing the access protocol is unnecessary, and in this respect as well, the cost can be reduced.
[0148]
Furthermore, since power and a synchronous clock are separately supplied from the read / write device 200 to the contactless memory card 100, even if the frequency of the synchronous clock is changed according to the type of the memory 130 as needed, The power supply voltage supplied to the contactless memory card 100 does not change, and the circuit characteristics do not become unstable. Therefore, it becomes possible to change the frequency of the synchronous clock in accordance with the type of the memory 130 mounted on the contactless memory card 100 and set the access speed to the maximum, and high speed access is realized in this respect. Conventionally, the access speed is about 500 Kbps to about 1 Mbps, but in the case of the proposed system, high-speed access of about 5 Mbps can be realized.
[0149]
In addition, the synchronous clock coil 102 etc However, since data transmission / reception between the read / write device 200 and the contactless memory card 100 is performed in a serial format, the contactless memory card is compared with the case of inputting in parallel. The size and current consumption of 100 do not increase, and the contactless memory card 100 can be reduced in thickness and cost, including that the CPU is not mounted on the contactless memory card 100.
[0150]
Note that the memory read / write control circuit according to the present invention is not limited to the application of a contactless memory card, and can be similarly applied to a circuit incorporating a memory such as a microcomputer. That is, preprocessing for read / write operation is performed based on various data on the register circuit, and in this state, the write data transferred from the main unit is sequentially written to the memory without passing through the register circuit. At the time of reading, as long as it has a function of sequentially reading the data recorded in the memory and transferring it to the main device, the type of various data, the contents of preprocessing, the configuration of the circuit, the type of memory, etc. are not questioned.
[0151]
The contactless memory card according to the present invention is not limited to the above embodiment. That is, the read / write control circuit is mounted, and the power supply coil for inputting power from the read / write device and the synchronous clock coil for inputting the synchronous clock from the read / write device are separately provided. The select data transferred from the main device through the read / write device is input in a serial format through the select coil, and various data other than the select data transferred from the main device through the read / write device is serialized through the input coil. As long as the read data to be output to the main device through the read / write device is output in serial form through the output coil, the configuration of the peripheral circuit of the coil is not questioned.
[0152]
The same applies to the read / write device according to the present invention. That is, a device that is connected to the main device and in which the contactless memory card is set, the power supply coil for supplying power from the read / write device to the contactless memory card, and the read / write device. The synchronous clock coil for supplying the synchronous clock to the contactless memory card is separated, and the select data transferred from the main unit is output in serial form through the select coil, and the select transferred from the main unit As long as various data other than data are output in serial form through the output coil, and read data output from the contactless memory card to the main unit is input through the input coil, the peripheral circuit of the coil It does not matter about the configuration.
[0153]
The same applies to the read / write system of the contactless memory card according to the present invention. That is, any configuration may be used as long as the main device, the read / write device, and the contactless memory card are provided. In particular, the main device switches between a preprocessing stage in which various data is held in the register circuit in the contactless memory card and a main operation stage in which preprocessing and read / write operations are performed based on the various data held in the register circuit. In addition to this, select data is generated and transferred to the contactless memory card through the read / write device. Separately, in the preprocessing stage, various data is generated and transferred to the contactless memory card through the read / write device. In this operation stage, the write data required for writing is generated and transferred to the contactless memory card through the read / write device, while at least the read data transferred from the contactless memory card through the read / write device is input at the time of reading. As long as you have .
[0154]
【The invention's effect】
As described above, in the case of the memory read / write control circuit according to the first, second, third, fourth, or fifth aspect of the present invention, the preprocessing on the read / write operation is performed only by transferring various data from the main device In this state, the data transferred from the main device is sequentially written to the memory, while the data recorded in the memory is sequentially read and transferred to the main device, so the read / write operation is repeated. At this time, the proportion of the main apparatus involved is smaller than that of the conventional apparatus. Further, when a flash memory is used, it is possible to perform a plurality of accesses within one cycle period, and accordingly, it becomes possible to perform a read / write operation during a period of a conventional wait. . Furthermore, by combining a plurality of various data and sequentially performing preprocessing and read / write operations, not only can a flash memory with a complicated access protocol be easily handled, but also a simple Although it is the content, the processing which has conventionally required a great amount of time can be performed very easily and in a short time. As a result, significant high speed access is realized.
[0155]
In the case of the memory read / write control circuit according to claim 6 of the present invention, in addition to the configuration of claim 1, the address set for the memory is performed only by transferring various data from the main unit. Even with a NAND flash memory or the like, significant high-speed access can be realized.
[0156]
In the memory read / write control circuit according to the seventh aspect of the present invention, in addition to the configuration of the first aspect, various control signals are generated only by transferring various data from the main unit. Many types of memory can be adapted. In addition, since the data indicating the memory attribute is transferred to the main device simply by transferring various data from the main device, the main device can quickly recognize the memory attribute. It becomes possible to achieve higher speed access.
[0157]
In the memory read / write control circuit according to claim 8 of the present invention, in addition to the configuration of claim 7, the configuration is such that a spare control signal is generated only by transferring various data from the main unit. Therefore, even if a new type of memory is developed, if only the type of control signal is different from that of the conventional memory, the new type of memory can also be adapted, and it is possible to improve performance in this respect. Become.
[0158]
In the case of the contactless memory card according to claim 9 of the present invention, since the memory read / write control circuit according to claims 1 to 8 is mounted, the advantages of claims 1 to 8 are achieved. In particular, even when a flash memory having a complicated access protocol is used, it is not necessary to use a CPU unlike the conventional case. Therefore, power consumption is reduced, and in this respect, it is possible to reduce the thickness and cost of the card. In addition, since the power and the synchronous clock are separately supplied from the read / write device, the circuit characteristics do not become unstable even if the frequency of the synchronous clock is changed. Therefore, it becomes possible to change the frequency of the synchronous clock in accordance with the type of memory and set the access speed to the maximum, and also in this respect, high speed access is realized.
[0159]
In the case of the read / write device according to the tenth aspect of the present invention, since it is configured to be used in combination with the contactless memory card according to the eighth aspect, the same advantages as in the eighth aspect are obtained.
[0160]
According to the non-contact memory card read / write system of the eleventh aspect of the present invention, the non-contact memory card has the non-contact memory card of the ninth aspect, the read / write device of the tenth aspect, and the main apparatus. The same advantages as those of the ninth aspect are obtained.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an embodiment of the present invention, and is a block diagram of a read / write system for a contactless memory card.
FIG. 2 is an explanatory diagram showing a memory applicable to a contactless memory card and its bus line.
FIG. 3 is an explanatory diagram showing the contents of various data transferred from the main device to the contactless memory card.
4 is an explanatory diagram showing the contents of controls 1 and 2 used for the type of memory shown in FIGS. 2B and 2C. FIG.
FIG. 5 is an explanatory diagram showing the contents of controls 1 and 2 used for the type of memory shown in FIG.
6 is a diagram showing an example of a write operation for the memory of the type shown in FIG. 2A, where FIG. 6A is the contents of various data on the register circuit, and FIG. 6B is included in the various data. It is a figure which shows each the content of the bit code contained in control.
7 is a diagram showing an example of a write operation for a memory of the type shown in FIG. 2A, and is a control when a read / write control circuit is operated based on various data shown in FIG. 6A. It is a figure which shows timing charts, such as a signal.
8 is a diagram showing an example of a read operation for the type of memory shown in FIG. 2 (A), where (A) is the contents of various data on the register circuit, and (B) is included in the various data. It is a figure which shows each the content of the bit code contained in control.
9 is a diagram showing an example of a read operation for the type of memory shown in FIG. 2A, and is a control when the read / write control circuit is operated based on various data shown in FIG. 8A. It is a figure which shows timing charts, such as a signal.
10A and 10B are diagrams showing examples of byte write operations for the type of memory shown in FIG. 2B, where FIG. 10A shows the contents of various data on the register circuit, and FIG. It is a figure which shows each the content of the bit code contained in the control to be performed.
11 is a diagram showing an example of a byte write operation for the type of memory shown in FIG. 2B, and is a control when the read / write control circuit is operated based on various data shown in FIG. It is a figure which shows timing charts, such as a signal.
FIGS. 12A and 12B are diagrams showing an example of a page write operation for a memory of the type shown in FIG. 2B, where FIG. 12A shows the contents of various data on the register circuit, and FIG. It is a figure which shows each the content of the bit code contained in the control to be performed.
13 is a diagram showing an example of a page write operation for a memory of the type shown in FIG. 2B, when the read / write control circuit is operated based on various data shown in FIG. It is a figure which shows timing charts, such as a control signal.
FIGS. 14A and 14B are diagrams showing an example of a read operation for the type of memory shown in FIGS. 2B and 2C, where FIG. 14A shows the contents of various data on the register circuit, and FIG. It is a figure which shows each the content of the bit code contained in the control contained in data.
15 is a diagram showing an example of a read operation for the type of memory shown in FIGS. 2B and 2C, in which the read / write control circuit operates based on various data shown in FIG. 14A. It is a figure which shows a timing chart of the control signal etc. at the time of doing.
FIGS. 16A and 16B are diagrams showing an example of a write operation for the memory of the type shown in FIG. 2C, where FIG. 16A shows the contents of various data on the register circuit, and FIG. It is a figure which shows each the content of the bit code contained in control.
17 is a diagram showing an example of a write operation for the memory of the type shown in FIG. 2C, and is a control when the read / write control circuit is operated based on various data shown in FIG. It is a figure which shows timing charts, such as a signal.
[Explanation of symbols]
100 contactless memory card
101 Coil for power supply
102 Coil for synchronous clock
103 Select coil
104 Coil for input
105 Output coil
120 Read / write control circuit
122 Control unit
1221 Register circuit
121 Data input switching circuit
123 Mode switching circuit
1231 Attribute input circuit
130 memory
200 Read / write device
201 Coil for power supply
202 Coil for synchronous clock
203 Coil for selection
204 Output coil
205 Input coil
300 Main unit

Claims (12)

Transferred address from the main unit, and a control unit that performs control necessary for read / write operation to the memory based on the data and control data to and the various data have register circuit for holding at least inclusive various data, wherein and it is connected to the subsequent stage of the register circuit receiving a command from the control unit and a data output circuit for outputting data on the register circuit to the memory, the control unit, the control data on the register circuit When a code related to data fixing selection is included, data on the register circuit is set to be output to the memory, while control data on the register circuit includes a code related to data change selection. Is transferred from the main unit without going through the register circuit. Write data is read / write control circuit of the memory, characterized in that has a structure having a function of setting so as to sequentially write into the memory has. Transferred address from the main unit, and a control unit that performs control necessary for read / write operation to the memory based on the data and control data to and the various data have register circuit for holding at least inclusive various data, wherein A data input switching circuit which is provided in a preceding stage of the register circuit and switches an output destination of various data transferred from the main device from the register circuit to the memory based on select data transferred separately from the various data from the main device; And a data output circuit connected to a subsequent stage of the register circuit and receiving a command from the control unit and outputting data on the register circuit to a memory, and the control unit controls the register circuit If your data contains code related to data pinning, When the data on the registration circuit is set to be output to the memory, and the control data on the register circuit includes a code relating to the selection of data change, the main device without going through the register circuit A read / write control circuit for a memory having a function of setting so that write data transferred from the memory is sequentially written to the memory. 3. The read / write control circuit for a memory according to claim 1, wherein the control unit performs a write to the memory when a control data on the register circuit includes a code related to a write selection. When the control data on the register circuit includes a code related to read selection, the memory has a function of setting so that the memory is read . A memory read / write control circuit. 3. The memory read / write control circuit according to claim 1, further comprising an address output circuit that receives an instruction from the control unit and generates an address signal and outputs the address signal to the memory. A configuration having a function of setting a bit length of an address bus line between the address output circuit and the memory when the control data on the circuit includes an address setting code, according to the setting; A memory read / write control circuit . 3. The read / write control circuit for a memory according to claim 1, wherein the control unit receives various data sequentially transferred from the main unit in n (n ≧ 1) register circuits 1, 2,. is capable of holding, and controls necessary for read / write operation to the memory on the basis of various data on the register circuit 1, then read to the memory on the basis of various data on the register circuit 2 · · · n / A memory read / write control circuit having a function of sequentially performing control necessary for a write operation . 3. The read / write control circuit for a memory according to claim 1 , wherein the control unit includes a counter circuit for counting the number of read / write processes when the read / write operation is repeatedly performed. when the code contains about once processed in the control data of the above, while performing read / write operations to be performed on the basis of the various data only once, the control data on the register circuit contains code for continuous treatment sometimes is, memory read / write control, characterized in that has a configuration in which the read / write operation performed on the basis of the various data has a function of performing many times of the number of counts contained in the various data circuit. In the address bus and the data bus and the common Display Types of memory of a memory according to claim 1 or 2, wherein adaptable read / write control circuit, wherein the control unit, the address set in the control data on the register circuit about when the code is present contains Marete is the control data to the included address settings, selection of address mask presence, the choice of address set number, the selection of mask address, transfer to the main unit of the data indicating the attribute of the memory while in accordance with the presence or absence of selection and related that code to each selection of the presence or absence of an output (including selection of the clock synchronization output / constant output CS) of the various control signal for setting the address set for the memory, controls on the register circuit If the data contains a code related to a dataset, Setting of addresses included in the trawl data, setting of the memory control, data of the changing / fixing settings (including selection of clocked out / constant output CS) each selection of presence or absence of an output of the various control signals and R / A read / write control circuit for a memory having a function of setting a data set for the memory according to a code relating to selection of whether or not to transfer a B signal to a main device. 3. The read / write control circuit for a memory according to claim 1, wherein a plurality of types of memories can be applied. The switch is a switch for setting and inputting a type of a memory to be used among the applicable memories, and the setting result is used as a signal. a mode switching circuit for outputting to the control unit includes an attribute input circuit for generating data indicating the attribute of the memory based on the type of the memory to the setting, the control unit stores various control in the control data on the register circuit when the code for the output signals are free Marete is the one that activates the control signal to be output to the memory, code for transfer to the main unit of the data indicating the attribute of the memory to the control data is present contains Marete sometimes, it functions to transfer data generated by said attribute input circuit to the main unit Memory, characterized in that has a has a configuration read / write control circuit. In the read / write control circuit of the memory of claim 8, wherein, when the code is present contains Marete regarding the output of the preliminary control signal to the control data on the register circuit, the control to be output to the memory A read / write control circuit for a memory, which has a function of activating a signal. A claim 2,3,4,5,6,7,8 or 9 memory read / write control circuit contactless memory card installed in the power supply for inputting power from the read / write device and use the coil, the coil of the synchronous clock for inputting the synchronous clock from the read / write device, the select-purpose coil for inputting a select data transferred through the read / write device in serial form from the main unit, the main an input coil for inputting various data transferred through the read / write device from a device in serial form, for output for outputting the read data and the like to be transferred to the main unit in serial form through the read / write device A contactless memory card comprising a coil. In the read / write device contactless memory card provided and claim 10 is connected to the main unit is set, and a power supply coil for supplying power to the contactless memory card, synchronized with the contactless memory card Mu said coil for a synchronous clock for providing a clock, a select-purpose coil for outputting in serial form the select data transferred to the contactless memory card from the main unit, various data transferred from the main unit an output coil for outputting the contact memory card in serial form, that at least the read data transferred toward the main unit from the non-contact memory card equipped with the input coil for inputting in serial form Characteristic read / write device. A contactless memory card according to claim 10 , a read / write device according to claim 11 , and a main device connected to the read / write device, wherein the main device registers various data in the contactless memory card. Solid state through the pretreatment and the read / write device to generate a select data for switching between the operation steps to perform read / write operations on the basis of various data stored in the pre-processing stage and a register circuit for holding the Separately, the data is transferred to the memory card. Separately, in the preprocessing stage, various data are generated and transferred to the contactless memory card through the read / write device. In this operation stage, the write data required for writing is generated and read. / Transfers to a contactless memory card through a write device, while reading from a contactless memory card Contactless memory card read / write system, characterized in that it is configured for inputting at least read data transferred through the light device.

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