JP2933848B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a data processing apparatus for use in a microprocessor or the like, in particular those concerning the faster data processing speed.

[0002]

2. Description of the Related Art In recent years, a microprocessor having a configuration (superscalar) for simultaneously executing a plurality of instructions has been proposed in response to a demand for higher performance of a data processing device such as a microprocessor. In the microprocessor having the superscalar configuration, a plurality of instructions are fetched by an instruction cache access every cycle and supplied to a plurality of instruction buses. These instructions are selectively issued to a plurality of instruction execution units and executed. Each instruction execution unit can often process only certain types of instructions,
Therefore, in selecting and issuing an instruction, it is necessary to determine the type of the fetched instruction and issue the instruction to an instruction execution unit that can process the instruction according to the type.

The configuration of each section of such a conventional data processing apparatus will be described below.

FIG. 4 shows a configuration of a conventional data processing apparatus, and particularly shows a detailed configuration of an instruction fetch unit. As shown in the figure, the data processing device includes an instruction cache 230.
, An instruction fetch unit 200, and instruction execution units 250 and 26
0 is arranged. In this example, the instruction execution unit includes an integer unit 252 so as to execute an integer operation instruction.
And a second execution unit 260 including a floating-point unit 262 for executing a floating-point instruction. Also, each execution unit 2
Two instruction decoders 251 and 261 for decoding instruction signals to 50 and 260 are provided. The instruction fetch unit 200 includes pre-decoders 221 and 222 for determining the type of instruction, and two instructions for selectively supplying an instruction by determining an instruction execution unit capable of executing the instruction from the type of instruction. Selection circuits 241, 242 are arranged. These instruction selection circuits 241, 242 are:
It is arranged corresponding to each of the instruction execution units 250 and 260 described above. Two instruction buses Bin1 and Bin2 for supplying the instructions IR1 and IR2 to the instruction selection circuits 241 and 242 are derived from the instruction cache 230. The instruction buses Bin1 and Bin2 are respectively connected to the instruction buses Bin1 and Bin2. It is connected to each of the instruction selection circuits 241, 242. Further, the instruction buses Bin1 and Bin2 are connected to the input sides of the predecoders 221 and 222, respectively. Then, the output signals PD1, PD2 of the respective predecoders 221, 222
Are used as control signals for the instruction selection circuits 241, 242.

[0005] Figure 5 is a timing chart showing a state of each signal in the data processing apparatus having the configuration of FIG 4. That is, when a plurality of instructions IR1 and IR2 are supplied from the instruction cache 230 (see timing ta in FIG. 3), the types of these instructions are determined in the predecoders 221 and 222, and each instruction is determined according to the type. The control signals PD1, PD are supplied to the selection circuits 241, 242.
2 is sent (see timing tb in the figure). The instruction selection circuits 241 and 242 select the instructions I1 and I2 corresponding to the instruction execution units 250 and 260 capable of executing the instruction from the types of these instructions, and
0, 260 each instruction decoder 25 arranged on the input side
Executing instructions I1 and 12 are output to reference numerals 261 and 261 respectively (see timing tc in the figure).

[0006]

However , in the configuration of the instruction fetch unit shown in FIG. 4 , the instruction signal supplied from the instruction cache is pre-decoded and used immediately for instruction selection / issue control to select the instruction. Because of the configuration, predecoding and selection of instructions must be controlled between the time an instruction is supplied from the instruction cache and the time it is issued to the instruction execution unit, thus completing the fetch operation. It takes a considerable amount of time T (see FIG. 5 ) to complete the process, which is one factor that hinders the high-speed operation of the data processing device.

SUMMARY OF THE INVENTION It is an object of the present invention to realize a high speed operation of a data processing device having a super scalar configuration in which selection / issue control of an instruction is performed using an instruction stored in an instruction queue. It is in.

[0008]

In order to achieve the above-mentioned object , a data processing apparatus according to the present invention is provided from an instruction cache.
The supplied instruction and the instruction determined by its predecode
An instruction standby unit for temporarily storing information representing the type of
It has a configuration in which instruction issuance is controlled using the information stored here.

Specifically, the means implemented by the present invention comprises: an instruction generating unit for generating a plurality of types of instructions; a plurality of instruction execution units each configured to execute a different type of instruction; It is assumed that the data processing apparatus includes an instruction fetch unit that selects and fetches an instruction input from the unit and adds the instruction to each of the instruction execution units. The instruction fetch unit is disposed corresponding to each of the instruction execution units, and selects one of the instructions input from the plurality of input units in response to the control signal and sends the selected instruction to each of the instruction execution units. A plurality of instruction selection circuits to be sent; an instruction standby unit having an input side connected to the instruction generation unit via an instruction bus, and an output side connected to the input unit of the instruction selection circuit via a standby instruction bus; After detecting the instruction input to each instruction execution unit from the selection circuit, and storing in the instruction standby unit the instruction that has not been executed by any instruction execution unit among the instructions input from the instruction generation unit, And control means for controlling transmission from the instruction selection circuit to the instruction execution unit.
Moreover, the instruction waiting section stores the unexecuted instruction and its program.
Wait instruction indicating the type of instruction determined by re-decoding
Unexecuted wait after temporarily storing decode signal
An instruction is output to the standby instruction bus and the standby instruction
A code signal is sent to each of the above-mentioned instruction selection circuits as the above-mentioned control signal
It has a function to output.

[0010]

According to the present invention, instruction selection / selection by the instruction selection circuit is performed.
When issuing control, the standby command output from the
Instruction decoding signal
Even if the instruction output from the standby unit is decoded again
To which instruction execution unit this instruction should be issued.
You can know immediately. Therefore, it is necessary to issue
Time and data processor speed
It is.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention.

As shown in FIG. 1, the data processing apparatus of the present invention includes an instruction cache operation clock generation unit 10, an instruction address generation unit 20, an instruction cache 30, and instruction buses Bin1 and Bin2 provided in the instruction cache 30. Instruction fetch unit 100 connected via
00, first and second instruction execution units 50 and 60 connected via instruction issue buses Bout1 and Bout2, respectively, are arranged. The instruction cache is connected to an instruction bus (not shown), and the first and second instruction execution units 50 and 60 are connected to a register file (not shown). Further, a data cache (not shown), a data address generator, and a data cache operation clock generator are connected to the register file.

The instruction cache operation clock generator 1
0, the instruction address generation unit 20, the instruction fetch unit 100,
Each of the first and second instruction execution units 50 and 60 is configured to operate in response to an external clock signal CLK, but the instruction cache 30 stores the address synchronization clock generated by the instruction cache operation clock generation unit 10. Signal S10
It is configured to operate in accordance with The first and second instruction execution units 50 and 60 are configured to execute different types of instructions. That is, the address signal S22 from the instruction address generation unit 20 is transmitted to the instruction cache 3
0, two instructions are read in one cycle in the instruction cache 30, and the instruction IR of the relevant address is read.
1 and IR2 are output to the instruction buses Bin1 and Bin2. Then, the instructions IR1, I2 are transmitted via the instruction buses Bin1, Bin2.
When R2 is input to the instruction fetch unit 100, the instruction fetch unit 100 sorts the instructions IR1 and IR2 into types that are compatible with the instruction execution units 50 and 60, and selects each type via the instruction issue buses Bout1 and Bout2. The instruction is sent to the instruction execution units 50 and 60.

As shown in FIG. 2, the instruction fetch unit 1
00 is a predecoder 121,1 for decoding instructions IR1, IR2 input from the respective instruction buses Bin1, Bin2.
22 and the output from each of the predecoders 121 and 122 and the signal on each of the instruction buses Bin1 and Bin2 before passing through the predecoders 121 and 122. An instruction queue 123 having a function of outputting, three-state buffers 141 and 142 interposed on the instruction buses Bin1 and Bin2 on the entrance side of the predecoders 121 and 122, and which instruction is transmitted to each of the instruction execution units 50 and 60. An instruction fetch control circuit 143 for detecting whether or not an instruction has been input and controlling the issuance of a subsequent instruction; and having three input terminals, two control terminals, and one output terminal, and one of the input instructions And instruction selection circuits 151 and 152 for selecting the output and outputting them to the instruction execution units 50 and 60, respectively. The output terminal of the instruction queue 123 includes:
First and second standby instruction buses Bwt1 and Bwt2 are connected, and each of these standby instruction buses Bwt1 and Bwt2 is connected to the input terminal of each of the instruction selection circuits 151 and 152. The standby instruction decode signal lines Bdc1 and Bdc2 for outputting the standby instruction decode signal are connected to the predecoder 121,
122 is provided via an instruction queue 123 from the output side of the standby instruction decode signal lines Bdc1 and Bdc2.
Are connected to the control terminals of the instruction selection circuits 151 and 152. That is, the standby instruction decode signal is temporarily stored in the instruction queue 123 and then output to the instruction selection circuits 151 and 152 at the next timing. In the configuration of the instruction fetch unit 100, the instruction waiting unit 120 is configured by each of the predecoders 121 and 122 and the instruction queue 123, and each of the instruction selection circuits 15
1 and 152 constitute an instruction selecting unit 150, and the three-state buffers 141 and 142 and the instruction fetch control circuit 143 constitute a control unit 140.

The first instruction execution unit 50 includes a first
An instruction decoder 51, a latch 53, and a floating point unit 52 capable of processing a floating point instruction are arranged. The second instruction execution unit 60 includes a second
An instruction decoder 61, a latch 63, and an integer unit 62 capable of processing an integer operation instruction are arranged. Then, the first and second instruction selection circuits 151, 15
2 and the first and second instruction decoders 51 and 61
Are the first and second instruction issuing buses Bou, respectively.
They are connected via t1 and Bout2. Latches 53, 63
Is the L (load) stage and E (execution) of the pipeline
It separates the stage.

The function of each element of the data processing device configured as described above will be described. The instruction cache 30 is:
Two instructions are read in one cycle and each instruction bus Bin1 is read.
, Bin2 to output the instructions IR1 and IR2. And
The instructions IR1 and IR2 are input from the instruction buses Bin1 and Bin2 to the predecoders 121 and 122 and the instruction queue 123. One instruction IR1 is also input to the first and second instruction selection circuits 151 and 152. Predecoder 12
1 and 122 respectively receive the instructions IR1 and IR2, determine the type of the supplied instruction (integer operation instruction / floating point operation instruction), and output the standby instruction decode signals PD1 and PD2 to the instruction queue 123. The instruction queue 123 includes a FIFO (First-In-First-Out) memory circuit having a plurality of entries. Each entry can store a standby instruction decode signal corresponding to an instruction, and can be sequentially read from the previously written entry. Is controlled. The instruction queue 123 stores two instructions IR1 and IR in one cycle.
2 and the corresponding standby instruction decode signals PD1 and PD2 can be written to two consecutive entries, and the instruction fetch control circuit 143 controls only the unexecuted instruction and the corresponding standby instruction decode signal among these. Is controlled to be written. The instructions of the two consecutive entries written earlier are supplied to the input terminals of the instruction selection circuits 151 and 152 as standby instructions R1 and R2 via first and second standby instruction buses Bwt1 and Bwt2, respectively. The corresponding standby instruction decode signals QD1 and QD2 are standby instruction decode signal lines Bdc1 and Bdc.
2 are supplied to the control terminals of the first and second instruction selection circuits 151 and 152 and the instruction fetch control circuit 143. The first and second instruction selection circuits 151 and 152 output a standby instruction decode signal to a control terminal from among three signals input from the first instruction bus Bin1 and the first and second standby instruction buses Bwt1 and Bwt2. One signal is selected according to QD1 and QD2, and first and second instruction issue buses Bout1 and Bou are respectively selected.
Output to t2.

The first instruction selection circuit 151 has a standby instruction R1
Is a floating point operation instruction, the standby instruction decode signal QD1 indicates that the standby instruction R1 is an integer operation instruction, and the standby instruction decode signal QD1 indicates that the standby instruction R1 is an integer operation instruction. When the standby instruction decode signal QD2 indicates that the instruction is a decimal point operation instruction, the standby instruction R2 is selected. Otherwise, the instruction IR1 input from the first instruction bus Bin1 is selected. The instruction selected by the first instruction selection circuit 151 in this way is referred to as a first instruction issue bus Bou as an issued instruction I1.
It is input to the first instruction execution unit 50 via t1. When the standby instruction decode signal QD1 indicates that the standby instruction R1 is an integer operation instruction, the second instruction selection circuit 152 outputs the standby instruction R1 and the standby instruction R1 that the standby instruction R1 is a floating point operation instruction. When the standby instruction decode signal QD2 indicates that the decode signal QD1 indicates that the standby instruction R2 is an integer operation instruction, the standby instruction R2 is used. Otherwise, the instruction I input from the first instruction bus Bin1 is used.
Select R1 respectively. The instruction selected by the second instruction selection circuit 152 in this manner is issued as an issued instruction I2.
It is input to the second instruction execution unit 60 via the second instruction issue bus Bout2.

Next, a specific operation of the data processing apparatus will be described with reference to a timing chart of FIG. First, when all the entries in the instruction queue 123 are empty and the instructions IR1 and IR2 are supplied to the first and second instruction buses Bin1 and Bin2, respectively (for example, I2
(Where R1 is an integer operation instruction and IR2 is a floating point operation instruction). In the first clock cycle Pe1, the first and second instruction buses Bin1 and Bin at timing t1.
2 are supplied with the instructions IR1 and IR2, respectively, since no instructions are supplied to the first and second standby instruction buses Bwt1 and Bwt2, the first and second instruction selection circuits 151 and 15 are provided.
In both cases, the instruction IR1 (integer operation instruction) on the first instruction bus Bin1 is selected and output to the instruction issue buses Bout1 and Bout2. This instruction is executed by the second instruction execution unit 60, but is ignored by the first instruction execution unit 50 because it does not match. Therefore, in this cycle Pe1, only the issued instruction I2 of the second instruction selection circuit 152, that is, the integer operation instruction IR1 is executed (timing t2 in the figure). The instruction fetch control circuit 143 controls each of the three-state buffers 141 and 142 and the instruction queue 123 according to the decoding results of the first and second instruction decoders 51 and 61. As a result, the unexecuted second instruction bus B
The floating point operation instruction IR2 of in2 is written to the instruction queue 123. Also, the predecoder 122 outputs the instruction IR
2 generates a standby instruction decode signal PD2 indicating that the instruction is a floating point operation instruction.
2 is also written to the instruction queue 123 (timing t3 in the figure).

In the next clock cycle Pe2, the floating-point arithmetic instruction IR
2 is a standby instruction R1 and its decode signal PD2
Are output as the standby instruction decode signal QD1 (timing t4). Subsequently, in this cycle, new instructions IR1 and IR2 are supplied to the first and second instruction buses Bin1 and Bin2, respectively (for example, the instructions IR1 and IR2 are both integer operation instructions) (timing t in FIG.
Five ). Then, the first instruction selection circuit 151 selects the floating-point operation instruction R1 on the first standby instruction bus Bwt1 and outputs it to the first instruction execution section 50 as the issued instruction I1, while the second instruction selection circuit 152 outputs the first instruction The integer operation instruction IR1 on the instruction bus Bin1 is selected and output to the second instruction execution unit 60 as the issued instruction I2. These issued instructions I
1 and I2 are executed by the first and second execution instruction units 50 and 60, respectively. Therefore, in this cycle Pe2, two instructions are executed in parallel (timing t6). At this time, during the time T between the timing t5 and the timing t6, the instructions IR1 and IR1 of the first and second instruction buses Bin1 and Bin2 are set.
2 is not pre-decoded, so that the time T is shorter than before. On the other hand, the integer operation instruction IR2 not input to the instruction execution units 50 and 60 is written to the instruction queue 123 under the control of the instruction fetch control circuit 143. Further, the predecoder 122 generates a standby instruction decode signal PD2 indicating that the instruction IR2 is an integer operation instruction, and the standby instruction decode signal PD2 is also written in the instruction queue 123 (timing t7).

Further, in the next clock cycle Pe3, the waiting integer operation instruction IR is stored in the instruction queue 123.
2 is a standby instruction R1 and its decode signal PD2
Are output as the standby instruction decode signal QD1 (timing t8). Subsequently, in this cycle, new instructions IR1 and IR2 are supplied to the first and second instruction buses Bin1 and Bin2, respectively (for example, both the instructions IR1 and IR2 are floating-point arithmetic instructions) (timing t9 in FIG. ). Then, the first instruction selection circuit 151
The floating-point operation instruction IR1 on the instruction bus Bin1 is selected, and the integer operation instruction R1 on the first standby instruction bus Bwt1 is selected by the second instruction selection circuit 152 (timing t10).
On the other hand, the floating-point operation instruction instruction IR2 not input to the instruction execution units 50 and 60 and its decode signal PD2 are written in the instruction queue 123 under the control of the instruction fetch control circuit 143.

As described above, in the data processing device of this embodiment, in a cycle in which an instruction is in the instruction queue 123, two instructions can be executed in parallel according to the combination of instructions. In the present embodiment, the number of executed instructions is 2 at the maximum and cannot exceed the number of supplied instructions 2. Therefore, as long as instruction supply is continuously performed, one or more instructions are always stored in the instruction queue 123. I have. Therefore, if the combination of instructions allows, two instructions can always be executed in parallel. In this case, in the conventional example, the contents of the instruction buses Bin1 and Bin2 are decoded in order to control the selection / issuance of the instruction by the instruction selection circuit, whereas in this embodiment, the standby instruction decode signal QD1 is used. , QD2. Since the read time of the instruction queue 123 is shorter than that of the instruction cache 30, the instructions on the standby instruction buses Bwt1 and Bwt2 are not read by the instruction buses Bin1 and Bin2.
Settled earlier than compared to. In the conventional example, a series of operations such as reading from the instruction buses Bin1 and Bin2, predecoding, and selecting an issued instruction had to be executed in one cycle. However, in the present embodiment, the instruction bus Bin was used.
1, read from instruction queue 123,
Only the issue instruction selection needs to be performed in one cycle. Therefore, as compared with the configuration in which the types of the instructions IR1 and IR2 of the instruction buses Bin1 and Bin2 are determined to issue / control the instructions,
Instruction selection / issuance can be performed at high speed, and high-speed operation of the data processing device can be realized.

In this embodiment, the instruction cache 30
Has a configuration in which two instructions are supplied to two instruction buses in one clock, but the same operation can be realized by supplying one or three or more instruction buses and supplying instructions to each. Is possible.

The instruction fetch unit 100 of the above embodiment
In this configuration, the instruction queue 123 is configured to output stored instructions and signals to two standby instruction buses and standby instruction decode signal lines. It is also possible to provide a configuration in which a plurality of instructions are provided and the instructions and the signals stored in the instruction queue are output to each of them.

[0024]

As described above, according to the present invention , as a data processing device, one of input instructions is selected by a plurality of instruction selection circuits and sent to each instruction execution unit. Since the instruction not executed by the instruction execution unit is stored together with the predecode result in the instruction standby unit, the instruction is sent from the instruction selection circuit to the instruction execution unit using the predecode result . The time required for issuing an instruction is reduced, and the operation speed of the data processing device can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a data processing device according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a detailed configuration of an instruction fetch unit in FIG.

FIG. 3 is an operation timing chart of an instruction fetch unit in FIG. 2;

FIG. 4 is an electric circuit diagram showing a configuration of a conventional data processing device.

FIG. 5 is an operation timing chart of an instruction fetch unit in FIG. 4 ;

[Explanation of symbols]

 Reference Signs List 10 instruction cache operation clock generation unit 20 instruction address generation unit 30 instruction cache 50 first instruction execution unit 51 first instruction decoder 52 floating point unit 53 latch 60 second instruction execution unit 61 second instruction decoder 62 integer unit 63 latch 100 instruction Fetch unit 120 Instruction waiting unit 121, 122 Predecoder 123 Instruction queue 140 Control means 141, 142 Three-state buffer 143 Instruction fetch control circuit 150 Instruction selection unit 151 First instruction selection circuit 152 Second instruction selection circuit Bin1, Bin2 Instruction bus Bwt1 , Bwt2 standby instruction bus Bdc1, Bdc2 standby instruction decode signal line Bout1, Bout2 instruction issue bus

──────────────────────────────────────────────────続 き Continuing from the front page (56) References Morihiro Kuga and two others “Low-level parallel processing algorithm of“ Shinpu ”processor based on SIMP (single instruction flow / multiple pipeline)”, Parallel Processing Symposium JSPP '89, February 1989, pp. 163-170 (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 9/38

Claims (3)

(57) [Claims] An instruction generator for generating a plurality of types of instructions, a plurality of instruction execution units configured to execute different types of instructions, and an instruction input from the instruction generator are selected. And an instruction fetch unit for extracting and fetching the instruction fetch unit from the plurality of input units. A plurality of instruction selection circuits for selecting any one of the input instructions and sending the selected instruction to each of the instruction execution units, and an input side connected to the instruction generation unit via an instruction bus;
An output side is connected to an input unit of the instruction selection circuit via a standby instruction bus, and an instruction standby unit detects an instruction input to each instruction execution unit from each instruction selection circuit, and receives an instruction from an instruction generation unit. and after the instruction was not executed in any of the instruction execution unit of the instruction is stored in the instruction waiting section, it is composed of a control means for controlling to send the instruction execution unit from the instruction selection circuit, the instruction standby section Is the above unexecuted instruction and its predecode
Wait instruction decode indicating the type of instruction determined by the command
After temporarily storing the signal and
Output to the standby instruction bus and decode the standby instruction
Is output to each of the instruction selection circuits as the control signal.
A data processing device having a function . 2. The data processing device according to claim 1, wherein each of said instruction selection circuits has at least one of its input sections.
One is connected to the above-mentioned instruction generator via the instruction bus, and the other is
The input unit is connected to the instruction standby unit via a standby instruction bus.
The data processing apparatus characterized by being. 3. The data processing device according to claim 2, wherein each of said instruction selection circuits is executable by a corresponding instruction execution unit.
Instruction is input from both the instruction bus and the standby instruction bus.
If the via standby instruction bus from the instruction standby section
A data processing device having a function of preferentially selecting an input instruction .