JPS61288230A - Pipeline control system - Google Patents

Abstract

PURPOSE:To improve the throughput by shortening the delay time of a hold signal generating circuit in each state in the pipeline control to reduce the clock cycle of an information processor. CONSTITUTION:An instruction sent through an instruction register 31 is transmitted to stages D, A1, D2, and E and is processed in the cycle of a maximum of one clock. In case of a load/store instruction, an operation code OP and an address are sent to a buffer memory unit in the stage E. In case of an arithmetic instruction, the operation code OP and the first and the second operands Y and Z are sent to an arithmetic unit corresponding to the classification of operation in the stage following the stage E. During this period, a general register (GR) used for address generation of the load/store instruction is read out in the stage D and a GR of an arithmetic operand is read out in the stage E.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pipeline control system, and particularly to a hold control system for processing stages.

[Conventional technology]

Conventionally, read control of a general-purpose register (hereinafter abbreviated as GR) and hold control of each stage in an instruction processing unit that employs a pipeline control method is as follows. In order to simplify the explanation, an instruction processing unit that mainly handles arithmetic instructions between GRs and load/store instructions between a memory and a GR will be described.

FIG. 6 is a block diagram showing the main parts of an instruction processing unit that employs a conventional pipeline control method. This instruction processing unit includes an instruction fetch section 1, a decode (D) stage instruction register 2, a first address creation (Δ1) stage instruction register 3, a second address creation (A2) stage instruction register 4, and an execution start (E) stage instruction register 5, register bank 11, displacement register 12, base address register 13,
An index address register 14, a carry save adder (CAS) 15, registers 16 and 17 for holding intermediate results of address addition, and a two-person adder (CP).
8) 18, memory address register 19, operand registers 20 and 21, flag 6 indicating that part of the GR in register bank 11 is in an update waiting state, and GR used as the base address and index address are updated. A combinational circuit 7 for detecting whether it is in a waiting state, a combinational circuit 8 for similarly detecting whether GR used as an operand is in an update waiting state, each of a plurality of arithmetic units and a buffer. The main part consists of a flag 9 provided corresponding to the memory unit and indicating that these units are unusable, and a combinational circuit 10 that detects that the arithmetic unit used by the E stage instruction is unusable. It is configured.

In such a pipelined instruction processing unit, the instruction word received from the instruction fetching unit 1 can be processed by propagating it sequentially to the D stage, A1 stage, A2 stage, and E stage at a cycle of 1 instruction and 1 clock. , processing may be delayed depending on the instruction sequence being processed.

For example, when reading a value in a GR that is an input for address generation in the D stage, this GR is in an update waiting state.
In other words, the instruction preceding the D stage instruction is the same -GR
If the instruction to update the parentheses is in progress somewhere between the AI stage and the final stage of the arithmetic unit, it is necessary to wait for the processing in the D stage, and the same thing will happen to the operand in the E stage. GR
This also occurs when reading .

Furthermore, if the arithmetic unit is not completely pipelined, it is also necessary to wait until the arithmetic unit becomes available in the E stage.

Conventionally, the detection of waiting conditions is performed using combinational circuits 7.8 and l.
This is achieved by matching the flag with the instruction word information of the stage to wait as shown in O, and holding that stage and all stages above it based on this detection output.

[Problem that the invention seeks to solve]

In the conventional pipeline control method described above, although the hold signal of each stage is a signal that spans the entire instruction processing unit, the number of gate stages between the flip-flops of the hold signal is quite large, so it takes a long time to transmit the hold signal. This has the drawback that it takes a long time and the clock cycle of the information processing device including the instruction processing unit cannot be reduced, which hinders the performance improvement of the information processing device.

In addition, simply inserting a flip-flop in the middle of the hold signal generation circuit of each stage will only delay the start and release timing of hold by one clock, which will result in incorrect processing and will not solve the problem. .

An object of the present invention is to provide a pipeline control method in which the hold condition of a specific stage is predicted several clocks in advance, a hold FF set signal is created, and the register of each stage is directly held with the output of the hold FF. It is about providing.

[Means for solving problems]

The pipeline control method of the present invention is a pipeline control method for an information processing device that includes a plurality of serially connected stages and processes the output of each stage while sequentially transmitting the output in synchronization with a clock. a prediction means for predicting whether or not the processing information needs to be held at the specific stage in a stage preceding the specific stage when the processing information needs to be held at a specific stage; , flip-flop means for setting the processing information in the specific stage and simultaneously setting the prediction signal to hold the specific stage; and reset means for predicting hold release conditions before the hold release timing of the specific stage and resetting the flip-flop means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a control section of an instruction processing unit that employs a pipeline control method according to an embodiment of the present invention. This instruction processing unit includes an instruction register 31 of an instruction fetch section, a D stage instruction register 32, an AI stage instruction register 33, and an A2 stage instruction register 3.
4, the E stage instruction register 35, the GR update wait detection circuit 36, and the GR update wait check instruction registers 37 and 38 of the AI stage, A2 stage, and E stage.
and 39, arithmetic unit busy check instruction registers 40 and 41 of A2 stage and E stage,
A plurality of busy flags 42 that display when an arithmetic unit cannot be used, decoders 49, 50 and 51 that decode instruction operation codes, and flip-flops that hold registers of the AI stage, A2 stage, and E stage. (Hereinafter, F
The main part thereof is composed of an FF 59 (abbreviated as F) and an FF 55 that holds registers of stages D and higher.

Note that each instruction register is 4 bytes, and in Figure 1 G
Although the register bank, address adder, and peripheral registers constituting R are not shown, they are as shown in FIG. 6 described above.

FIG. 3 shows the format of the instruction word given to the instruction processing unit.

The instruction word for an operation instruction between GRs is 4 bytes, and includes the operation code oP, the storage destination GR number
It consists of The command word of the load/store instruction is the above operation code OP and GR numbers x, y, z followed by a 4-byte displacement, and the addresses are GRy and GR.
z (However, the subscripts y and 2 are the GR number base and Z
This means that it is a GR specified by. The same applies hereafter) and the displacement.

Returning to FIG. 1, the instruction word sent sequentially via the instruction register 3I is transmitted to the D, AI, A2 and E stages and processed in a maximum period of one clock, and in the case of a load/store instruction, the E Operation code OP from stage
In the case of an arithmetic instruction, the operation code OP and the first and second operands Y and Z are sent to the arithmetic unit according to the type of operation. During this time, in the D stage, the GR used to generate the address of the load/store instruction is read, and in the E stage, the GR that becomes the arithmetic operand of the arithmetic instruction is read.

Further, when the execution start is issued from the E stage, the operation result is returned to the register bank 11 (see FIG. 6) at the time determined by the operation code OP. Load data also returns at a fixed time unless a miss occurs in the buffer memory unit.

Next, details of the GR update wait detection circuit 36 will be explained with reference to FIG. This GR update waiting detection circuit 36 has a register 80 in which the GR number to be updated is registered, and a register 80 that indicates that the GR indicated in this register 80 is being updated, that is, this GRR
3 types of FF83.84 indicating that a new command is in progress
and 87, an execution time counter 85 which has a preset execution time for this new GRR instruction and counts down after receiving the execution start signal 110, and a decoder 86 which detects that the value of this counter 85 is 1 degree. A1 stage GR number number base and Z and updated GRR number register 8
8 sets (entries) of circuits each consisting of matching circuits 81 and 82 that detect matching with GR numbers within 0 (II
It is growing.

When the GRR new instruction is set from the instruction register 31 to the D stage instruction register 32, the operation code O
The decoded signal 67-a by the decoder 50 of P becomes "l", and one of the vacant entries among the eight entries,
For example, entry 0 is selected by the selection circuit 98.
Furthermore, if the T output of the hold FF 59 is '0° and there is no GR update wait condition in the D stage, the GR update instruction stored in the D stage instruction register 32 is an AI stage instruction and is sent to the register 33. At this time, at the same time, the storage destination GR number Validity display FF83 is also set. Further, the number of the registered entry, ie, "0" and the valid bit are set in the register 121. At the same time as this update instruction is sent from the A2 stage to the E stage, the FF 84 is sent.

Furthermore, when execution of this update instruction is started from the E stage, the FF 87 is sent by the execution start signal 110, and at the same time, the execution time counter 85 starts decrementing.

When the value of the counter 85 reaches 2, the FF 84 is reset, and when the value of the counter 85 reaches "lo", the FFs 83 and 87 are reset.

Next, the operations of the FFs 55 and 59 that control stage hold in the pipeline control system of the present invention will be described.

Figure 4 is a time chart when an instruction sequence of an addition instruction that updates GR4 and a load instruction that uses GR4 for address calculation is processed. explain.

At the same time that the AD instruction enters the AI stage from the D stage, the update wait state of GRi is set to entry 0 of the GR update wait detection circuit 36. That is, i is preset to the update GR number register 80, the calculation time "3" of the AD instruction is preset to the execution time counter 85, and the validity display FF 83 of entry O is set.

At the same time, the subsequent LD instruction is
(abbreviated as FC) l is sent from the instruction register 31 to the D stage instruction register 32. At this time, the decode signal output from the decoder 49 becomes 1 if there is a load/store instruction in the instruction register 3I, sets the AND gate 52 to "lo", and sets the FF 55. , the GR is read in the D stage, but if this GR is waiting for update, it is necessary to hold the D stage, and the load/store instruction is set in the D stage instruction register 32 and FF 55 is set at the same time. If not, which is often the case, there is no loss in performance even if the D stage instruction register 32 is held for one clock, because the last 4 bytes of the LD instruction are displaced. , this is because it is not set in the D stage instruction register 32.

When the hold FF 55 is set, the LD instruction is set in the D stage instruction register 32 at the same time, and the GR number Y or Z indicating the first or second operand becomes i, so the entry O is sent via the signal line 61 or 62. The output of the matching circuit 81 or 82 becomes °1, and the signal 64 becomes °
1°, and the FF 55 is set to am by the output of the AND gate 53. Two clocks later, the AD instruction enters the E stage, and at the same time an execution start instruction is issued, which causes the execution start signal 110 of the decoder 125 to become "lo" and the execution time counter 85 to start decrementing. This counter value becomes " When the signal becomes "2", the FF 84 is reset, and when the signal becomes "1", the FFs 83 and 87 are reset.

When the FF 83 becomes "O", the outputs of the matching circuits 81 and 82 of entry 0 are invalidated, the signal 64 becomes "0", and the FF 55 is reset.

FIG. 5 shows a time chart when an instruction sequence of an addition instruction that updates GRi and a multiplication instruction that uses GRi as an operand is processed.
The D instruction and multiplication instruction will be abbreviated as ML instruction.

When the AD instruction advances from the D stage to the A1, A2, and E stages and starts execution, the validity display FFs 83 and 84 and the execution time counter 85 of entry 0 operate in the same manner as described above.

When the ML instruction is sent to the D stage instruction register 32, the outputs of the matching circuits 81 and 82 at entry 0 are
Therefore, the input of bit O of the update waiting check instruction register 37 becomes "1°." Here, entry 0 is set by the signal 66 in the combinational circuit 45.
The value of FF84 is checked, and since the value of FF84 is still °1°, OR gate 47 and AND gate 56
The hold FF 59 is set via the OR gate 58. This timing is at the same time that the ML instruction is sent to the E stage instruction 35. Hold FF
When 59 is set, all stages are held.

When the ML instruction is set in the E stage instruction register 35, bit 0 of the update waiting check instruction register 39 becomes “1”, and the value of the validity display FF 84 becomes the signal 6.
6, and at the same time the hold F is checked via OR gate 48, AND gate 57 and OR gate 58.
F59 is continuously set.

When the value of the execution time counter 85 reaches "2 degrees", that is, one clock before the writing cycle to GRi by the AD instruction, the validity display FF 84 is sent via the decoder 86.
will be reset. In the next cycle, the output of the combinational circuit 46 becomes 0, the FF 59 is reset, and the hold of all stages is released.

Next, the busy check of the arithmetic unit will be explained.

The decoder 51 inputs the operation code OP stored in the A1 stage instruction register 33, decodes the arithmetic unit used to execute this instruction, and sets the corresponding bit to "Alo".The busy check instruction registers 40 and 41 The purpose is to transfer the results to various stages.

The plurality of busy flags 42 provided for each arithmetic unit become "1" when the arithmetic unit is in an unusable state, and the cent and reset are performed two machine cycles before the actual arithmetic unit's busy state. When an instruction enters the E stage from the A2 stage, the combinational circuit 43 checks whether a predetermined arithmetic unit is busy, and if it is not busy, the E stage execution start FF (not shown) is set along with other conditions. This is because this FF is sent to the arithmetic unit after receiving it one more time.The reset of the busy flag of the arithmetic unit is also realized by the same execution time counting means as described above.

〔Effect of the invention〕

As explained above, the present invention reduces the clock cycle of the information processing device by shortening the time required to transmit the hold signal of each stage, that is, the electrical delay time of the hold signal generation circuit. It has the effect of improving performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the control section of an instruction processing unit that adopts the pipeline control method of the present invention, FIG. 2 is a block diagram of the GR update wait detection circuit in FIG. 1, and FIG. 3 is a block diagram of the GR update wait detection circuit in FIG. FIG. 4 and FIG. 5 are time charts for explaining the stage hold operation of the instruction processing unit in FIG. 1. FIG. 6 is a diagram showing a conventional pipeline control method. FIG. 2 is a block diagram of an instruction processing unit employed. In the figure, 31.32.33.34.3536...Instruction register, 36...GR update wait detection circuit, 37.38.3
9.GR update wait check instruction register, 40.41... Arithmetic unit check instruction register, 42... Arithmetic unit busy flag, 55.59
...Stage hold FF, 80...Updated GR
Number register, 85...Arithmetic time counter, 81.82...-Number circuit, 83.84.87-Status flag, 121.122.123...Register. Figure 1 /II /It 3rd picture 4th picture 5th picture

Claims (1)

[Scope of Claims] A pipeline control method for an information processing device that has a plurality of cascade-connected stages and processes the output of each stage while sequentially transmitting it in synchronization with a clock, comprising: Prediction means for predicting whether or not it is necessary to hold the processing information at the specific stage in a stage preceding the specific stage when it is necessary to hold the processing information at a specific stage; flip-flop means for setting the processing information to the specific stage and simultaneously setting the prediction signal to hold the specific stage; and holding the specific stage using the processing information set for the specific stage. A pipeline control method comprising: a reset means for predicting a release condition before the hold release timing of the specific stage and resetting the flip-flop means.