JPH02136926A - Process follow-up type interlock mechanism - Google Patents

Abstract

PURPOSE:To effectively transform a process unit having the complicated process contents into a pipeline by releasing the inhibition of the modification or reference for a unit set at a front stage of the relative and subsequent instruction when a specific condition is not satisfied. CONSTITUTION:For instance, the conditions which decide whether or not a process unit U2 of the next stage should modify or refer to the contents of a memory element to which a process unit U1 of the preceding stage always modifies or refers with a subsequent specific instruction are decided at and after the time point when the unit U1 can process the preceding instruction. In such a case, the satisfaction or dissatisfaction of the relevant conditions is detected at and after the processable time point. When the conditions are not satisfied, the inhibition is released for the modification or the reference of the relative subsequent instructions for the unit U1. Thus it is not required to inhibit the subsequent instructions for a period longer than the necessary period. Then a process unit having the complicated process contents can be effectively transformed into a pipeline.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a pipeline system, and particularly relates to a processing process tracking type system that enables effective pipelining of a processor (processing unit) having a complex processing content. It relates to an interlock mechanism.

[Conventional technology]

Conventionally, in a pipeline computer, as shown in FIG.
, CRy, CRz, and CRw, flags Fx and Fy are added to each shared register.

Fz and Fw are set, and when S fetches/decodes a certain instruction, one of the shared registers is set by U2. set,
Until unit U2 has finished its execution and flag reset circuit R resets this flag, ink clock unit IU3 will henceforth etch/decode any instructions that need to modify or reference this register in unit) Ul. An interlock mechanism was used to prevent modification or reference even if the

[Problem to be solved by the invention]

As mentioned above, in conventional interlock mechanisms.

It was necessary to determine the registers to be modified or referenced by each processing unit in the pipeline at the time an instruction was 7etched/decoded. When the future K is determined only after further processing has progressed, it has been difficult to effectively bypass the process.

To be more specific, as shown in FIG.
In the case of a two-stage pipeline system that shares x, CRy, CRz, and CRw, for instruction 1 that is always modified by unit)U2, register CRx is modified by unit)U2 in the previous stage.
The flag set circuit S sets the flag Fx corresponding to the register CRxK when this instruction is etched/decoded 7 times, and after this instruction is executed in unit U2 until the flag reset circuit R resets it. , reference to register CRx by an instruction that modifies or expands reference to register CRx, for example, instruction 15, is inhibited by ink clock unit EU3. In the same figure, this relationship is shown by the broken line D1.
It is shown in In this case, deterrence is considered inevitable. However, in the prior art, if the condition as to whether or not the subsequent unit (U2) modifies or refers to a specific preceding instruction is determined after the time when the preceding unit (U1) can process the preceding instruction. U2 modifies register CRz or not, which depends on the contents of register CRx.
If decoded, the flag set circuit S of unit U1
At this point, unit U2 executes instruction 13, and flag reset circuit R resets 7-lag Fz, regardless of whether instruction 13 modifies register CRz. Until this happens, it is necessary to suppress reference to register CRz by an instruction that refers to register CRz in unit U1, such as instruction 16. In the figure, this relationship is shown by a solid line D2. Similarly, as shown by solid lines D3 and D4, a specific preceding instruction, for example instruction 14, causes the register C, which is a storage element that is always modified by the subsequent unit U2, to
If there is Rw, whether this content is modified or referenced by instruction 17.18 of the specific instruction read later by the previous unit (Ul) is determined by K, which in this case is determined once the contents of register CRx are determined. Since nothing more than setting the flag Fw corresponding to register CRw is done when instruction 14 is etched/decoded 7 times, even if the contents of register CRx are confirmed, instructions 17.18
Even if U2 does not modify or refer to register CRw, unit) U2 finishes executing instruction 14,
With conventional interlock mechanisms, it is necessary to inhibit subsequent instructions for a longer period than necessary, such as having to inhibit the processing of instructions 17 and 18 in Units) Ul until the flag Fw is reset. Effective pipelining was difficult.

[Failure to solve the problem]

The processing process tracking interlock @ structure of the present invention is used in a pipeline system consisting of a plurality of units. When the conditions for whether or not to be modified or referenced in an instruction are determined after the time when the preceding unit is able to process the preceding instruction, and the contents of the memory element are always modified or referenced by the subsequent unit by the preceding specific instruction. is modified or referenced by a specific subsequent instruction by the preceding unit, and the condition is satisfied or not satisfied in at least one of the cases where the condition as to whether or not the preceding unit is modified or referred to by the subsequent specific instruction is determined after the time when the preceding unit is able to process the preceding instruction. It has a function of detecting after the processable time, and when the condition is not satisfied, K is involved in this and cancels the inhibition of modification or reference in the preceding unit of the subsequent instruction.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The pipeline consists of two stages: the first processing unit (Ul) and the second processing unit (U2), and registers CRx and CRy.
#CRz and CRw are shared, and each register has seven corresponding lags Fx, Fy, Fz, and Fw. These seven lags are set by the flag set circuit SK of the unit (U1) in the previous stage, and reset by the flag reset circuit R of the unit (U2) in the rear stage. In this embodiment, these flags are not only referenced but also reset via signal line Lll. The interlock unit IUI transmits information from the condition determination circuit C to the signal line L2, which determines whether modification or reference of a specific register in a specific instruction is executed by unit)U1 or unit)U2.
Receive via. This is K, (1) Enitsu in the first part)
The condition of whether or not the subsequent unit modifies or refers to the contents of a storage element that Ul always modifies or refers to in the subsequent specific instruction is the time when the preceding unit can process the preceding instruction. In the following cases, the condition of whether or not the preceding unit modifies or refers to the contents of a storage element that is always modified or referenced by the subsequent unit by the specific instruction that precedes it is the condition that precedes the condition. If the instruction to be executed is determined after the time when the preceding unit can process it, the satisfaction or non-fulfillment of the above condition is detected after the time when the above process can be performed, and if the above condition is not satisfied, the subsequent instruction related to this is determined. It is possible to cancel the suppression of modification or reference in the previous unit.

Specifically, in the case of the relationship shown by the solid line D2, first the instruction 13
The flag Fz is set by the flag set circuit SK at the time when the flag is footch/decoded, but on the other hand, the interlock unit IUI indicates that the unit U2 is processing an instruction to modify the register CRx based on the state of the flag Fx. is detected, and it is noted that the modification of register CRz depends on the contents of register CRx, which will be determined in the future. When the modification of register CRx by instruction IIK is completed, condition judgment circuit C
transmits information regarding the contents of register CRx, which determines whether register CRz is modified, to interlock unit IUIK via signal line L2, and when interlock unit IUI determines that register CRz is not modified by instruction 13, , the register CR that had been set temporarily until then
The flag Fz corresponding to zK is reset and the inhibition of instruction 16 is released. In the figure, this relationship is shown by a dashed line F2.

Also, solid line D3. In the case of the relationship shown by D4, the flag set circuit S registers 7 when the instruction 14 is etched/decoded 7 times.
Lag Fw is set, but on the other hand, interlock unit IUI detects from the state of 7 lag Fx that unit U2 is processing an instruction that modifies register CRx, and sets a specific instruction, in this example, instruction 17. For .18,
This flag is recorded to be ignored depending on the contents of register CRx. When the modification of the register CRx by the instruction IIK is completed, the condition determination circuit C interfaces via the signal line L2 information regarding whether the unit U1 modifies or refers to the contents of the register CRw by the specific instruction 17.18. If the interlock unit IUI determines that these instructions do not modify or refer to the register CRwt in unit U1, the interlock unit IUI executes instructions 17.18 even if the flag Fw is set.
release the suppression. In the same figure, these relationships are indicated by a dashed line F.
3. Indicated by F4. The method by which the condition determination circuit C specifically determines whether or not modification or reference of a particular register is executed in unit U1 or unit U2 in a particular instruction depends on the instruction set. It is also possible to simply use a condition code that reflects the result of operation in U2, such as whether the result of addition is OK or not, and whether or not the contents of the achievable register are OK.

It is essentially unnecessary to place the condition judgment circuit C in the unit U2. In fact, as in the other embodiments shown in FIG. If it is determined only by the contents, it is sufficient for the interlock unit IU2 to have a signal #L3 for referring to the contents of these registers in addition to the signal line Lll. In a specific instruction, a specific register is modified or referenced in unit U1 or unit U2.
Whether or not there is a preceding instruction that affects whether or not it is executed, and whether or not such an instruction has finished executing, in this case can be determined from the state of the flag, and as a result, the specified instruction, the modification or reference of a specific register is in unit U1 or unit U2. Whether or not this is executed can be determined from the contents of the register referenced via this signal line L3. It is also not essential that the signal line Lli has a seven-lag reset function.

In fact, the condition of whether or not the contents of the storage element that the previous unit (U) always modifies or refers to in a specific subsequent instruction is modified or referenced by the subsequent unit (U2) in a specific instruction that follows the preceding instruction. If the unit in the previous stage) is determined after the time when Ul can be processed, the corresponding flag is reset by the reset circuit R when it is detected that the unit in the subsequent stage) U2 is not modified or referenced in the preceding specific instruction. Then, the inhibition of subsequent instructions related to this register can be released.

In each of the above embodiments, instructions 11, 12 . -18 are the instructions fetched in this order, and the ones in parentheses are Ik (registers that affect whether or not Ul refers to; registers that are referenced on the left; registers that affect whether or not Ul modifies or not).

Registers modified by the description on the left Registers that affect whether or not TJ 2 references, registers referenced by the description on the left: U 2
refers to the registers that determine whether or not to be modified, and the registers that are modified as shown on the left). If "," is omitted, it means that there is no register, and if it is written as NOP, it means that the register involved does not exist.

It should be noted that whether or not the contents of a specific register will be modified or referenced by the subsequent unit U2 in a specific instruction (61).
The interlock mechanism of the present invention is applicable even when the conditions of whether or not the unit U1 in the previous stage is modified or referenced in a specific instruction are determined after the time when the unit U1 in the previous stage is able to process the preceding command. can be implemented similarly.

In addition, although registers are shown as examples in each embodiment, the application can be similarly applied to general storage elements, and if both the previous and subsequent units only perform reference, subsequent processing can be performed in the same way as in general pipelining. It goes without saying that there is no need to suppress the command.

〔Effect of the invention〕

As explained above, according to the present invention, there is no need to suppress subsequent deaths for an unnecessarily long period of time, and it is possible to effectively eliminate a wide range of processing units (7) with complex processing contents. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional interlock mechanism. Ul, U2...... front stage, rear stage processing unit), C
Rx. CRy, CRz, CRw-=-register, "xr F
y T F z . Fw...Flag corresponding to each register, S...
... Flag set circuit, R ... Flag reset circuit, TUI, IU2 ... Interlock unit, C ... Condition judgment circuit, Lll ...
・Signal line for flag reference and reset, L2...
...Signal line for condition transmission, L3...Signal line for referencing the contents of the shared register. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In a pipeline system consisting of multiple units, there is a condition as to whether or not a subsequent unit modifies or references the contents of a storage element that is always modified or referenced in a specific subsequent instruction by a unit in the previous stage. When the preceding instruction is determined after the time when the preceding unit can process it, and when the preceding specific instruction causes the subsequent specific instruction to modify or refer to the contents of a storage element that the subsequent specific instruction In the case where the condition of whether or not to modify or refer to a preceding instruction is determined after the time when the preceding unit can process the instruction, the present invention has a function of detecting whether or not the condition is met after the time when the preceding unit can process the instruction. death,
A process tracking type interlock mechanism, characterized in that when the condition is not met, the inhibition of modification or reference in the preceding unit of the subsequent instruction involved in the condition is released.