JPH0322055A - Microprocessor - Google Patents

Abstract

PURPOSE:To prevent the quick degradation of performance due to the occurrence of error by providing plural cache memory areas and using the cache memory area other than the cache memory area where error occurs. CONSTITUTION:Internal states of an instruction cache memory 3 and data cache memory 4 are always monitored by an error detecting circuit 5; and if error occurs, the operation of the cache memory where error occurs is stopped. Simultaneously, the occurrence of error is reported to an address decod er 2 by an error detection signal VED and an address decoding signal is stopped from being distributed to the instruction cache memory 3 and the data cache memory 4 by address signal AD. Both of instruction and data areas of the cache memory where error does not occur are used. Thus, the quick degradation of performance is prevented at the time of the occurrence of error.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microprocessor, and in particular to a microprocessor equipped with a cache memory in which a portion of data in a main memory that is expected to be frequently used is copied in advance. The present invention relates to a microprocessor having a function of stopping the operation of the cache memory when an error occurs in the cache memory.

[Conventional technology]

Conventionally, this type of microprocessor has been controlled to disable the entire cache memory when an error occurs in the built-in cache memory.

This is because if an error occurs in the cache memory, it is difficult to correct the error and re-execute.

[Problem to be solved by the invention]

The conventional microprocessor mentioned above is configured to stop all functions as a cache memory when a single error occurs in the cache memory, so this is the simplest way to deal with the error. The disadvantage of this method is that the performance of the microprocessor rapidly declines.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor that does not completely stop the cache memory function when an error occurs, but leaves the cache memory function partially, thereby preventing a sudden drop in performance.

[Means to solve the problem]

The microprocessor of the present invention includes an address decoder that decodes an address signal and outputs an address decode signal, first and second cache memory areas that perform predetermined processing according to the address decode signal, and an error detection circuit that detects whether an error has occurred in the processing contents of the cache memory area and, when an error is detected, stops the processing operation of the cache memory area on the side where the error is detected; and switching means for supplying the address decode signal only to the cache memory on the side where no error is detected.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment decodes an address signal from an internal address bus l, and supplies an address decode signal corresponding to this address signal to an instruction cache memory 3 and a data cache memory 4 when an error detection signal VED is not input. , when the error detection signal VED is input, the command cache, sea memory 3 and data cache memory 4
an address decoder 2 that supplies an address decode signal to the side of which no error has been detected, and instruction cache memories that are first and second cache memory areas that perform predetermined processing according to the address decode signal from the address decoder 2. 3 and a data cache memory 4,
It is detected whether an error has occurred in the processing contents of the instruction cache memory 3 and the data cache memory 4, and when an error is detected, an error detection signal VED is transmitted to the address decoder 2, and the side where the error has been detected The configuration includes an error detection circuit 5 that stops the processing operation of the cache memory area.

Next, the operation of this embodiment will be explained.

Address signal A during external access to normal operating state
An address decode signal corresponding to D is input from the address decoder 2, and either the instruction cache memory 3 or the data cache memory 4 operates to take in address information and data information from the external bus 10.

The internal states of these instruction cache memory 3 and data cache memory 4 are constantly monitored by an error detection circuit 5, and when an error occurs, the operation of the side where the error occurs is stopped.

At the same time, error detection signal vi to address decoder 2
By notifying the occurrence of an error using D and stopping the distribution of the address decode signal to the instruction cache memory 3 and data cache memory 4 using the address signal AD, the cache memory area on the side where no error has occurred is used for instructions. , and control it so that it can be used for both data and data purposes.

FIG. 2 is a block diagram of a second embodiment of the invention.

While in the first embodiment the address decoder 2 has the function of switching the address decode signal, in the second embodiment the switching means is separated from the address decoder.

．． )-address decoder7. According to the address decode signal D1, the first cache memory 7 normally operates for instructions and the second cache memory 8 operates for data.

When an error is detected in either the first cache memory 7 or the second cache memory 8 by five error detection circuits, the operation of the side where the error is detected is stopped.

At the same time, the normal one is controlled to operate as both instruction and data, but at this time, the switching circuit 6At6
The address decode signal is supplied only to the normal one by B, and half of the normal one is used for instructions, and the other half is used for data, so that the purpose of use is divided.

In this embodiment, even after an error occurs, the instruction cache memory and the data cache memory can be maintained as they are in an independent structure, so there is an advantage in terms of performance of the cache memory system.

〔Effect of the invention〕

As explained above, the present invention provides a plurality of cache memory areas, and when an error occurs in one cache memory area, another cache memory area is used. Since not everything is stopped, the part where the error has occurred can be covered by the normal cache memory area, which has the effect of preventing a sudden drop in performance due to the occurrence of the error.

S decoder, 3...Instruction cache memory, 4
...Data cache decoder, 5,5▲...
...Error detection circuit, 6A+6B...Switching circuit, 7...First cache memory, 8...
...Second cache memory, lO゜゜゜゜゜゜゜external bathrobe

Claims (1)

[Claims] An address decoder that decodes an address signal and outputs an address decode signal, first and second cache memory areas that perform predetermined processing according to the address decode signal, and processing contents of the first and second cache memory areas. an error detection circuit that detects whether an error has occurred and stops the processing operation of the cache memory area on the side where the error is detected when an error is detected; and switching means for supplying the address decode signal only to the cache memory on the side.