JPH0756774A - Watching timer - Google Patents

Abstract

PURPOSE:To reduce power consumption by inhibiting the counting operation of a watchdog timer in a SLEEP mode and enabling the counting operation only when a CPU is in an operating state. CONSTITUTION:When the CPU 1 stops, i.e., a SLEEP signal S2 from a SLEEP flag 2 is '1', an AND gate 20 is closed and the input of a clock signal tphi to a free run counter 4 is inhibited to stop the counting signal phi to a free run counter 4 is inhibited to stop the counting operation of the counter 4. When a reset signal generating circuit 30 is accessed from the CPU 1 by a prescribed procedure, a reset signal generating circuit 30 generates a reset signal S3 to reset the counter 4, and also when the SLEEP signal S2 is switched from '1' to '0', i.e., when an interruption signal IR is inputted and the CPU 1 wakes up and starts operation, generates the reset signal S3 to reset the counter 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watch dog timer for detecting an abnormal loop or runaway of a program in a microcomputer or the like by resetting a counter at a certain fixed cycle, and its operation in particular. It is about control.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional watchdog timer. This watchdog timer is controlled by a central processing unit (hereinafter referred to as CPU) 1 provided in a microcomputer or the like,
A sleep (SLEEP) flag 2 and a reset signal generating circuit 3 are connected to the CPU 1 via an address bus AB and a data bus DB. From CPU1, SLEE
The write signal S1 is input to the P flag 2 and the reset signal generation circuit 3. The interrupt signal IR is input to the SLEEP flag 2, and the SLEEP signal S2 output from the SLEEP flag 2 is input to the CPU 1. The reset signal generation circuit 3 is a circuit that generates a reset signal S3 at a constant cycle based on the write signal S1 from the CPU 1, and the reset signal S3 is a reset input terminal of a counter with reset (for example, free-run counter) 4. It is connected to R. The free-run counter 4 counts the number of clock signals φ input to the clock input terminal CLK, outputs an overflow signal S4 from the overflow output terminal OVF when the count value exceeds a certain value, and resets the reset input terminal R. The counter is reset when the signal S3 is input.

Next, the operation of the watchdog timer shown in FIG. 2 will be described. When the microcomputer is powered on, the clock signal φ is input to the clock input terminal CLK of the free-run counter 4, and when a certain time elapses, the free-run counter 4 overflows and outputs the overflow signal S4 to the overflow output terminal OVF. Output from.
This overflow signal S4 means the runaway of the CPU 1. Therefore, the CPU 1 accesses the reset signal generation circuit 3 so as to reset the free-run counter 4 before it overflows. The reset signal generation circuit 3 generates the reset signal S3 only when the CPU 1 writes predetermined data in a predetermined procedure. It is programmed in advance so that this operation is repeated periodically. For example, if the free-run counter 4 overflows in 2 seconds, the reset operation is repeated every 1 second. CPU 1 to reset signal generation circuit 3 and SLEE
The P flag 2 is accessed by the write signal S1 output from the CPU 1 via the data bus DB and the address bus AB. When "1" is written in the SLEEP flag 2 from the CPU 1 and the SLEEP signal S2 output from the SLEEP flag 2 becomes "1", the CPU 1
Becomes a non-operating state (SLEEP state). Interrupt signal I
When R becomes "1", the SLEEP flag 2 is reset, and the CPU 1 enters the operating state (WAKE UP state).

[0004]

However, in the conventional watchdog timer, even when the CPU 1 is in the SLEEP mode, the watchdog timer is reset (that is, the free-run counter 4 is reset) by the interrupt signal IR. I have to wake up. Therefore, there is a problem that the power consumption of the microcomputer and the like increases, and it is difficult to solve it with a relatively simple circuit configuration and control. The present invention provides a watchdog timer that solves the problem that the above-mentioned conventional technique has with respect to an increase in power consumption due to the reset operation of the watchdog timer.

[0005]

In order to solve the above-mentioned problems, the present invention provides a counter for inputting a clock signal and counting the number thereof, and a reset signal for every constant period under the control of the CPU. In a watchdog timer provided with a reset signal generating circuit for resetting the counter, a prohibiting unit for prohibiting input of the clock signal to the counter during the SLEEP mode of the CPU, and the canceling means when the SLEEP mode is released. And reset means for resetting the counter.

[0006]

According to the present invention, since the watchdog timer is configured as described above, when the CPU is in the SLEEP mode, since the CPU is not running out of control, the prohibition means prohibits the input of the clock signal to the counter. And the SL
The watchdog timer count operation in the EEP mode is prohibited. When the SLEEP mode is released, the reset means resets the counter. Since the reset of the watchdog timer is performed only when the CPU is in the operation state, the power consumption as a whole is reduced. Therefore, the above problem can be solved.

[0007]

1 is a block diagram of a watchdog timer in a microcomputer or the like showing an embodiment of the present invention, in which elements common to those in FIG. 2 of the prior art are designated by common reference numerals. . This watchdog timer differs from the conventional one in that a prohibition means (for example, a 2-input AND gate) 20 for permitting or prohibiting the input of the clock signal φ to the free-run counter 4 is added. In place of the reset signal generating circuit 3, the reset signal generating circuit 30 having a different structure from that of the reset signal generating circuit 3 is provided. The clock signal φ is input to one input terminal of the 2-input AND gate 20, and SLEE is input to the other inverting input terminal.
The SLEEP signal S2 from the P flag 2 is input to
The output terminal of the ND gate 20 is connected to the clock input terminal CLK of the free-run counter 4. The reset signal generation circuit 30 has a function of generating the reset signal S3 based on the write signal S1 from the CPU 1 as in the conventional reset signal generation circuit 3, and also has the SLEEP flag 2
The SLEEP signal S2 from the
It has reset means for generating 3. Next, the operation of the present embodiment will be described, focusing on the differences (a) and (b) between the operations of the watchdog timer of FIG. 1 and the watchdog timer of FIG.

(A) First Difference The free-run counter 4 shown in FIG. 2 is always supplied with the clock signal φ after the power is turned on, regardless of whether the CPU 1 is stopped or operating. Performs count operation. On the other hand, in the present embodiment, when the CPU 1 is stopped (that is, when the SLEEP signal S2 is "1"), AND
The gate 20 prohibits the supply of the clock signal φ to the free-run counter 4. In other words, SL from CPU1
When "1" is written in the EEP flag 2 and the SLEEP signal S2 output from the SLEEP flag 2 becomes "1", the CPU 1 becomes inoperative. At this time, SLEE
Since the P signal S2 is "1", the AND gate 20 is closed and the input of the clock signal φ to the free-run counter 4 is prohibited. (B) Second Difference In the reset signal generation circuit 3 of FIG. 2, the write signal S1 is supplied from the CPU 1 and the reset signal S3 is generated only when the write signal S1 is accessed in a predetermined procedure. In contrast,
In the reset signal generation circuit 30 of the present embodiment, SLEEP
When the SLEEP signal S2 output from the flag 2 is switched from "1" to "0", that is, the interrupt signal IR is input to the SLEEP flag 2 and the CPU 1 causes the WAKE UP.
Then, when the operation is started, the reset signal S3 is generated and the free-run counter 4 is reset.

Since the conventional example and the present embodiment have the above-mentioned differences, the present embodiment has the following advantages. (I) The free-run counter 4 of this embodiment is the CPU 1
Since the AND gate 20 prohibits the input of the clock signal φ during the stop, the counting operation is not performed. Therefore, it is not necessary to wake up the CPU 1 to reset the free-run counter 4 while the CPU 1 is stopped. Therefore, it is not necessary to increase the power consumption, and it is possible to realize a microcomputer with lower power consumption. (Ii) The CPU 1 is released from the SLEEP mode, and the C
When PU1 starts its operation, the free-run counter 4 is once reset by the reset signal S3. Therefore, even when the operation of the CPU 1 is repeated for a short time, the count value of the free-run counter 4 is not accumulated, and the reset operation of the free-run counter 4 by the program is executed by the write signal S1 of the CPU 1 in the free-run mode. The control of the watchdog timer is extremely simple because it is necessary only when the counter 4 continuously operates for the time from "0" to overflow. It should be noted that the present invention is not limited to the above embodiment, and for example, AN
The D gate 20 may be configured by a prohibition unit such as another gate circuit, the free-run counter 4 may be configured by another counter with reset, or another functional block may be added to the circuit of FIG. Can be modified.

[0010]

As described above in detail, according to the present invention, the counting operation of the counter is prohibited by the prohibiting means while the CPU is stopped.
It is not necessary to wake up the CPU to reset the counter while the U is stopped, thereby reducing power consumption. Further, when the CPU's SLEEP mode is released and the CPU starts its operation, the counter is reset once, so that the count value of the counter is accumulated even when the operation of the CPU for a short time is repeated. Never. As a result, the reset operation of the counter based on the control of the CPU by the program is required only when the counter continuously operates for the time from "0" to overflow, so that the control of the watchdog timer is extremely simple. become.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a watchdog timer showing an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional watchdog timer.

[Explanation of symbols]

 1 CPU 2 SLEEP flag 4 Free-run counter 20 AND gate (inhibiting means) 30 Reset signal generation circuit IR interrupt signal S1 write signal S2 SLEEP signal S3 reset signal S4 overflow signal φ clock signal

Claims (1)

[Claims] 1. A counter is provided which inputs a clock signal and counts the number thereof, and a reset signal generation circuit which generates a reset signal at regular intervals under the control of a central processing unit to reset the counter. In the watchdog timer, a prohibiting unit that prohibits the input of the clock signal to the counter in the sleep mode of the central processing unit, and a reset unit that resets the counter when the sleep mode is released are provided. Watchdog timer characterized by the following.