JP2006099654A - Semiconductor circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect an operation abnormality of a processor quickly. <P>SOLUTION: A microcomputer 1 monitors the operation of a CPU 11 and executes recovery processing coping with the case that the abnormality is detected. An abnormality determination part 15 makes abnormality determination by a state transitional signal outputted in response to a state transition by the CPU 11. The abnormality determination part 15 is provided with a counter 151 for counting synchronized with a counter clock and, when the state transitional signal is detected, resets the counter 151. When the abnormality determination part 15 does not detect the state transitional signal but the counter 151 has reached a reference value, the abnormality determination part 15 determines it to be abnormal in processing operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor circuit device, and more particularly, to a semiconductor circuit device that executes circuit operation abnormality determination.

  At present, microcomputers are used not only in computer systems such as personal computers but also in many electronic devices such as home appliances, OA devices, automobiles, and control devices for manufacturing apparatuses. As a functional element, a microcomputer reads out data including an instruction code and an address and controls the entire microcomputer according to the result of instruction execution, an arithmetic processing part that executes arithmetic operations and logical operations, and necessary data A register set for storing data is provided. When implemented as a control device for various devices, it has various peripheral functions in addition to memories such as ROM and RAM. A control unit, an arithmetic processing unit, a register set, and the like are implemented as functional elements in the CPU. The microcomputer sequentially decodes the instruction code included in the program and performs a process according to the instruction code, thereby realizing a desired function.

  The instruction code is fetched from the address indicated by the program counter included in the register set. For example, when the value of the program counter changes due to external noise or the like, there is a problem that the microcomputer accesses an unexpected address and the program execution of the microcomputer runs out of control. For this reason, it is necessary to automatically detect a microcomputer runaway and perform a recovery process corresponding to the runaway. Several methods for detecting runaway have been proposed so far. For example, a runaway can be detected by distributing TRAP instructions in a program stored in the ROM, and a predetermined return program can be executed by TRAP processing.

  In addition, for example, Patent Document 1 discloses one runaway detection method for a microcomputer. The microcomputer disclosed in Patent Document 1 includes a runaway detection counter, and always operates it. When the runaway detection counter overflows, it is determined that runaway occurs and an abnormal signal is output to the CPU. The microcomputer clears the runaway detection counter at a predetermined timing during normal operation. As a result, the runaway detection counter does not overflow during normal operation, and runaway that differs from normal operation can be detected.

Specifically, the microcomputer monitors the execution address of the program, and clears the runaway detection counter if the pre-registered address is executed. Also, when all the peripheral hardware factors of the microcomputer are functioning correctly, the runaway detection counter is cleared. The runaway detection counter is cleared directly by hardware without using software (program). In this way, by clearing the runaway detection counter in hardware, it is possible to prevent the program from accidentally clearing the runaway detection counter during program execution runaway, and to ensure runaway detection when program execution has runaway Can be done.
JP 2004-151446 A

  In the technique of the above-mentioned Patent Document 1, a signal that is a criterion for microcomputer abnormality determination is a signal that is output when the CPU executes a program of a specific address, and is a secondary signal due to an operation in the microcomputer. It was. As described above, since the conventional technique does not monitor a signal directly attributable to the operation of the CPU, it has been impossible to reliably or quickly detect an abnormal operation of the microcomputer. For example, even if the execution of a program is unstable due to a CPU failure, if a signal is output to the extent that a specific address is executed and the counter does not overflow, an abnormality in the CPU can be detected. could not. Alternatively, even when the access time by the CPU is longer than usual due to an abnormality in the memory on the bus, the abnormality cannot be detected as long as the signal is output to the extent that the counter does not overflow.

  The present invention has been made against the background described above, and one object of the present invention is to improve the detection of abnormalities in circuit operation.

  According to a first aspect of the present invention, a processor that operates according to an instruction code and transitions between a plurality of different operation states, and a state signal output from the processor based on the operation state is detected under a predetermined condition. And a recovery processing instruction unit that instructs a predetermined recovery process when the determination unit determines that the state signal has not been detected under a predetermined condition. By using the status signal, an abnormal circuit operation can be detected quickly.

  It is preferable that the state signal is a state transition signal output in response to a transition of the operation state of the processor. Alternatively, it is preferable that the status signal is a fetch signal output in an instruction fetch state of the processor. By using these signals, abnormalities in processor processing can be detected quickly.

  The determination unit determines whether the state signal is detected within a reference time, and the recovery processing instruction unit, when the determination unit determines that the state signal is not detected within the reference time, It is preferable to instruct the recovery process. Thereby, it is possible to quickly detect the stop of the operation of the processor.

  The determination unit includes a reference value storage unit that stores a reference value and a counter that is controlled based on the state signal, and determines the detection of the state signal based on the reference value and the counter value of the counter, Preferably, the semiconductor circuit device further includes a reference value setting unit that changes a reference value stored in the reference value storage unit based on processing of the processor. This makes it possible to detect an appropriate circuit operation abnormality according to the processor processing.

  The determination unit includes a counter that counts according to a count clock and is controlled based on the state signal, and determines whether the state signal is detected before the count value of the counter reaches a predetermined reference value. The semiconductor circuit device preferably further includes a counter control unit that stops the counting of the counter according to a control signal. This makes it possible to detect an appropriate circuit operation abnormality according to the processor processing. It is preferable to further include an instruction execution address holding unit that temporarily holds an instruction execution address held by the processor when the determination unit determines that the state signal is not detected under a predetermined condition. . Thereby, it is possible to resume from the process interrupted after the recovery process.

  A second aspect of the present invention is a semiconductor circuit device, a processor that operates according to an instruction code, a counter that counts according to an input signal, a reference value storage unit that stores a reference value, a count value of the counter, and the reference And a reference value setting unit that changes a reference value stored in the reference value storage unit based on processing of the processor. By changing the reference value based on the processing of the processor, it is possible to detect an appropriate circuit operation abnormality according to the processor processing.

  The counter counts in synchronization with a count clock as the input signal, and is cleared in response to a signal from the processor, and the determination unit has a case where the count value of the counter reaches the reference value It is preferable to determine that the circuit operation is abnormal. Thereby, abnormality detection using a counter can be performed effectively. Preferably, the reference value setting unit changes the reference value based on an access destination of the processor. As a result, it is possible to perform an appropriate abnormality detection according to the processing time of the processor that varies depending on the access destination.

  A third aspect of the present invention is a semiconductor circuit device, in which a processor that executes processing according to an instruction code, a counter that counts according to a count clock, and a count value of the counter reaches a predetermined reference value A determination unit that determines that the processor processing is abnormal, and a counter control unit that stops counting of the counter according to a control signal. As a result, it is possible to more accurately detect abnormalities in processor processing.

  The determination unit includes a reference value storage unit that stores the reference value, and the semiconductor circuit device further includes a reference value setting unit that changes a reference value of the reference value storage unit based on processing of the processor. It is preferable to provide. This makes it possible to detect an appropriate circuit operation abnormality according to the processor processing.

  The determination unit can determine that the processor is operating abnormally when the count value reaches the reference value and the counter overflows. The control signal is preferably a wait signal to the processor. Alternatively, the control signal is preferably a standby signal output by the processor in response to a standby state. By stopping the counting operation with these signals, more accurate abnormality detection can be performed.

  According to the present invention, abnormality detection in circuit operation can be improved.

  Hereinafter, embodiments to which the present invention can be applied will be described. The following description is to describe the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Moreover, those skilled in the art can easily change, add, and convert each element of the following embodiments within the scope of the present invention.

Embodiment 1 FIG.
The microcomputer of this embodiment monitors the operation of a processor (shown as a CPU in this embodiment) and executes a recovery process corresponding to the case where an abnormality is detected. The abnormality of the processor operation is performed by detecting a state signal output from the processor based on the operation state. In this embodiment, a state transition signal output in response to a transition of the operating state of the processor is used as the state signal. By determining the abnormality based on the status signal from the processor, it is possible to quickly detect an abnormal operation of the processor.

  In order to detect abnormalities in processor operation, the microcomputer of this embodiment uses a counter. For example, the counter is cleared based on the status signal of the processor, and when the counter reaches the reference value, it is determined that the operation of the processor is abnormal, and the corresponding recovery process is executed. If the processor state transition is normal, the counter is cleared before the reference value is reached. When the state transition is not normal, the counter reaches the reference value, and an abnormality in the processor operation can be detected. The reference value is changed according to the processing of the processor. Thereby, abnormality detection can be made more appropriate.

  Before describing in detail the abnormality detection in the microcomputer of this embodiment, the outline of the hardware configuration of the microcomputer of this embodiment will be described first. FIG. 1 is a block diagram schematically showing an outline of the hardware configuration of the microcomputer 1 according to this embodiment. The microcomputer 1 includes a CPU 11 that is an example of a processor, a ROM 12 that is a read-only memory, a RAM 13 that can read and write data by specifying an arbitrary address, and a peripheral that interfaces data input and output with peripheral circuits. An I / O circuit 14 is provided. The CPU 11, ROM 12, RAM 13 and peripheral I / O circuit 14 are connected via an internal bus, and each circuit inputs and outputs data such as an instruction code, an address or calculation data and a control signal via the internal bus. To do.

  Further, the microcomputer 1 includes an abnormality determination unit 15 that detects an abnormality in the processing operation of the CPU 11, a monitoring unit 16 that instructs a recovery process based on the detection result of the abnormality determination unit 15, and instruction execution when an abnormality occurs in the CPU 11 operation. An instruction execution address holding unit 17 for storing addresses is provided. The abnormality determination unit 15 monitors the operation of the CPU 11 and outputs an abnormality detection signal to the monitoring unit 16 when an abnormality in the CPU 11 operation is detected. The monitoring unit 16 instructs recovery processing in response to the abnormality detection signal. The instruction for the recovery process is output as an interrupt request or a reset signal.

  The configuration of each circuit element shown in FIG. 1 will be described. The CPU 11 includes circuit blocks such as a register set 111, a control unit 112, an arithmetic processing unit 113, and a bus interface 114. The register set 111 includes a plurality of registers, and temporarily stores instruction codes, addresses, operation data, and the like. The register set 111 includes an accumulator that stores operation data, a program counter that indicates a program execution address, and the like.

  The control unit 112 includes an instruction fetch circuit that fetches an instruction code from the ROM 12 or the like, an instruction decoder that decodes the instruction code, and the like. The control unit 112 reads data including an instruction code and an address from the ROM 12 and the RAM 13 into a register, and controls the entire microcomputer 1 according to the result of executing the instruction. Also, when an interrupt request is received from another circuit, the interrupt processing is controlled according to the interrupt factor. The interruption process is performed by executing an interruption program stored in the ROM 12. The arithmetic processing unit 113 executes numerical operations such as addition and subtraction, logical operations such as AND / OR / NOT, and shift instructions. The bus interface 114 interfaces data and instruction code input / output with other circuits.

  The ROM 12 stores in advance instruction codes and calculation data set by the user. As the ROM 12, a non-volatile memory that retains stored data even when the power is turned off is used. For example, an EEPROM (Electrically Erasable Read-Only Memory) such as a flash memory can be used. The RAM 13 is a volatile storage device, and an SRAM that does not require rewriting, a DRAM that requires rewriting at regular intervals, and the like can be used.

  The abnormality determination unit 15 includes a counter 151 and a compare register 152. The counter 151 counts according to the input count clock. Typically, the count clock is input as a constant frequency signal. The compare register 152 stores the set reference value. The abnormality determination unit 15 compares the value of the counter 151 with the value of the compare register 152. When the value of the counter 151 reaches the reference value, it is determined that the CPU 11 is operating abnormally, and an abnormality detection signal is output. The abnormality determination unit 15 can calculate a reference value by calculation from the value of the compare register 152, or can determine abnormality by calculating the value of the compare register 152 and the value of the counter 151. It is.

  The monitoring unit 16 controls the execution of the recovery process based on the abnormality determination result of the abnormality determination unit 15. When the abnormality determination unit 15 outputs an abnormality detection signal, the monitoring unit 16 instructs execution of the recovery process in response to the abnormality detection signal. For example, the monitoring unit 16 issues an interrupt request to the CPU 11 or outputs an internal reset signal. In response to the interrupt request, the CPU 11 reads a predetermined interrupt program from the ROM 12 and executes recovery processing according to the interrupt program.

  Alternatively, as another aspect of the recovery process, the CPU 11 and the RAM 13 can be selectively reset by a reset signal, or the entire microcomputer 1 can be reset. After the reset, a predetermined initialization process is executed. It is also possible to output an interrupt request to an external circuit, notify the external device of an abnormality of the microcomputer 1 (CPU 11), and input a reset signal from the external device to the microcomputer 1.

  In response to the control signal from the monitoring unit 16, the instruction execution address holding unit 17 temporarily stores the instruction execution address of the CPU 11 when an abnormality is detected. When the monitoring unit 16 obtains the abnormality detection signal from the abnormality determination unit 15, the monitoring unit 16 outputs a control signal to the instruction execution address holding unit 17, and executes the value stored in the program counter of the CPU 11 in response to the control signal. The address holding unit 17 stores it.

  The address stored in the instruction execution address holding unit 17 can be read by an external debugging tool (not shown) and used for debugging, or can be read by the CPU 11 after recovering from an abnormality. By holding the execution address at the time of abnormality detection, analysis (debugging) at the time of abnormality can be made easier. Alternatively, in the return processing from the abnormal state, the execution address at the time of occurrence of the abnormality can be known, so that appropriate return processing can be performed. In addition to the execution address, other data stored in the register set 111 can be stored.

  As described above, when the count value of the counter 151 becomes equal to or greater than the reference value (reaches the reference value), the abnormality determination unit 15 determines that an abnormality has occurred in the operation of the CPU 11. For this reason, when the CPU 11 is operating normally, the value of the counter 151 needs to be cleared (reset to a specified value). The abnormality determination unit 15 clears the counter 151 in response to the clear signal from the CPU 11. In this embodiment, a state transition signal is used as the clear signal. FIG. 2 is a timing chart showing the clear timing of the counter 151. As shown in FIG. 2, the counter 151 counts in synchronization with the input count clock. In this example, the counter counts up at the rising edge of the count clock. When the clear signal is input, the counter 151 is cleared. In this example, the counter value is reset to 0 in synchronization with the rising edge of the clear signal.

  As described above, the microcomputer 1 according to the present embodiment uses a state transition signal representing an operation state transition of the CPU 11 as a clear signal from the CPU 11. The abnormality determination unit 15 monitors the operation state transition of the CPU 11 and clears the counter 151 based on the operation state transition of the CPU 11. As a result, when the state transition signal is not detected within a predetermined reference time, it is determined that the CPU 11 process is abnormal. That is, it is determined that the operation of the CPU 11 is abnormal when the operation of the CPU 11 is stopped and the operation state of the CPU 11 has not changed to the next operation state and the predetermined time has passed.

  A state transition signal representing a change in the operating state of the CPU 11 is input from the CPU 11 to the abnormality determination unit 15. In response to the state transition signal indicating the state transition, the abnormality determination unit 15 clears the counter 151. The counter 151 advances the count until the state transition signal indicates a state transition. When the value of the counter 151 reaches the reference value of the compare register 152, the abnormality determination unit 15 outputs an abnormality detection signal.

  FIG. 3 is a timing chart showing the relationship between the operation state of the CPU 11 and the state transition signal. The CPU 11 of this embodiment executes program instructions by pipeline processing. As shown in FIG. 3, the instruction processing (instruction cycle) is divided into a plurality of processing steps (operation states). “IF (Instruction Fetch)” indicates an instruction fetch, “ID (Instruction Decode)” indicates an instruction decode / register file read, and EX (EXecution) indicates an execution / address generation processing unit. Further, MEM (MEMory access) indicates memory access (read / write), and WB (Write Back) indicates each process (operation state) of writing to the register file.

  Pipeline processing starts the next instruction cycle before the previous instruction cycle ends by performing different processing steps simultaneously. The CPU 11 includes different circuit blocks corresponding to the processes described above, and each circuit block is connected via a pipeline register. Each circuit block performs processing independently. As described above, since the pipelined data path is provided, the CPU 11 can simultaneously execute different processing units in one clock cycle and execute a plurality of instructions in parallel.

  The state transition signal is output in synchronization with the end (or start) of each operation state constituting the pipeline processing by the CPU 11. The state transition signal indicating the state transition is output at a substantially constant cycle while the CPU 11 normally executes the pipeline processing. However, when the processing of the CPU 11 stops due to memory lock or the like, the state transition signal also stops, and the level of the output signal is kept constant without changing. If this state continues for a predetermined time or more, the value of the counter 151 reaches the reference value. As described above, by monitoring the change in the operation state of the CPU 11, it is possible to detect an abnormality according to the operation clock of the CPU 11, and it is possible to quickly detect an abnormality.

  The microcomputer 1 of the present embodiment further changes the reference value stored in the compare register 152 based on the processing of the CPU 11. For example, the memory access (MEM stage in FIG. 3) time varies depending on the response time of the memory (access destination). The memory (access destination) to be accessed is an external device connected to the external bus in addition to the ROM 12 and the RAM 13, or a register of the peripheral I / O circuit 14.

  Since these response times can be different from each other, it is preferable to set the allowable time for stopping the CPU 11 (the time for determining that the CPU 11 operation is abnormal) to an appropriate value according to the access destination. In this embodiment, the CPU 11 or the abnormality determination unit 15 according to the request determines the reference value of the compare register 152 according to the access destination of the CPU 11 and sets the value. As a result, the time until the value of the counter 151 reaches the reference value is changed, and the time from the transition to the current state to the determination of an abnormality without transition to the next state is set to an appropriate time. By having the above configuration, it is possible to set an allowable time for stopping the CPU 11 according to the access destination of the CPU 11, and to improve the detection accuracy of the abnormal operation of the CPU 11.

  The microcomputer 1 according to the present embodiment includes circuits such as the abnormality determination unit 15 and the monitoring unit 16 as internal circuits, but these can also be configured as external circuits. Further, instead of comparing the value of the counter 151 with the reference value of the compare register 152, the abnormality determination unit 15 can output an abnormality detection signal when the counter 151 overflows. Furthermore, the abnormality determination unit 15 can reset the overflow value in accordance with the operation of the CPU 11.

  Further, the abnormality detection of the CPU 11 operation according to the present embodiment can be applied to various types of microcomputers. For example, the present invention can be applied to any type of microcomputer such as an MPU, a peripheral LSI (MPR: Micro Peripheral Unit), a microcontroller, and a DSP (Digital Signal Processor). These points are the same in the following description.

Embodiment 2. FIG.
A microcomputer according to the present embodiment will be described with reference to FIG. Unlike the first embodiment, the microcomputer of this embodiment uses a signal that is always output in each operation state of the processor (processing step in one instruction cycle) as a state signal from the processor. In particular, in the following, an example will be described in which a determination of an abnormal operation of a processor is performed according to a fetch signal in an instruction fetch operation state.

  Further, the microcomputer of this embodiment uses a counter for detecting an abnormality in the processor operation. Unlike the first embodiment, the microcomputer of this embodiment counts up the counter in response to detection of a predetermined state signal, and determines that the processor is operating abnormally if the reference value is not reached within a predetermined time. The corresponding recovery process is executed.

  FIG. 4 is a block diagram schematically showing the outline of the hardware configuration of the microcomputer 2 according to this embodiment. The microcomputer 2 of this embodiment is different from that of the first embodiment in the abnormality determination unit 25 and the counter 251, and other components are the same as those described in the first embodiment. The abnormality determination unit 25 receives a fetch signal output from the CPU 11 to the fetch bus. As the fetch signal, a read clock on the fetch bus, a fetch address, a fetch bus use right acquisition signal, or the like can be used. The abnormality determination unit 25 may not directly monitor the signal on the fetish bus, but may directly input a signal output from the CPU 11 in the instruction fetch state to the abnormality determination unit 25.

  In this example, the counter 251 counts up in response to the fetch signal input from the CPU 11 instead of the count clock. The abnormality determination unit 25 determines whether or not the count value of the counter 251 reaches a predetermined reference value at a predetermined reference time. When the count value reaches the reference value, the abnormality determination unit 25 determines that there is no abnormality in the CPU operation, and clears the counter 251. The cleared counter 251 restarts the counting process in response to the detected fetch signal from the beginning.

  When the count value does not reach the reference value, the abnormality determination unit 25 determines that an abnormality has occurred in the operation of the CPU 11. In this example, when the fetch signal is not detected the reference number within the reference time (that is, when the fetch signal is not detected within the reference time), the abnormality determination unit 25 causes the CPU 11 to malfunction. Judge that there is. As a result, when the instruction fetch process (operation state) is not executed the reference number of times within the reference time, the abnormality determination unit 25 determines that the CPU 11 has an operation abnormality.

  For example, when execution of the CPU 11 is stopped due to a failure of the CPU 11 or a bus lock, the fetch signal of the execution program stops. The abnormality determination unit 25 can detect the execution stop (operation abnormality) of the CPU 11 when the counter value of the counter 251 does not reach the specified value. The recovery process when the CPU 11 abnormality determination unit 25 determines that there is an abnormality is the same as in the first embodiment. As described above, by monitoring the signals output in each operation state of the CPU 11 and determining the operation abnormality of the CPU 11, the operation abnormality of the CPU 11 can be detected quickly.

  In this embodiment, an example of a fetch signal has been described. However, a signal output in another operation state such as instruction decode / register file read and execution / address generation can be used as a state signal. Further, as described in the first embodiment, it is possible to detect abnormality using a counter that operates in accordance with a counter clock. On the other hand, in the first embodiment, it is possible to use a counter that operates in response to detection of a state signal.

  As in the first embodiment, the value of the compare register 152 can be changed according to the processing of the CPU 11. For example, when the fetch signal is temporarily stopped to execute an instruction that requires time for processing, abnormality detection can be made appropriate by changing the value of the compare register 152. Also, the value of the compare register 152 can be changed according to the fetch destination (ROM 11 or RAM 13). It should be noted that it is possible to determine the abnormality of the CPU 11 operation using a plurality of different state signals such as a state transition signal and a fetch signal.

Embodiment 3 FIG.
The microcomputer according to the present embodiment will be described with reference to FIGS. Unlike the first embodiment, the microcomputer of this embodiment includes a mask control unit that masks the count clock input to the counter of the abnormality determination unit. When the mask control unit masks the count clock, the counter stops counting, and the counter can be easily controlled.

  5 is a block diagram schematically showing a schematic configuration of the microcomputer according to the present embodiment. As shown in the figure, the microcomputer 3 includes a mask control unit 31. The mask control unit 31 receives a control signal for controlling the count clock and the mask of the count clock. In this embodiment, as a preferred embodiment, wait signals from the ROM 12, RAM 13 and peripheral I / O circuit 14 are input as control signals. These wait signals are input to the mask control unit 31 via the OR logic 32.

  In addition, the abnormality determination unit 35 outputs an abnormal detection signal in response to the overflow of the counter 351. Other configurations are the same as those of the first embodiment, and detailed description thereof is omitted. As in the first embodiment, the abnormality determination unit 35 includes a compare register 152 and can determine an abnormality in the operation of the CPU 11 by comparing the reference value with the value of the counter 351.

  FIG. 6 is a timing chart showing the relationship between the control signal of the counter 351 and the counter operation in this embodiment. FIG. 6 shows a clear signal from the CPU 11, a count clock input to the mask control unit 31, a mask signal from the mask control unit 31, and a counter operation of the counter 351. The mask control unit 31 has AND logic, and receives a wait signal and a count clock. When the wait signal is input, the mask control unit 31 masks the count clock and sets the mask signal to active. Since the count clock is not input to the counter 351, the counter 351 stops counting. Since the wait signals from the ROM 12, the RAM 13 and the peripheral I / O circuit 14 are input to the OR logic 32, when any one of these circuit elements outputs the wait signal, the wait signal is sent to the mask control unit 31. Entered.

  On the other hand, when no wait signal is input, the mask control unit 31 outputs the input count clock to the counter 351. The counter 351 performs a count process in synchronization with the count clock. When the counter 351 overflows, the abnormality determination unit 35 outputs an abnormality detection signal to the monitoring unit 16.

  When the CPU 11 accesses the memory, the state transition operation of the CPU 11 is stopped until data is input from the memory (RAM 13) to the CPU 11. In the case where the memory access fluctuates due to the unspecified time wait, if the wait time does not cause a problem in the system, the count clock is masked with the wait signal. Accordingly, the counter 351 can count and monitor processing time other than the wait time. As a result, it is possible to effectively monitor processing other than the wait time that has been buried in the shadow of the unspecified wait time.

  For example, when the CPU 11 performs memory access, the CPU 11 acquires the right to use the bus. When the CPU 11 outputs a data request to the memory (RAM 13), the data of the CPU 11 is input from the RAM 13 in response. If the RAM 13 cannot output data immediately in response to a request from the CPU 11, the RAM 13 outputs a wait signal to the CPU 11. While the wait signal is output, the counter 151 stops counting, so that the bus use right acquisition time hidden behind the wait time can be monitored. Alternatively, the counter function can be stopped by masking the count clock to disable the monitoring function. This is useful when you want to stop the monitoring function when debugging.

  In the above example, the wait signal is used to mask the count clock, but in addition to this, a standby signal corresponding to the standby state of the microcomputer can be used. The standby signal is a signal that is input to the microcomputer in order to set the microcomputer 3 in the standby state, or that is output in the microcomputer after the standby state is set. In addition, the count clock can be masked according to the control signal from the external terminal. A standby signal and a control signal from an external terminal are input to the OR logic 32 shown in FIG. As a result, the count clock can be masked in response to these signals, and the monitoring function can be temporarily stopped.

  Alternatively, the count operation of the counter 351 can be stopped at a desired timing by providing the counter 351 with an input of a count permission signal for controlling the count operation. The count permission signal can be used in place of the mask function of the count clock or together with the mask function. In this example, the wait signals from a plurality of circuit elements are input to the OR logic and used, but only the wait signals from one circuit are used, or the signals from the plurality of circuit elements are AND logic. Can also be entered.

It is a block diagram showing typically the hardware constitutions of the microcomputer concerning a 1st embodiment. It is a timing chart which shows the clear timing of the counter concerning a 1st embodiment. It is a timing chart which shows the relationship between the operation state of CPU which concerns on 1st Embodiment, and a state transition signal. It is a block diagram which shows typically the hardware constitutions of the microcomputer which concerns on 2nd Embodiment. It is a block diagram which shows typically the hardware constitutions of the microcomputer which concerns on 3rd Embodiment. 10 is a timing chart showing a relationship between a count operation of a counter according to a third embodiment, a clear signal, and a mask signal.

Explanation of symbols

1 microcomputer, 2 microcomputer,
3 microcomputer, 14 peripheral I / O circuit, 15 counter,
15 abnormality determination unit, 16 monitoring unit, 17 instruction execution address holding unit,
25 abnormality determination unit, 31 mask control unit, 32 OR logic, 35 abnormality determination unit,
111 register set, 112 control unit, 113 arithmetic processing unit,
114 bus interface, 151 counter,
152 Compare register, 251 counter, 351 counter

Claims (15)

A processor that operates according to the instruction code and transitions between different operating states;
A determination unit that determines whether a state signal output from the processor based on the operation state is detected under a predetermined condition;
A recovery process instruction unit that instructs a predetermined recovery process when the determination unit determines that the state signal has not been detected under a predetermined condition;
A semiconductor circuit device.   The semiconductor circuit device according to claim 1, wherein the state signal is a state transition signal output in response to a transition of an operation state of the processor.   The semiconductor circuit device according to claim 1, wherein the state signal is a fetch signal output in an instruction fetch state of the processor. The determination unit determines whether the state signal is detected within a reference time,
The recovery process instruction unit instructs the recovery process when the determination unit determines that the status signal is not detected within the reference time.
The semiconductor circuit device according to claim 1. The determination unit includes a reference value storage unit that stores a reference value and a counter that is controlled based on the state signal, and determines the detection of the state signal based on the reference value and the counter value of the counter,
The semiconductor circuit device further includes a reference value setting unit that changes a reference value stored in the reference value storage unit based on processing of the processor.
The semiconductor circuit device according to claim 1. The determination unit includes a counter that counts according to a count clock and is controlled based on the state signal, and determines whether the state signal is detected before the count value of the counter reaches a predetermined reference value. ,
The semiconductor circuit device further includes a counter control unit that stops counting of the counter according to a control signal.
6. The semiconductor circuit device according to claim 1 or 5.   The apparatus further comprises an instruction execution address holding unit that temporarily holds an instruction execution address held by the processor when the determination unit determines that the state signal is not detected under a predetermined condition. 2. The semiconductor circuit device according to 1. A processor that operates according to the instruction code;
A counter that counts according to the input signal;
A reference value storage unit for storing a reference value;
A determination unit for determining a circuit operation abnormality based on the count value of the counter and the reference value;
A reference value setting unit that changes the reference value stored in the reference value storage unit based on the processing of the processor;
A semiconductor circuit device. The counter counts in synchronization with a count clock as the input signal, and is cleared in response to a signal from the processor,
The determination unit determines that the circuit operation is abnormal when the count value of the counter has reached the reference value;
The semiconductor circuit device according to claim 8.   The semiconductor circuit device according to claim 8, wherein the reference value setting unit changes the reference value based on an access destination of the processor. A processor that executes processing according to an instruction code;
A counter that counts according to the count clock;
A determination unit that determines that the processor process is abnormal when the count value of the counter reaches a predetermined reference value;
A counter control unit for stopping the counting of the counter according to a control signal;
A semiconductor circuit device. The determination unit includes a reference value storage unit that stores the reference value,
The semiconductor circuit device further includes a reference value setting unit that changes a reference value of the reference value storage unit based on processing of the processor,
The semiconductor circuit device according to claim 11.   The semiconductor circuit device according to claim 11, wherein the determination unit determines that the processor is operating abnormally when the count value reaches the reference value and the counter overflows.   The semiconductor circuit device according to claim 11, wherein the control signal is a wait signal to the processor.   12. The semiconductor circuit device according to claim 11, wherein the control signal is a standby signal output in response to a standby state of the processor.

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