JP5331451B2 - Microcontroller - Google Patents

Description

  The present invention relates to a microcontroller including a CPU.

  2. Description of the Related Art Conventionally, a microcontroller that includes a CPU and performs requested interrupt processing and monitors the execution time of the interrupt processing is known.

  For example, in Patent Document 1, a timer operation is started when an interrupt permission signal becomes “0” (interrupt disabled state), and when the elapsed time by the timer exceeds the monitoring time value, the monitoring time excess signal A technique for generating the above has been proposed. According to this technology, it is possible to alert the user and the program by detecting that the interrupt disabled state continues.

In Patent Document 2, the execution time monitoring unit monitors the execution time of each application task whose execution time is set together with the execution priority, and if it detects that the execution time has been exceeded, the priority order changing unit is A technique for lowering the execution priority of an application task that has been started and is currently being executed has been proposed. According to this technique, since the priority of a task in which a failure has occurred is lowered, the system can be operated normally without affecting the execution cycle of other normal tasks.
Japanese Patent Laid-Open No. 2-18626 Japanese Patent Laid-Open No. 5-241906

  In general, in a microcontroller provided with a CPU, when an interrupt request signal is accepted in an interrupt enabled state, an interrupt routine is started and interrupt processing is performed. When this interrupt routine is executed, if another interrupt is enabled, another interrupt can be accepted (this is referred to as a multiple interrupt). On the other hand, if another interrupt is disabled, no other interrupt can be accepted.

  In general microcontrollers, when an interrupt is accepted in the interrupt enable state, the interrupt is automatically disabled. Therefore, to enable multiple interrupts, the interrupt enable operation must be performed explicitly in the interrupt routine by software. It is necessary to do.

  Here, when multiple interrupts are not permitted and processing has been executed for a longer time than planned (for example, when processing cannot escape from the interrupt routine), other interrupt processing is performed. This results in a problem that the performance of the entire system is hindered. In other words, if a response time allowed for a certain process is specified, the entire system will fail if the process is not started within the specified response time after an interrupt occurs. Will occur.

  Therefore, in Patent Document 1, it is proposed to call attention when the elapsed time by the timer exceeds the monitoring time value. However, in Patent Document 1, attention is only given to request a countermeasure by the user or a program, and the microcontroller does not release the interrupt disabled state.

  Also, some microcontrollers receive interrupt processing requests with priorities set for each factor, and interrupt processing having higher priority than interrupt processing being executed by the CPU provided in the microcontroller. Some have an interrupt controller that receives the request and requests the CPU to start the accepted interrupt process when the request is received. In this interrupt controller, when an interrupt service is executed by an interrupt factor having a higher priority, an interrupt having a lower priority than the interrupt factor is not accepted. For this reason, an interrupt factor with a low priority must wait until the interrupt process with a high priority is completed.

  Therefore, for example, if a problem occurs in an interrupt routine with a high priority, and if the problem is longer than expected, or if the processing being executed by the CPU is not able to escape from this routine, the interrupt process with a low priority is performed. As a result, there is a problem that the performance of the entire system is hindered.

  Patent Document 2 proposes a technique for lowering the execution priority of an application task that is currently being executed when the execution time has exceeded. However, even if the priority of the interrupt routine is lowered during the current execution, other interrupt processing cannot be performed as long as the interrupt disabled state continues.

  In view of the above circumstances, an object of the present invention is to provide a microcontroller that can improve the performance of the entire system.

The microcontroller of the present invention that achieves the above object provides:
A microcontroller with a CPU,
An interrupt disabled state in which activation of the requested interrupt processing is prohibited, and an interrupt enable state in which activation of the requested interrupt processing is permitted,
A timer that measures the duration of interrupt processing being executed in the CPU, and an interrupt enable change that changes the CPU from an interrupt disabled state to an interrupt enabled state when the duration measured by the timer exceeds a predetermined value An interrupt control unit for generating a signal is provided.

  The microcontroller of the present invention is configured to change the CPU from the interrupt disabled state to the interrupt enabled state when the duration of interrupt processing being executed in the CPU exceeds a predetermined value. According to this configuration, the CPU can be changed to the interrupt enable state regardless of whether the CPU is in the interrupt disable state or the interrupt enable state. Therefore, for example, when a problem occurs in an interrupt routine that does not permit multiple interrupts, and the CPU enters a state in which it cannot escape from this interrupt routine for a long time, other interrupts can be forcibly permitted. Therefore, the performance of the entire system can be improved.

  Here, it is preferable that a history flag recording unit that can be referred to by software executed by the CPU is further provided, and a flag is set in the history flag recording unit when the interrupt enable change signal is generated.

  In this way, when the interrupt disable state changes to the interrupt enable state, the change can be confirmed by software. Therefore, if interrupt processing has been performed for a long time, it can be determined whether the processing is valid (whether any problem has occurred in the processing).

Also, when receiving a request for interrupt processing having a priority set for each factor and receiving a request for interrupt processing having a higher priority than the interrupt processing being executed in the CPU, the request is accepted, An interrupt controller that requests the CPU to start the accepted interrupt process,
And further comprising an interrupt controller including a priority setting unit that sets the priority so that the priority of the activated interrupt processing is lowered when the duration measured by the timer exceeds the predetermined value. Is preferred.

  When such an interrupt controller is provided, there is a problem in an interrupt routine with a high priority, a problem that is longer than expected, and a process that is being executed by the CPU cannot be escaped from this routine. However, interrupt processing with a low priority can be performed.

  According to the present invention, a microcontroller that can improve the performance of the entire system is provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a microcontroller according to an embodiment of the present invention.

  The microcontroller 1 shown in FIG. 1 includes an interrupt controller 10 and a CPU 20.

  The interrupt controller 10 receives interrupt factor signals IR0, IR1, IR2, and IR3 indicating requests for interrupt processing with priorities set for respective factors. Here, it is assumed that the priority order is higher in the order of the interrupt factor signals IR0, IR1, IR2, and IR3. Although the configuration of the interrupt controller 10 will be described later, the interrupt controller 10 accepts the request when an interrupt factor signal indicating a request for an interrupt process having a higher priority than the interrupt process being executed by the CPU 20 is input. Then, an interrupt request signal INT_ for requesting the CPU 20 to start the accepted interrupt process is output. The interrupt controller 10 outputs data DO to the outside via the data bus.

  The CPU 20 outputs an address signal ADR, a read signal RD, and a write signal WD to the outside. Further, the CPU 20 inputs data DI from the outside via the data bus and outputs data DO to the outside via the data bus. Details of the CPU 20 will be described with reference to FIG.

  FIG. 2 is a diagram showing an internal configuration of the CPU shown in FIG.

  The CPU 20 shown in FIG. 2 includes an interrupt processing unit 21, a control circuit unit 22, a register unit 23, and a calculation unit 24. Control signals CNT such as a read signal RD and a write signal WD are input to the interrupt processing unit 21, the control circuit unit 22, the register unit 23, and the calculation unit 24.

  The interrupt processing unit 21 receives an interrupt request signal INT_ from the interrupt controller 10 shown in FIG. 1 and transmits an interrupt request to the control circuit unit 22 that controls the entire CPU 20.

  The control circuit unit 22 gives an interrupt permission to the interrupt processing unit 21 when it becomes a period during which the interrupt processing can be accepted during the period in which the CPU 20 operates. The interrupt processing unit 21 receives this interrupt permission and outputs an interrupt permission signal INTA_ to the interrupt controller 10.

  The register unit 23 is configured by a storage latch circuit that holds data, and the register unit 23 outputs data according to a program code read in advance to the arithmetic unit 24.

  The arithmetic unit 24 performs a logical operation or an arithmetic operation using the data from the register unit 23 and writes the result back to the register unit 23.

  Note that the address signal ADRS and data DATA required when the CPU 20 reads data from or writes data to an external memory or 1/0 is output from the register unit 23. Further, the internal configuration of the CPU 20 will be described in detail with reference to FIG.

  FIG. 3 is a diagram showing the configuration of the interrupt processing unit and the register unit shown in FIG.

  The interrupt processing unit 21 shown in FIG. 3 includes a flip-flop 21_1, an AND gate 21_2, a measurement timer 21_3 (corresponding to an example of a timer according to the present invention), a comparator 21_4, AND gates 21_5 and 21_6, and an OR gate. 21_7.

  On the other hand, the register unit 23 includes a flip-flop 23_1, an interrupt enable register 23_2, and a set value register 23_3.

  Here, the interrupt permission signal INTA_ shown in FIG. 3 is generated at a portion (not shown) of the interrupt processing unit 21, and the interrupt permission signal INTA_ and the clock signal CLK are input to the flip-flop 21 </ b> _ 1 constituting the interrupt processing unit 21. . The flip-flop 21_1 and the AND gate 21_2 at the next stage constitute a circuit that detects the falling edge of the interrupt permission signal INTA_. The falling edge of the interrupt enable signal INTA_ from this circuit becomes the count start signal COUNT to the measurement timer 21_3, and the duration of the interrupt service is measured by counting the clock of the clock signal CLK by the measurement timer 21_3. .

  On the other hand, an arbitrary value is set in the set value register 23_3 constituting the register unit 23 by an instruction executed by the CPU 20. The comparator 21_4 constituting the interrupt processing unit 21 is a circuit that compares the value of the set value register 23_3 with the value of the measurement timer 21_3. When the two match, the comparator 21_4 outputs a logic “1” (“H” level) as the interrupt enable change signal IEC.

  The interrupt enable register 23_2 constituting the register unit 23 is used to determine whether or not the control circuit unit 22 shown in FIG. 2 accepts the interrupt request signal INT_. Specifically, the interrupt enable register 23_2 shown in FIG. 3 is disabled by the count start signal COUNT generated based on the falling edge of the interrupt enable signal INTA_, and sets the 'L' level as the interrupt enable signal IE. Output. Further, it is enabled by the interrupt enable change signal IEC, and outputs the “H” level as the interrupt enable signal IE. That is, the CPU 20 is in an interrupt enable state when the interrupt enable signal IE of “H” level is output.

  On the other hand, the interrupt enable change signal IEC is output as a “priority change request signal PCR” to the interrupt controller 10 (see FIG. 1). The interrupt enable change signal IEC is input to a circuit composed of AND gates 21_5, 21_6 and OR gate 21_7. An output from this circuit is input to the flip-flop 23_1, and a history flag F (interrupt enable change history flag) is output from the flip-flop 23_1. The flip-flop 23_1 corresponds to an example of a history flag recording unit referred to in the present invention. This history flag F is cleared ('0') when the interrupt permission signal INTA_ becomes active ('L' level), and when the value of the measurement timer 21_3 becomes the same as the value of the set value register 23_3. Set ('1'). By referring to the history flag F, the software can determine whether or not a problem has occurred during the processing in the routine.

  FIG. 4 is a diagram showing a configuration of the interrupt controller shown in FIG.

  The interrupt controller 10 shown in FIG. 4 includes an interrupt request register (IRR) 11, a control circuit 12, a priority order assignment circuit 13, and an interrupt service register (ISR) 14.

  The interrupt request register 11 receives interrupt factor signals IR0, IR1, IR2 and IR3 indicating interrupt processing requests. Note that the priority order of the interrupt factor signals IR0, IR1, IR2, and IR3 is higher in the order of the interrupt factor signals IR0, IR1, IR2, and IR3, as described above. In the interrupt request register 11, when an interrupt request is generated by any one of the interrupt factor signals IR0, IR1, IR2, and IR3, the bit corresponding to the interrupt factor signal is set to '1'. Thereafter, when the control circuit 12 receives the interrupt permission signal INTA_ from the CPU 20, the corresponding bit is reset to '0'.

  In the interrupt service register 14, when the interrupt controller 10 performs an interrupt service, the corresponding bit of the interrupt service is set to “1”. When the service is completed, the corresponding bit is reset to “0”.

  The priority assignment circuit 13 corresponds to an example of a priority setting unit according to the present invention, and sets and assigns priority of interrupt factors.

  The control circuit 12 accepts interrupts, masks interrupt requests, and assigns interrupt services. Also, a function of receiving a priority change request signal PCR from the CPU 20 and changing the priority setting of the priority assignment circuit 13 so that the priority corresponding to the interrupt factor currently in service is relatively lowered. Have.

  Further, the control circuit 12 has a function of outputting the start address (interrupt vector) of the interrupt routine required for the so-called interrupt vector method on the data bus.

  When receiving an interrupt request from the interrupt request register 11, the control circuit 12 refers to the interrupt service register 14 to grasp the interrupt processing (service) being executed in the CPU 20 and uses the priority assignment circuit 13. Whether the priority of the interrupt factor of the request received from the interrupt request register 11 is higher than the priority of the interrupt factor requesting the interrupt processing being executed (in other words, from the interrupt request register 11 It is determined whether or not the priority of the interrupt service due to the interrupt factor of the request is higher than the priority of the interrupt service being executed. When it is determined that an interrupt service request having a higher priority than the interrupt service being executed has been received, the request is accepted, the service is allocated, and an interrupt request signal INT_ is output to the CPU 20. Thereby, an interrupt request is made to the CPU 20. The CPU 20 receives the interrupt request signal INT_, and outputs an interrupt permission signal INTA_ to the control circuit 12 when the interrupt becomes acceptable. In response to this, the control circuit 12 outputs an interrupt vector corresponding to the interrupt factor on the data bus, and sets the corresponding bit of the interrupt service register 14 to “1” for the bit corresponding to the factor to which the service is assigned. To do. In this way, the value of the interrupt service register 14 is updated. In other words, the interrupt service is started when the value of the interrupt service register 14 is updated.

  FIG. 5 is a diagram showing the timing from when the interrupt controller shown in FIG. 4 receives an interrupt request until the interrupt service is started.

  At the first time point, the interrupt request signal INT_ output from the control circuit 12 and the interrupt permission signal INTA_ output from the CPU 20 are both at the ‘H’ level.

  When the control circuit 12 receives an interrupt request from the interrupt request register 11, the control circuit 12 changes the interrupt request signal INT_ from the “H” level to the “L” at the rising edge of the first clock of the clock signal CLK. Change to level. The 'L' level interrupt request signal INT_ is input to the CPU 20.

  Then, the CPU 20 captures the 'L' level interrupt request signal INT_ at the rising edge of the next clock. Further, when the interrupt can be accepted at that time, the CPU 20 changes the interrupt permission signal INTA_ from the ‘H’ level to the ‘L’ level at the rising edge of the next clock.

  In response to this, the control circuit 12 outputs an interrupt vector on the data bus at the rising edge of the second clock.

  Further, at the next rising edge of the clock, the interrupt service register 14 sets the corresponding bit to “1” based on the interrupt factor corresponding to the generated interrupt vector. As a result, the value of the interrupt service register 14 is updated. Further, after a predetermined time, the CPU 20 changes the interrupt permission signal INTA_ from the “L” level to the “H” level.

  Furthermore, the interrupt service is started at the next rising edge of the clock. Further, the control circuit 12 changes the interrupt request signal INT_ from the “L” level to the “H” level at the next rising edge of the clock in response to the interrupt permission signal INTA_ becoming the “H” level. .

  FIG. 6 is a diagram showing an example of an interrupt sequence of the microcontroller shown in FIG.

  Here, as described above, the priority order is higher in the order of the interrupt factor signals IR0, IR1, IR2, and IR3. First, an interrupt factor signal IR1 is generated, and an interrupt process by the interrupt factor signal IR1 is performed. That is, the service state is established by the interrupt factor signal IR1. During this interrupt processing, the interrupt factor signal IR0 is generated. Since the priority of the interrupt factor signal IR0 is lower than that of the interrupt factor signal IR1, the interrupt request by the interrupt factor signal IR0 is not accepted and the service is performed. Absent. In this example, interrupt factor signals IR2 and IR3 are not generated. The interrupt factor signal IR1 is assumed to be long.

  Here, the value of the measurement timer 21_3 (see FIG. 3) matches the value of the set value register 23_3. At this time, the priority change request signal PCR becomes valid, and the priority is changed in the order of the interrupt factor signals IR1, IR2, IR3, IR0. Along with this, service by the interrupt factor signal IR1 is interrupted, and interrupt processing by the interrupt factor signal IR0 is started.

  The interrupt enable register 23_2 is in an enabled state until immediately before the service is started by the interrupt factor signals IR1 and IR0. Therefore, the CPU 20 accepts the interrupt request signal INT_. When the interrupt request signal INT_ is accepted and service by the interrupt factor signals IR1 and IR0 is started, the interrupt enable register 23_2 is disabled. Furthermore, the interrupt enable register 23_2 is enabled when the value of the measurement timer 21_3 matches the value of the set value register 23_3. Thereafter, the interrupt state is disabled when the interrupt processing by the interrupt factor signal IR0 is started.

  As described above, in the microcontroller 1 of this embodiment, for example, when a problem occurs in an interrupt routine that does not permit multiple interrupts, and the CPU 20 falls into a state where it cannot escape from the interrupt routine for a long time, low priority is given. Ranking interrupts can be allowed. Therefore, the performance of the entire system can be improved.

  In the present embodiment, the example in which the measurement timer is provided in the CPU has been described. However, the present invention is not limited to this, and the measurement timer may be provided in the interrupt controller. A timer for measuring the duration of interrupt processing may be provided in either the CPU or the interrupt controller.

It is a figure which shows the structure of the microcontroller of one Embodiment of this invention. It is a figure which shows the internal structure of CPU shown in FIG. FIG. 3 is a diagram illustrating a configuration of an interrupt processing unit and a register unit illustrated in FIG. 2. It is a figure which shows the structure of the interrupt controller shown in FIG. FIG. 5 is a diagram illustrating timings from when an interrupt request is received until an interrupt service is started by the interrupt controller shown in FIG. 4. It is a figure which shows an example of the interruption sequence of the microcontroller shown in FIG.

Explanation of symbols

1 Microcontroller 10 Interrupt Controller 11 Interrupt Request Register 12 Control Circuit 13 Priority Assignment Circuit 14 Interrupt Service Register 20 CPU
DESCRIPTION OF SYMBOLS 21 Interrupt processing part 21_1, 23_1 Flip-flop 21_2, 21_5, 21_6 AND gate 21_3 Measurement timer 21_4 Comparator 21_7 OR gate 22 Control circuit part 23 Register part 23_2 Interrupt enable register 23_3 Setting value register 24 Calculation part

Claims (2)

A microcontroller with a CPU,
An interrupt disabled state in which activation of the requested interrupt processing is prohibited, and an interrupt enable state in which activation of the requested interrupt processing is permitted,
A timer that measures the duration of interrupt processing being executed in the CPU, and an interrupt enable change that changes the CPU from an interrupt disable state to an interrupt enable state when the duration measured by the timer exceeds a predetermined value An interrupt control unit that generates a signal, and a history flag recording unit that can be referred to by software executed by the CPU, and sets a flag in the history flag recording unit when the interrupt enable change signal is generated A microcontroller characterized by When receiving a request for an interrupt process having a priority set for each factor and receiving a request for an interrupt process having a higher priority than the interrupt process being executed in the CPU, the request is accepted and the CPU receives the request. An interrupt controller that requests activation of the accepted interrupt processing,
And further comprising an interrupt controller including a priority setting unit for setting the priority so that the priority of the activated interrupt processing is lowered when the duration measured by the timer exceeds the predetermined value. The microcontroller according to claim 1.

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