CN109933549B - Interrupt controller suitable for RISC-V treater - Google Patents
Interrupt controller suitable for RISC-V treater Download PDFInfo
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Abstract
The present invention relates to an interrupt controller suitable for RISC-V processors. The interrupt controller of the invention uses AHB-Lite protocol to communicate with the processor, can receive interrupts of various forms, compare the interrupt source with interrupt request by the comparator, select the interrupt source with the largest request response priority, and then send interrupt notice to the processor; the interrupt controller supports interrupt nesting and can continuously send interrupt notification to the processor in the interrupt execution process of the processor according to the nesting priority of the interrupt source, so that a task with higher nesting priority can be quickly responded; the interrupt controller has a plurality of configurable registers, which is convenient for users to dynamically change the functions of the interrupt controller according to actual requirements. The interrupt controller of the present invention is suitable for managing the external interrupt signal of RISC-V processor and has high flexibility and expansibility.
Description
Technical Field
The present invention relates to the field of computers, and more particularly, to an interrupt controller suitable for RISC-V processors.
Background
The RISC-V instruction set is produced in the Berkeley division of California university in 2010, and is characterized in that the RISC-V instruction set is open-source and free, and anyone can design own chips by using the RISC-V instruction set without paying high authorization cost. The instruction set defines 3 types of interrupts: external interrupts, timer interrupts, and software interrupts. The timer interrupt and the software interrupt belong to the internal interrupt of the processor, and the interrupt source is a timer or a certain instruction in the processor; external interrupts typically come from various peripherals connected to the processor, such as external timers, GPIOs, watchdog, serial port and SPI, among others.
Since the processor has only one external interrupt input signal, interrupts generated by various peripheral devices must be processed by the interrupt controller to enter the processor. The interrupt system, one of the most complicated control systems in a processor, is very important in improving the performance of the processor, the response speed to peripheral devices, the power consumption ratio, and the like. The RISC-V privileged document describes a Platform Level Interrupt Controller (PLIC), but it contains only some of the most basic functions, lacking much of the design details; the RISC-V fund also does not make hard rules that the RISC-V processor must implement PLIC. In the design of many open-source RISC-V processors, the specific implementation of an interrupt controller is rarely involved, and most designs only implement the functions of a kernel part. Furthermore, this also reduces the real-time performance of the processor to some extent, since the RISC-V instruction set specifies that interrupt nesting is not supported by default.
Disclosure of Invention
In order to solve the defect that the prior interrupt controller based on the RISC-V processor has single function, the invention provides an interrupt controller suitable for the RISC-V processor.
In order to realize the purpose, the technical scheme is as follows:
an interrupt controller suitable for RISC-V processor, including communication module, interrupt source gate module, interrupt source edge counter, interrupt source enable register, interrupt source nesting priority register, interrupt source response priority register, nesting priority threshold register, response priority threshold register, interrupt event counter, interrupt notification register; the communication module is respectively connected with an interrupt source gate module, an interrupt source edge counter, an interrupt source enabling register, an interrupt source nesting priority register, an interrupt source response priority register, a nesting priority threshold register, a response priority threshold register, an interrupt event counter and an interrupt notification register;
the communication module is used for sending the read signal or the control signal to the interrupt source gate module, the interrupt source edge counter, the interrupt source enable register, the interrupt source nesting priority register, the interrupt source response priority register, the nesting priority threshold register, the response priority threshold register, the interrupt event counter and the interrupt notification register when the processor needs to read the current state of the rest of modules or sends the control signal to set the working modes of the rest of modules; when the processor sends a response signal or a completion signal to the interrupt controller, the communication module is responsible for sending this signal to the interrupt notification register.
The interrupt source gate module is responsible for converting interrupt signals sent by different types of external interrupt sources into interrupt signals in a uniform form;
the interrupt source edge counter is responsible for recording the times of interrupt requests sent by each interrupt source;
the interrupt source enabling register is used for judging whether the interrupt source can send an interrupt notification to the processor or not;
the interrupt source nesting priority register is used for storing nesting priority of the interrupt source;
an interrupt source response priority register for storing a response priority of the interrupt source;
a nesting priority threshold register for storing a nesting priority threshold set by the processor;
a response priority threshold register for storing a response priority threshold set by the processor;
an interrupt event counter for recording the number of interrupts nested by the processor;
and the interrupt notification register is used for recording the interrupt source sequence number of the interrupt notification which is finally sent to the processor after multiple comparisons.
Preferably, the interrupt source gate module supports 4 kinds of triggering of interrupt signals, including low level triggering, high level triggering, falling edge triggering, and rising edge triggering.
Preferably, in the interrupt source edge counter, when the interrupt source gate module is configured to be edge-triggered, the count number of the counter is increased by 1 every time a corresponding edge is received.
Preferably, in the interrupt event counter, the processor increments the count number of the counter by 1 each time it receives an interrupt notification sent by the interrupt controller; each time an interrupt completion signal is sent to the interrupt controller, the count number of the counter is decremented by 1.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention can detect interrupt signals generated by peripheral equipment in various forms, and can record the generation times of the interrupt signals triggered by the edges, thereby facilitating the processor to acquire the detailed information of the peripheral equipment.
2. The invention can control each interrupt source independently by changing the configuration registers of a plurality of modules, and has very high flexibility.
3. The invention supports interrupt nesting and ensures the stability and the real-time performance of an interrupt response system.
Drawings
FIG. 1 is a block diagram of the overall architecture of a system of an interrupt controller and a RISC-V processor.
Fig. 2 is a schematic diagram illustrating connection between each module and a communication module inside the interrupt controller.
Fig. 3 is a schematic diagram of state transition of the interrupt source gate module.
Fig. 4 is a functional schematic diagram of an interrupt source gate module.
FIG. 5 is a diagram of an interrupt source priority register.
FIG. 6 is a process diagram of an interrupt controller sending an interrupt notification to a processor.
Fig. 7 is a flowchart of the overall operation of the interrupt controller.
FIG. 8 shows a possible register address mapping in example 3.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent;
the invention is further illustrated below with reference to the figures and examples.
Example 1
As shown in fig. 1 and 2, the present embodiment provides an interrupt controller adapted to a RISC-V processor, which communicates with the processor using the AHB-Lite protocol.
As shown in fig. 1, an interrupt signal sent by an external interrupt source to a processor is first input to an interrupt controller and processed by the interrupt controller, and then the interrupt controller sends an interrupt notification signal to the processor. The processor sets the working mode of the interrupt controller according to the actual running condition by sending a control signal which accords with an AHB-Lite protocol to the interrupt controller. When the interrupt controller sends an effective interrupt notification signal to the processor, if the processor can receive the interrupt notification, a response signal is sent to the interrupt controller; after the processor runs a particular interrupt handler, a completion signal is sent to the interrupt controller. The control signal, the response signal and the completion signal all change the operating state of the interrupt controller.
As shown in fig. 1, there may be theoretically any number of external interrupt sources that the interrupt controller can receive, but should incorporate resource limitations of the hardware when implemented. The interrupt controller of the present embodiment is capable of receiving 32 external interrupts. Further, RISC-V specifies that the interrupt source with an interrupt number of 0 is a reserved interrupt, indicating "no possible interrupt", so that in practice there are only 31 external interrupts that the interrupt controller can receive, and the valid interrupt number starts from 1.
As shown in fig. 2, the communication module in the interrupt controller transmits a control signal, a response signal and a completion signal to other designated modules according to the difference of the processor access addresses. If other modules connected with the communication module are bidirectional arrows, the modules indicate that the configuration registers in the modules can be read and written; if the arrow is a one-way arrow, the configuration register in the module is readable and non-writable.
Example 2
As shown in fig. 3 and 4, the interrupt source gate in this embodiment has 3 operating states:
a1: idle state, when the interrupt source gate does not receive any valid external interrupt signal. In this state, if a valid external Interrupt signal is received, an Interrupt Pending register (IP) is set to 1, and the state a2 is entered.
A2: and a waiting response state, wherein the interrupt source gate receives a valid external interrupt signal, the IP is 1, but the processor does not send a response signal to the interrupt controller, namely the processor cannot receive the external interrupt signal passing through the interrupt source gate. In this state, if a response signal sent by the processor is received, IP is set to 0, and state a3 is entered.
A3: a to-do state, in which the external interrupt signal through the interrupt source gate has been received by the processor, but the processor has not yet processed this interrupt, i.e. has not yet sent a done signal to the interrupt controller. In this state, if a completion signal sent by the processor is received, state a1 is entered.
As shown in fig. 4, the interrupt source gate module supports 4 types of triggering of the interrupt signal: low level triggering, high level triggering, falling edge triggering, and rising edge triggering. The trigger mode of the 32 external interrupts can be selected with 4 interrupt source gate module trigger mode configuration registers (LOW _ LEVEL, HIGH _ LEVEL, fault _ EDGE, RISING _ EDGE). For example, setting RISING _ EDGE [14] to 1, LOW _ LEVEL [14], HIGH _ LEVEL [14], and FALLING _ EDGE [14] to 0, when the interrupt source with sequence number 14 sends a RISING EDGE signal to the corresponding interrupt source gate, it will be converted into an interrupt request signal meeting the specification. In general, the functions of level triggering and edge triggering should not be turned on at the same time.
As shown in fig. 4, when the interrupt trigger mode is triggered at a high (low) level, the continuous high (low) level will only send one interrupt request to the interrupt controller. Assume scenario 1: at time T1, when an external interrupt source sends a high (low) level to the interrupt controller, the interrupt source gate successfully receives the high (low) level, the IP is set to 1, but the processor cannot receive the interrupt immediately; at time T2, the external interrupt source sends a low (high) level to the interrupt controller, that is, cancels the interrupt request, and since the IP can be set to 0 only by the response signal sent from the processor to the interrupt controller, the IP remains 1; the IP valid at time T3 sent the interrupt notification to the processor to be received by the processor and the processor sent a response signal to the interrupt controller, but in practice the external interrupt source would not have required the processor to process this interrupt notification, so the processor would actually enter the interrupt routine incorrectly at this point. In order to avoid executing unnecessary interrupt processing programs, when the processor receives an interrupt notification from an interrupt source in a high (low) level trigger mode, it should first check whether an interrupt request is actually generated by a peripheral device connected to the interrupt source, and then determine whether the interrupt processing program is actually required to be executed.
As shown in fig. 4, when the interrupt trigger mode is triggered by a rising (falling) edge, each time the interrupt source gate receives a valid rising (falling) edge, the edge counter is incremented by 1 to record the number of times that the external interrupt source in this operation mode sends an interrupt request to the interrupt controller within a certain time. As shown in fig. 4, the edge counter of each interrupt source is 4-bit, and can record interrupt requests sent by the peripheral device for 15 times at most. When the interrupt source gate is operating in state A1, the IP will be set to 1 as long as the edge counter value is not 0, even if the peripheral device does not send a valid rising (falling) edge to the interrupt source gate. When the processor receives an interrupt notification for this interrupt source, the edge counter is decremented by 1. When the processor modifies the trigger mode configuration register of an interrupt source gate by sending a control signal, the hardware will automatically clear the corresponding edge counter since the previously recorded value has no meaning.
Example 3
As shown in fig. 5, 6, 7 and 8, each interrupt source in this embodiment has its own nested priority register and response priority register, which are 4-bit, and at most 16 kinds of priorities are supported, and a larger priority number means a higher priority. Nesting priority of 0 means "nesting impossible", and response priority of 0 means "interruption impossible". When a plurality of interrupt sources set corresponding IP to 1 at the same time, only the interrupt source with the highest response priority can send the interrupt notification to the processor, if the response priorities of two or more interrupt sources are the same, the interrupt source with the smaller sequence number is selected to send the interrupt notification to the processor. Further, only interrupt sources with response priorities greater than a response priority threshold can send interrupt notifications to the processor. A response priority threshold of 15 indicates that all interrupts are masked; a response priority threshold of 0 indicates that all interrupts are not masked. Further, as shown in fig. 6, even if the response priority of the interrupt source selected by the comparator is not greater than the response priority threshold, the value of the interrupt source notification register is modified to the sequence number of the interrupt source, so that the processor can actively read the value of the interrupt source notification register without receiving an interrupt notification from the interrupt controller.
As shown in fig. 6, if one or more of the interrupt source gates has an operating state a3, it indicates that the processor is processing the interrupt notification of these interrupt sources. The comparator compares the nesting priorities of these interrupt sources and selects the maximum value to store in the nesting priority threshold register. When a new interrupt source sets its corresponding IP to 1, the comparator compares the nesting priority of the interrupt source with the nesting priority threshold. If the nesting priority of the interrupt source is greater than the nesting priority threshold, it is allowed to send a new interrupt notification to the processor and modifies the interrupt source sequence number stored in the interrupt notification register. Furthermore, the nesting priority threshold register can be automatically modified by the output of the comparator when the processor sends a response signal to the interrupt controller, and can also be modified by a control signal sent by the processor so as to meet special requirements.
After the interrupt controller issues an interrupt notification to the processor, if the processor is able to receive the interrupt notification, a response operation is performed by sending a read command to an interrupt notification register in the interrupt controller. After receiving the response signal from the processor, the interrupt controller returns the interrupt source sequence number stored in the interrupt notification register to the processor, and the processor can determine which interrupt processing function is to be executed. Meanwhile, the interrupt controller will change the working state of the interrupt source gate corresponding to the interrupt source sequence number from A2 to A3 and clear the corresponding IP. If the interrupt source sequence number returned to the processor by the interrupt controller is 0, no interrupt notification is indicated.
Further, if the processor completes the interrupt processing function of a certain interrupt source, a completion signal needs to be sent to the interrupt controller, and the specific implementation manner is to write the sequence number of the interrupt source corresponding to the executed interrupt processing function into the interrupt notification register. After receiving the write command, the interrupt notification register changes the operating state of the interrupt source gate corresponding to the interrupt source sequence number from A3 to a1, i.e., allows the interrupt source to initiate the next interrupt request through the interrupt source gate. Further, when the processor executes a high priority interrupt, the IP of a plurality of low priority interrupt sources in the interrupt controller may be 1, so that after the processor writes an interrupt source sequence number to the interrupt source notification register, that is, after sending the completion signal, the value of the interrupt source notification register changes to the sequence number of a low priority interrupt source and does not change to 0. Therefore, after the processor sends the completion signal and before the processor exits from a certain interrupt processing function, the processor can read the value of the interrupt source notification register again, if the value is 0, the processor can normally exit, and if the value is not 0, other interrupt processing functions are selected to be executed according to the read interrupt source sequence number. Therefore, the push and pop operations which need to be executed when the interrupt processing function is entered and exited are greatly reduced, and the real-time performance of the system is improved.
To record the number of currently nested interrupt layers, the interrupt counter is incremented by 1 each time the processor sends a response signal to the interrupt controller and decremented by 1 each time the processor sends a completion signal to the interrupt controller. The processor may read the value of the interrupt counter as needed to determine the nesting status of the current multiple interrupts.
As shown in fig. 7, a complete interrupt request flow is as follows:
B1. if the interrupt source gate is in the A1 state, the interrupt source initiates an interrupt request through the interrupt source gate, the hardware automatically sets the IP to 1, the working state of the interrupt source gate is changed from A1 to A2, and the subsequent interrupt is shielded by the gate.
B2. According to the arbitration mechanism, the interrupt source meeting the condition is selected to send an interrupt notification to the processor.
B3. After the processor receives the interrupt notification, if it can, it issues a read command to the interrupt source notification register to obtain the interrupt source sequence number that caused the interrupt notification. Meanwhile, the interrupt controller changes the working state of the corresponding interrupt source gate from A2 to A3 and clears the IP.
B4. And the processor selects to enter a certain interrupt processing program according to the read interrupt source sequence number.
B5. After the processor executes the interrupt handler, it sends a write command to the interrupt source notification register, where the written data is the interrupt source sequence number read in B3. After receiving the write command, the interrupt controller changes the operating state of the corresponding interrupt source gate from A3 to a 1.
In summary, the processor configures the operating mode of the interrupt controller by modifying the values of different registers in the interrupt controller, so that each 32-bit register of the interrupt controller should be memory address mapped. The interrupt controller of this embodiment is capable of receiving 32 external interrupts and therefore one possible register address mapping is shown in figure 8.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (4)
1. An interrupt controller suitable for RISC-V processor is characterized by comprising a communication module, an interrupt source gate module, an interrupt source edge counter, an interrupt source enabling register, an interrupt source nesting priority register, an interrupt source response priority register, a nesting priority threshold register, a response priority threshold register, an interrupt event counter and an interrupt notification register; the communication module is respectively connected with an interrupt source gate module, an interrupt source edge counter, an interrupt source enabling register, an interrupt source nesting priority register, an interrupt source response priority register, a nesting priority threshold register, a response priority threshold register, an interrupt event counter and an interrupt notification register;
the communication module is used for sending the read signal or the control signal to the interrupt source gate module, the interrupt source edge counter, the interrupt source enable register, the interrupt source nesting priority register, the interrupt source response priority register, the nesting priority threshold register, the response priority threshold register, the interrupt event counter and the interrupt notification register when the processor needs to read the current state of the rest of modules or sends the control signal to set the working modes of the rest of modules; when the processor sends a response signal or a completion signal to the interrupt controller, the communication module is responsible for sending the signal to the interrupt notification register;
the interrupt source gate module is responsible for converting interrupt signals sent by different types of external interrupt sources into interrupt signals in a uniform form;
the interrupt source edge counter is responsible for recording the times of interrupt requests sent by each interrupt source;
the interrupt source enabling register is used for judging whether the interrupt source can send an interrupt notification to the processor or not;
the interrupt source nesting priority register is used for storing nesting priority of the interrupt source;
an interrupt source response priority register for storing a response priority of the interrupt source;
a nesting priority threshold register for storing a nesting priority threshold set by the processor;
a response priority threshold register for storing a response priority threshold set by the processor;
an interrupt event counter for recording the number of interrupts nested by the processor;
and the interrupt notification register is used for recording the interrupt source sequence number of the interrupt notification which is finally sent to the processor after multiple comparisons.
2. An interrupt controller suitable for RISC-V processor as claimed in claim 1, wherein said interrupt source gate module supports 4 kinds of interrupt signal triggers including low trigger, high trigger, falling edge trigger and rising edge trigger.
3. An interrupt controller suitable for a RISC-V processor as claimed in claim 1, wherein in said interrupt source edge counter, when the interrupt source gate module is configured for edge triggering, the count of the counter is increased by 1 each time a corresponding edge is received.
4. An interrupt controller suitable for RISC-V processor as claimed in claim 1, wherein in said interrupt event counter, the processor increments the count number of the counter by 1 each time it receives the interrupt notification sent from the interrupt controller; each time an interrupt completion signal is sent to the interrupt controller, the count number of the counter is decremented by 1.
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| CN110865969B (en) * | 2019-11-05 | 2022-05-31 | 中国人民解放军国防科技大学 | Method and device for supporting inter-processor interrupt communication of extensible processor |
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| KR100313939B1 (en) * | 1998-12-05 | 2001-12-20 | 김영환 | Interrupt Controller |
| JP4151198B2 (en) * | 1999-06-23 | 2008-09-17 | 株式会社デンソー | Interrupt controller and microcomputer |
| US7043582B2 (en) * | 2002-09-06 | 2006-05-09 | Intel Corporation | Self-nesting interrupts |
| CN1277161C (en) * | 2003-12-12 | 2006-09-27 | 中兴通讯股份有限公司 | Programmable interrupt controller |
| GB0423094D0 (en) * | 2004-10-18 | 2004-11-17 | Ttp Communications Ltd | Interrupt control |
| US7788434B2 (en) * | 2006-12-15 | 2010-08-31 | Microchip Technology Incorporated | Interrupt controller handling interrupts with and without coalescing |
| CN102063335B (en) * | 2009-11-13 | 2014-04-02 | 大唐移动通信设备有限公司 | Interrupt controller and method for processing interrupt of multi-core processor shared device |
| JP5507317B2 (en) * | 2010-04-12 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | Microcomputer and interrupt control method |
| CN103544125B (en) * | 2012-07-12 | 2017-02-22 | 深圳市中兴微电子技术有限公司 | Interrupt control method, interrupt processing method, interrupt controller and processor |
| CN103676727A (en) * | 2013-11-27 | 2014-03-26 | 南京国电南自美卓控制系统有限公司 | Preemptible and nestable interrupt control method based on embedded chip |
| CN103617137B (en) * | 2013-11-29 | 2016-09-07 | 暨南大学 | The interrupt control unit of a kind of compatible 8051 IP kernels and control method thereof |
| US10031771B2 (en) * | 2015-06-15 | 2018-07-24 | Nxp Usa, Inc. | Multiple processor core interrupt priority levels |
| CN105094976A (en) * | 2015-10-09 | 2015-11-25 | 天津国芯科技有限公司 | Interrupt control method and interrupt controller |
| CN107015931A (en) * | 2016-01-27 | 2017-08-04 | 三星电子株式会社 | Method and accelerator unit for interrupt processing |
| CN108595256B (en) * | 2018-03-20 | 2020-12-29 | 武汉市聚芯微电子有限责任公司 | Method for realizing interrupt nesting by adopting software based on RISC-V architecture chip |
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