JPH05282256A - Intra-processor message communicating method - Google Patents

Abstract

PURPOSE:To provide a intra-processor message communicating method by which the performance of an entire system including the precedence of an emergency communication can be improved. CONSTITUTION:At the time of connecting the plural processors, each processor uses a cache communication bus 50 connecting each processor different from a command system bus, for a specific shared memory, and operates a intra- processor communication. Message buffers 32, 33, 34, and 35 for the intra- processor message communication to which an access can be directly attained from the cache communication bus 50 are provided on each processor, and the precedence of each message buffer 32, 33, 34, and 35 is decided according to the emergency of the intra-processor communication. An interruption processing for the recognition of the processors only by the sample window of a specific cycle time is generated from each message buffer 32, 33, 34, and 35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processors are indirectly connected by a common bus, and particularly, information is exchanged among the plurality of processors and one task is allocated to the plurality of processors. Therefore, the present invention relates to an interprocessor message communication method in a tightly coupled multiprocessor system that exhibits high performance.

[0002]

2. Description of the Related Art As a conventional multiprocessor system, a shared memory area having a fixed capacity in the system is used, and a fixed address area having a shared memory is used. There is a tightly-coupled multiprocessor system in which message data is written in an area, a processor that wants to receive a message executes interrupt processing, and the processor on the receiving side reads the address area again to execute inter-processor message communication. It was

[0003]

In inter-processor message communication in a conventional tightly coupled multiprocessor system, processing is performed using a fixed address area in the shared memory area, and therefore, it is necessary to perform the processing twice or more. However, if the number of bus masters exceeds a certain number, the load of the system bus increases and the response of the message communication between the processors deteriorates. In addition, when a message communication between a plurality of processors is executed for one processor, the receiving processor cannot determine which message communication has a high urgency, so that a fixed priority order is set. Since the processing requested by the issuing processor is executed based on the above, there are many cases where service is provided to inter-processor message communication with low urgency depending on the reception timing, and system performance such as inter-processor message communication with high urgency occurs. However, the response of the process that contributes to the system deteriorates, and the performance of the entire system deteriorates.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an inter-processor message communication method which improves the inconveniences of the conventional example, and particularly improves the performance of the entire system including the priority reason of emergency communication. To aim.

[0005]

According to the present invention, when a plurality of processors are connected, a cache communication bus for connecting each processor to a specific shared memory system, which is different from the common system bus, is provided. It uses the inter-processor message communication, and each processor has several sets of message buffers for inter-processor message communication that can be directly accessed from the cache communication bus. Prioritization is performed according to the degree of urgency, and a method is adopted in which the message buffer causes an interrupt process for causing the processor to recognize only in a sample window of a cycle time unique to each message. This aims to achieve the above-mentioned object.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
It will be explained based on. FIG. 1 shows an example of a computer system in which a plurality of processors are connected and a device driver or an application performs parallel processing in thread units on an operating system compatible with distributed processing multiprocessors. In FIG. 1, the processor 1 is connected to a cache memory 7 and a message communication control unit 4 via an internal cache bus 10. The cache memory 7 is connected to a shared memory system 3 via a common system bus 26.
0, processor board 1 via cache communication bus 25
7 and the cache memory 9 on the processor board 18.

The shared memory system 30 is composed of a D-RAM and has a sufficient memory capacity for accommodating an operating system kernel section and general application programs. Cash memory 7, 8,
9 is mounted in order to reduce competition of the shared memory system 30 and improve system performance, and is composed of a static RAM operating at high speed. Similarly, the processor 2 is connected to the cache memory 8 and the message communication control unit 5 via the internal cache bus 11,
The cache memory 8 is connected to the common system bus 26. The processor 3 is connected to the cache memory 9 and the message communication control unit 6 via the internal cache bus 12, and the cache memory 9 is connected to the common system bus 26.

The magnetic tape device 29, the hard disk device 28, the key input device 27, and other I / O adapters are all connected by a common system bus 26. The common system bus 26 is arbitrated by the common system bus adjusting device 31. The internal cache buses 10, 11, 12 and the cache communication bus 25 and the cache systems 7, 8, 9 are composed of high-speed devices with a small electrical load, and operate with a high-speed clock synchronized with the processor clock. The OS and other application programs executed by the respective processors are all shared memory system 30 and cache memory 7, which are connected by the common system bus 26,
8 and 9 run.

FIG. 2 shows details of the message communication control section mounted on each processor board. The message communication control unit includes a processor interrupt control unit 48, message buffers 32, 33, 34 and 35 and a time counter 4.
0, 41, 42, 43, count set register 36,
37, 38, 39, count comparators 44, 45, 46,
47, each message buffer can be directly written from a processor on another processor board via the cache communication bus 50.

The message buffers are prioritized with respect to inter-processor message communication processing, and the message buffers 32 and 3 are arranged in descending order of priority.
The order is 3, 34, 35. Time counter 40,4
1, 42, and 43 constantly perform increment count by the processor clock, and count set registers 36, 37, and
When the values are the same as 38 and 39, the pulse from the count comparator is input to the processor interrupt control unit 48.
When the processor interrupt control unit 48 recognizes that the processor has accepted the interrupt, the time counter is reset and the increment count is restarted from the initial value (0). The processor interrupt control unit 48 monitors the pulse output of the count comparators 44, 45, 46, 47 and uses the pulse output as a trigger to enable the processor interrupt signal 49 for the processor to generate an interrupt.

Then, when the processor responds to an interrupt, it controls the output enable of each message buffer from another processor and inputs the interprocessor communication message to the processor through the internal cache bus 50. Further, the set values of the respective time counters can be rewritten via the internal cache bus 50 by prohibiting interrupt processing during system startup and system operation, and can be changed according to system settings. it can.

The count set value differs depending on the message buffer, and here, the count set registers 36, 37, 38, 39 are arranged in the ascending order of the set value. That is, if the time counters are arranged in descending order of the pulse output frequency, the message buffers 32, 3 are arranged.
The order is 3, 34, 35. Here, when the processor 1 executes a certain program on the shared memory system,
To find a processor with a low load in the system, and to prepare an environment in which a program can be executed by multiple processors, start dividing the program into threads that can be executed in parallel.

When the processor 1 detects that the load state of the processor 2 is low, the processor 1 instructs the processor 2 to execute an inter-processor message via the cache communication bus 50 in order to cause the processor 2 to execute several threads in the divided threads. Issue a communication. In this case, when the thread executed by the processor 2 has the lowest priority as compared with the thread executed by the processor 1, the processor 1 determines that the message buffer for inter-processor message communication mounted on the board of the processor 2 is used. Among them, the message is written in the message buffer 35 having the lowest priority. In this case, since the pulse generation setting value of the count set register 39 attached to the message buffer 35 is very large, for example, if the pulse generation setting value is 100000 at the processor clock 100 [MHz] (cycle time 10 [ns]), the processor The time until the interrupt for 2 occurs is in the range of 10 [ns] to 1 [ms], and the average interrupt service time showing the average value is 500.
[Μs].

When the priority of the thread executed by the processor 2 is high, the processor 1 has the highest priority message buffer 32 among the message buffers for inter-processor message communication mounted on the board of the processor 2. Write a message to. In this case, since the pulse generation setting value of the count set register 36 is small, for example, in the case of 1000, the time until the interrupt to the processor 2 occurs is in the range of 10 [ns] to 10 [μs]. , The average interrupt service time is 5 [μs]. Similarly, the inter-processor message communication is issued from the processor 1 to the processor 3, and 10 [μs] after that, the processor 2 to the processor 3 issue the message communication.
If the inter-processor message communication issued by the processor 1 is low in urgency, and the inter-processor message communication issued by the processor 2 is high in urgency, the processor 1 is the processor 3 board. The message is written in the message buffer 38 having a slightly lower priority. After that, the data is written from the processor 2 to the message buffer 32 having the highest priority on the processor 3 board.

When the count value of the time counter 42 corresponding to the message buffer 34 at the time of writing a message of the processor 1 is 5000 and the count value of the time counter 40 corresponding to the message buffer 32 at the time of writing a message of the processor 2 is 500, The count value of both when the message of the processor 2 is 60 is displayed by the time counter 42.
At 00, the time counter 40 is 500. That is, the message from the processor 1 is processed by the processor 3 because the count value of the time counter 42 becomes 10,000.
It is after [μs], and the message from the processor 2 is processed by the processor 3 after 5 [μs] when the count value of the time counter 40 reaches 1000. Here, the processing time of message communication between processors with low urgency requested from the processor 1 to the processor 3 is 1 [m
s], the inter-processor message communication from the processor 1, which has a high degree of urgency, will be serviced 995 [μs] earlier than when interrupts are input in the order in which they are issued.

[0016]

As described above, according to the present invention,
Interprocessor communication messages written to high priority message buffers are more likely to be processed before low priority messages, and urgent interprocessor message communication may be delayed by lower priority messages. The number of processors is extremely small, which makes it possible to distribute the processor capacity of a multiprocessor system according to the priority of message communication between processors, and as a result, it is possible to improve the overall performance of the entire system. An inter-message communication method can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of a message communication control unit in FIG.

[Explanation of symbols]

 1,2,3 Processors 4,5,6 Message communication control unit 7,8,9 Cache memory 10,11,12 Internal cache bus 13,14,15 Interrupt signal 16,17,18 Processor board 19,20,21 Common Bus request signal 22, 23, 24 Common bus permission signal 25 Cache communication bus 26 Common system bus 30 Shared main memory 31 Common bus arbitration device 32, 33, 34, 35 Message buffer 36, 37, 38, 39 Count set register 40, 41, 42, 43 Time counter 44, 45, 46, 47 Count comparator 48 Processor interrupt control 49 Processor interrupt signal 50 Cache communication bus 51 Processor clock

Claims (1)

[Claims] 1. In a multiprocessor system in which a plurality of processors are indirectly connected by a common system bus in the system, a message buffer for interprocessor message communication is provided on each processor board, and each message buffer is provided. An inter-processor message communication method characterized in that the priority is defined in descending order of urgency, and the processor capacity is appropriately allocated according to the priority of communication processing.