JPH08339308A - Digital processor - Google Patents

Abstract

PURPOSE: To prevent the accidents, the breakage of parts, etc., which are caused by the abnormality of a microcomputer and an automobile, an industrial machine, etc., including the microcomputer and to improve the system reliability by providing a single-chip microcomputer, etc., that can prevent the runaway caused by occurrence of the abnormality without using any external parts. CONSTITUTION: A microcomputer MC, etc., is provided with a clock controller CLACK. The controller CLACK receives an abnormality detection signal TD from a watchdog timer or the writing of a complete stop control register RSTP by the instruction of a CPU and selectively fixes an internal signal CG at a low level to stop the operation of a clock generation circuit CLKG and to completely stop the operation of the MCU, etc. The complete stop state of the MCU can be canceled only by a power ON reset signal POR that is acquired in a power supply reapplication state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital processing device, for example, a single-chip microcomputer incorporated in an automobile or an industrial machine, and a technique particularly effective for improving reliability when an abnormality occurs. Is.

[0002]

2. Description of the Related Art There are single-chip microcomputers incorporating various modules such as a central processing unit, memory and analog-digital conversion circuit, and there are automobiles and industrial machines incorporating such microcomputers. In these application fields, a so-called fail-safe function is important, which prevents the influence from spreading to the entire system even when some kind of abnormality occurs, and a watchdog that detects an abnormality and stops its operation is used in microcomputers. A timer or the like is provided.

[0003]

In the conventional microcomputer, the abnormality detection signal output from the watchdog timer is used as a so-called normal reset generation condition, and the microcomputer, that is, the central processing unit thereof, is the abnormality detection signal by the reset. The operation is restarted after the recovery of. For this reason, if the conditions for detecting an abnormality by the watchdog timer are not recovered, the system will be in a runaway state, and in the case of automobiles and industrial machinery, it will cause serious consequences such as worst life and damage to parts such as motors. May be caused. In order to deal with this, a method of continuously inputting a reset signal from an external terminal may be considered, but external parts are required for the microcomputer, and the effect of making a single chip is impaired.

An object of the present invention is to provide a digital processing device such as a single-chip microcomputer capable of preventing runaway when an abnormality occurs without requiring external parts. Another object of the present invention is to prevent accidents and damages to parts when an abnormality occurs in a single-chip microcomputer and the like, and automobiles and industrial machines including the same, and to improve system reliability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a single-chip microcomputer or the like incorporated in an automobile, an industrial machine, or the like selectively stops the operation of the clock generation circuit upon receipt of an abnormality detection by a watchdog timer or writing of a predetermined register by an instruction from a central processing unit. In addition to providing a clock controller to put the microcomputer, etc. into a completely stopped state,
It is possible only by the power-on reset signal when the power is turned on again.

[0007]

According to the above means, when an abnormality occurs, the operation of the microcomputer or the like can be completely stopped until the operating power supply is turned off and on again. A digital processing device such as a microcomputer capable of preventing runaway can be realized. As a result, it is possible to prevent accidents and damages to parts when an abnormality occurs in the single-chip microcomputer and the like, and automobiles and industrial machines including the single-chip microcomputer, and improve the reliability of the system.

[0008]

1 is a block diagram showing an embodiment of a single-chip microcomputer MCU to which the present invention is applied. 2 shows a circuit configuration diagram of an embodiment of the clock controller CLKC included in the microcomputer MCU of FIG. Further, FIG. 3 shows a state transition diagram of an embodiment of the microcomputer MCU of FIG. 1, and FIG. 4 shows a transition condition diagram of the embodiment. Based on these drawings, the configuration and operation of the microcomputer MCU and the clock controller CLKC of this embodiment and their characteristics will be described. The circuit elements of FIG. 2 and FIG.
The circuit elements that make up each block of the
T (metal oxide semiconductor field effect transistor. In this specification, MOSFET is a generic term for an insulated gate field effect transistor).
It is formed on one semiconductor substrate such as single crystal silicon. The single-chip microcomputer MCU of this embodiment is incorporated in an automobile, an industrial machine or the like, and functions as a control device for the same.

In FIG. 1, the microcomputer MCU of this embodiment has a so-called stored program type central processing unit CPU as its basic constituent element. The central processing unit CPU may be, but not limited to, an internal bus IB.
Read only memory ROM, random access memory RAM, analog / digital conversion circuit A /
D, watchdog timer WDT, timer circuit TIM
And serial communication interface SC
I is bound. A predetermined clock signal CLK is supplied from the clock generation circuit CLKG to each unit of the microcomputer MCU including the central processing unit CPU, and the microcomputer MCU further controls a clock controller for controlling the operation of the clock generation circuit CLKG. CLKC and microcomputer MC at power on
A power-on reset circuit POR for resetting each part of U to the initial state.

An internal signal PR is supplied from the central processing unit CPU to the watchdog timer WDT, and its output signal, that is, the abnormality detection signal TD, is supplied to the clock controller C.
Supplied to LKC. In addition, the clock generation circuit CLKG
One input terminal is coupled to one electrode of the crystal oscillator XTAL via the external terminal EXTAL, and the other input terminal is supplied with the clock output signal CG of the clock controller CLKC. The other electrode of the crystal oscillator XTAL is coupled to the clock controller CLKC via the external terminal XTAL. Power-on reset circuit P
The OR is supplied with a power supply voltage VCC and a ground potential VSS, which are operating power supplies of the single-chip microcomputer MCU, via external terminals VCC and VSS, respectively.
The output signal, that is, the power-on reset signal POR,
It is supplied to the clock controller CLKC. The clock controller CLKC further includes a central processing unit CPU
To complete stop control register RSTP (first register)
Output signal RSTP and mode control register RCM
An output signal RCMD of D (second register) is supplied,
The output signal, that is, the normal reset signal RS is supplied to each unit of the microcomputer MCU including the central processing unit CPU.

Here, the central processing unit CPU performs a step operation according to a user program stored in the read-only memory ROM, executes a predetermined arithmetic processing, and controls / controls each unit of the microcomputer. In this embodiment, the central processing unit CPU comprises an instruction-writable complete stop control register and a mode control register, the output signals RSTP and RCMD of which are:
As described above, it is supplied to the clock controller CLKC. Further, the internal signal PR indicating the program execution status of the central processing unit CPU is constantly monitored by the watchdog timer WDT and is used for abnormality detection of the microcomputer MCU.

Next, the read-only memory ROM comprises, for example, a mask ROM having a predetermined storage capacity,
It stores programs and fixed data necessary for controlling the central processing unit CPU. Random access memory RAM
Is, for example, a static RA having a predetermined storage capacity.
The processing result of the central processing unit CPU, control data, etc. are temporarily stored. Further, the analog-digital conversion circuit A / D converts an analog input signal input from various external sensors into a digital signal of a predetermined bit and transmits it to the central processing unit CPU or the like via the internal bus IBUS. The timer circuit TIM is a clock generation circuit C
Time is measured according to the clock signal supplied from PG, and serial communication interface SC
I supports high speed data transfer between, for example, a serial input / output device coupled to the outside of the microcomputer and a random access memory RAM.

On the other hand, the watchdog timer WDT monitors the internal signal PR output from the central processing unit CPU, and in response to the fact that the internal signal PR is not formed over a predetermined time, in other words, the central processing unit CPU. In response to the instruction fetch not being performed for a long period of time, an abnormality of the central processing unit, that is, the microcomputer is detected, and its output signal, that is, the abnormality detection signal TD is selectively set to high level. Further, the power-on reset circuit POR monitors the potentials of the power supply voltage VCC and the ground potential VSS supplied via the external terminals VCC and VSS, and outputs its output signal, that is, the power-on reset signal at the beginning when the operating power is turned on. POR is temporarily set to a high level for a predetermined period. Watchdog timer WD
The abnormality detection signal TD by T and the power-on reset signal POR by the power-on reset circuit POR are supplied to the clock controller CLKC.

The clock controller CLKC includes a so-called set-reset type flip-flop FF1, as shown in FIG. The output signal of the OR gate OG1 is supplied to the set input terminal S of this flip-flop FF1, and the power-on reset signal P from the power-on reset circuit POR is supplied to its reset input terminal.
OR is supplied. The inverted output signal QB of the flip-flop FF1 is supplied to one input terminal of an AND gate AG1, and the other input terminal of the AND gate AG1 is connected to the crystal oscillator XTA via the external terminal XTAL.
L is coupled to one electrode. The output signal of the AND gate AG1 is supplied to one input terminal of the clock generation circuit CLKG as the clock output signal CG.

At one input terminal of the OR gate OG1,
The output signal RSTP of the complete stop control register RSTP of the central processing unit CPU is supplied to the other input terminal from the watchdog timer WDT to the N channel MO.
The abnormality detection signal TD is supplied via the SFET N1.
The abnormality detection signal TD is further supplied to the N-channel MOSFET.
It is supplied to one input terminal of the OR gate OG2 via N2. The reset signal RST is supplied to the other input terminal of the OR gate OG2 via the external terminal RST, and the output signal thereof is supplied to each unit of the microcomputer MCU as a normal reset signal RS. MOSFET N1
The output signal RCMD of the mode control register RCMD of the central processing unit CPU is supplied to the gate of the
An inverted signal from the inverter V1 is supplied to the gate of TN2.

From these facts, the flip-flop FF
1 is that the predetermined stop condition is satisfied and the output signal of the OR gate OG1 is set to the high level. In other words, the abnormality detection signal TD of the watchdog timer WDT is set to the high level and the mode control register of the central processing unit CPU is set. When the output signal RCMD of the RCMD is turned to the high level to turn on the MOSFET N1, or the complete stop control register RST of the central processing unit CPU
When the output signal RSTP of P is set to the high level, it is selectively set, and the power-on reset signal POR output from the power-on reset circuit POR is set to the high level, in other words, the single-chip microcomputer. When the operating power of the MCU is turned off and then turned on again, the MCU is selectively brought into the reset state.

When the flip-flop FF1 of the clock controller CLKC is in the reset state and its inverted output signal QB is at the high level, the external terminal XTAL becomes
Clock generation circuit CLKG via AND gate AG1
It becomes the shape combined with. Therefore, the clock generation circuit C
The LKG is coupled to the crystal oscillator XTAL via the external terminals XTAL and EXTAL to be in an oscillating state, generates a clock signal CLK having a frequency corresponding to the natural frequency of the crystal oscillator XTAL, and supplies it to each part of the microcomputer MCU. Supply. As a result, the microcomputer M
The CU is in a normal operation state and performs a synchronous operation according to the clock signal CLK.

On the other hand, when the flip-flop FF1 of the clock controller CLKC is set and the inverted output signal QB thereof is set to the low level, the AND gate AG1.
Output signal is fixed at a low level, and the clock generation circuit CLKG is separated from the crystal oscillator XTAL to stop the oscillation operation. Therefore, the microcomputer MC
U becomes a so-called complete stop state, and flip-flop F
The operation is completely stopped until F1 is reset, that is, until the operating power supply is turned off and then turned on again to set the power-on reset signal POR to the high level.

Next, the output signal of the OR gate OG2, that is, the normal reset signal RS, is output when the high-level reset signal RST is input via the external terminal RST or by the watchdog timer WDT.
When D is set to the high level and MOSFET N2 is turned on in response to the low level of the output signal RCMD of the mode control register of the central processing unit CPU, it is selectively set to the high level. When the normal reset signal RS is set to the high level, the microcomputer MCU is normally reset and each part thereof is reset to the initial state. As a result, the abnormality detection signal TD output from the watchdog timer WDT is also reset to the low level, so that the central processing unit CPU waits for the normal reset signal RS to return to the low level, restarts the operation, and enters the normal operation state. Return.

That is, the microcomputer MCU of this embodiment has the following arrangements as shown in FIGS.
Since the condition 5 is satisfied, that is, the mode control register RCMD of the central processing unit CPU is in the set state, its output signal RCMD is set to the high level, and the watchdog timer WDT detects the abnormality of the central processing unit CPU to detect the abnormality detection signal TD. Is set to a high level, or when the condition 6 is satisfied, that is, the set instruction from the central processing unit CPU sets the complete stop control register RSTP to a set state and its output signal RSTP is set to a high level, selectively. The normal operation state transits to the complete stop state, and the operation is completely stopped. In this complete stop state, the condition 2 is satisfied, that is, the reset signal RST is set to the high level via the external terminal RST, or the condition 3 is satisfied, that is, the mode control register RCMD of the central processing unit CPU is reset. Therefore, the output signal RCMD is set to the low level, the watchdog timer WDT detects the abnormality of the central processing unit CPU, and the abnormality detection signal TD is set to the high level, so that the normal reset is not canceled. When the condition 4 is satisfied, that is, when the operating power of the microcomputer MCU is turned off and then turned on again to set the power-on reset signal POR to the high level, it is not released.

As a result, a microcomputer capable of preventing a runaway state at the time of occurrence of an abnormality can be realized without the need for external parts, whereby an abnormality occurs in the microcomputer and automobiles and industrial machines including the same. It is possible to prevent accidents and damages of parts at the time and improve the reliability of the system.

The reset signal RST, the abnormality detection signal TD, and the output signal RCM of the mode control register RCMD
D, output signal RSTP of complete stop control register RSTP
Also, when both the power-on reset signal POR is set to the low level, the state of the microcomputer MCU is not changed and the normal operation state or the complete stop state is continued. Further, the reset state of the microcomputer MCU is unconditionally released upon the fall of the normal reset signal RS, and transits to the normal operation state.

The effects obtained from the above embodiments are as follows. That is, (1) The operation of the clock generation circuit is selectively performed by a single-chip microcomputer or the like incorporated in an automobile, an industrial machine, or the like, when an abnormality is detected by a watchdog timer or a predetermined register is written by an instruction from a central processing unit. In addition to providing a clock controller that can stop the operation, this complete stop state can be released only by the power-on reset signal when the power is turned on again. In the meantime, the effect that the operation of the microcomputer or the like can be completely stopped is obtained. (2) According to the above item (1), it is possible to realize a digital processing device such as a single-chip microcomputer capable of preventing runaway when an abnormality occurs without requiring external parts. (3) The above items (1) and (2) prevent accidents and damages to parts when an abnormality occurs in a microcomputer or the like, an automobile or an industrial machine including the same,
The effect is that the reliability of the system can be improved.

The invention made by the inventor of the present invention has been specifically described based on the embodiments, but the invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the watchdog timer WDT and the power-on reset circuit POR may be provided as an integrated circuit separate from the microcomputer MCU. Also,
The microcomputer MCU can be provided with other various modules, and its block configuration and bus configuration are not limited by this embodiment. In FIG. 2, the control for bringing the microcomputer MCU into a completely stopped state is performed by a clock generation circuit C which is constantly brought into an operating state.
This can also be performed by selectively transmitting the output signal of the LKG, that is, the clock signal CLK to each unit of the microcomputer MCU according to the output signal of the flip-flop FF1. The logic configuration of the clock controller CLKC can take various embodiments, and the abnormality detection signal TD, the power-on reset signal POR, the logic level of the output signal of each register, and the like are also arbitrary. The condition for completely stopping the microcomputer MCU can be set arbitrarily.

In the above description, the invention mainly made by the present inventor is applied to a single-chip microcomputer incorporated in an automobile, an industrial machine, or the like, which is the field of application in which the background is applied.
The present invention is not limited to this, and can be applied to, for example, similar microcomputers and microprocessors incorporated in various digital systems. The present invention
It can be widely applied to a digital processing device having at least a fail-safe function and a device or system including such a digital processing device.

[0026]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a digital processing device such as a single-chip microcomputer incorporated in an automobile or an industrial machine receives a failure detection by a watchdog timer or a predetermined register is written by an instruction from a central processing unit to selectively operate the clock generation circuit. By providing a clock controller to stop the operation and put the microcomputer etc. into a complete stop state, and by making it possible to release this complete stop state only by a power-on reset signal when the power is turned on again, when an abnormality occurs,
Since the operation of the microcomputer etc. can be completely stopped until the operating power is turned off and then on again, a digital processing device such as a microcomputer which can prevent runaway when an abnormality occurs without requiring external parts. Can be realized. As a result, it is possible to prevent accidents and damages to parts when an abnormality occurs in the microcomputer and the like, and automobiles and industrial machines including the same, and improve the reliability of the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a microcomputer to which the present invention is applied.

2 is a circuit configuration diagram showing an embodiment of a clock controller included in the microcomputer of FIG.

FIG. 3 is a state transition diagram showing an embodiment of the microcomputer shown in FIG.

FIG. 4 is a transition condition diagram showing an embodiment of the microcomputer shown in FIG.

[Explanation of symbols]

MCU: Single-chip microcomputer, CP
U ... Central processing unit, IBUS ... Internal bus, ROM ...
... Read-only memory, RAM ... Random access memory, A / D ... Analog-digital conversion circuit, WDT
...... Watchdog timer, TIM ...... Timer circuit, S
CI: Serial communication interface, POR: Power-on reset circuit, CLKC:
Clock controller, CLKG ... Clock generation circuit, XTAL ... Crystal oscillator. N1 to N2 ... N-channel MOSFET, V1 ... Inverter, OG1 to OG
2 …… OR gate, AG1 …… and (AN
D) Gate, FF1 ... Set-reset type flip-flop.

Claims (4)

[Claims] 1. A digital processing apparatus, which can be brought into a completely stopped state which cannot be recovered by a normal reset in response to occurrence of a predetermined stopped condition. 2. The complete stop state is released only by a power-on reset signal formed by temporarily stopping the supply of operating power and then supplying it again. Digital processing device. 3. The digital processing device is a single-chip microcomputer, and the stop condition includes:
The digital processing device according to claim 1 or 2, wherein the detection of abnormality by the watchdog timer and the writing to the first register by an instruction from the central processing unit are included. 4. The abnormality detection by the watchdog timer is regarded as a condition for generating the complete stop state selectively when the second register is in the set state, and a condition for generating a normal reset when the second register is in the reset state. The digital processing apparatus according to claim 3, wherein the digital processing apparatus is a digital processing apparatus.