JPH03201040A - Watchdog timer - Google Patents

Abstract

PURPOSE:To improve the detecting accuracy of runaway and to improve the safety by resetting this watchdog timer when all bits are set in each timing with the use of a register. CONSTITUTION:A buffer (register) 9 consists of two bits, and 1 is latched by a latch 3 when 1 is written into the bit 1 with a 1st access given to the buffer 9. Then the program of a CPU part 6 proceeds to the next step, and 1 is set to a latch 4 with the release of the buffer 9. When 1 is written to the bit 0 with a 2nd access given to the buffer 9, a gate 5 is activated and an F/F 7 is set at 1 by a CLK1. The output of the F/F 7 clears a counter 2. The inverted output of the F/F 7 clears both latches 3 and 4, and the F/F 7 is reset by the next CLK1. Then the clear of the counter 2 is canceled. When the program has the runaway and does not perform the preceding operations, the counter 2 has the overflow and resets the part 6. Thus the runaway detecting accuracy and the safety are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a watchdog timer, and particularly to a watchdog timer that prevents a microcomputer from running out of control.

(Prior Art) Conventionally, a watchdog timer has been configured as shown in FIG.

In Figure 5 of the drawing, when RESO is at a high level, TC
The voltage of R5T1 is O, and R5T1 is zero. When RESO goes low, capacitor c1 is charged and the potential increases,
A predetermined first level is detected and R3T1 is set to 1. W
When a signal comes to D, it returns to the predetermined first level, and if no signal comes to WD, the potential continues to rise, and when it reaches the predetermined second level, R5T1 is set low and the CPU (Cen
A watchdog reset function was implemented to reset the RAIP Processing Unit.

[Problem to be solved by the invention]

However, in the conventional example, a boat is required to reset the watchdog timer, and since elements C and R are used for oscillation of the watchdog timer, the time accuracy is poor, and there is sufficient margin. There is a problem in that the watchdog timer must be reset by the program, and there is also a problem in that the watchdog reset instruction must be inserted in many places in the program.

For this reason, a proposal has been made to provide a timer composed of a counter on the same chip as the microprocessor and use its output as a watchdog timer interrupt signal.

There was a problem in that the previously proposed watchdog timer's accuracy 1 function for detecting runaway needs to be further improved.

This invention was made to solve the above-mentioned problems, and in a microprocessor with a built-in watchdog timer, the watchdog timer is reset using a register and each bit is set at a different timing. An object of the present invention is to obtain a watchdog timer that can increase the accuracy and safety of runaway detection by setting the watchdog timer and detecting it when the watchdog timer is completely set.

(Means for solving problems) Therefore, in this invention, the CPU.

Same chip as RAM, ROM, timing generation circuit, etc.
A watchdog timer formed on the chip (hereinafter referred to as this chip), which counts using the clock generated by the timing generation circuit, and when a predetermined value is reached, the clock
a counting means for issuing a reset interrupt to the PU;
A register that can be accessed from a PU, and count clearing means that determines a value to be set by the CPU in a plurality of bits of the register and clears the counting means when the plurality of bits are set according to a predetermined procedure. The purpose of this invention is to achieve the above objective by using a watchdog timer.

(Function) The watchdog timer according to the present invention uses a counting means to count using a clock generated by a timing generation circuit, and when a predetermined value is reached, a reset interrupt is issued to the CPU. Then, the count clearing means determines the values to be set by the CPU in the plurality of bits of the register, and when the plurality of bits are set according to a predetermined procedure, the counting means is cleared.

〔Example〕

Hereinafter, four embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of a watchdog timer and its peripheral parts according to a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a third embodiment of the present invention. Fig. 4 is a block diagram of a fourth embodiment of the present invention.

First, a first embodiment of the present invention will be described with reference to FIG.

In Figure 1 of the drawing,! is a timing generator that generates the overall timing clock of this chip, 2 is a counter for the watchdog timer, 3 and 4.8 are latches, 7 is an F/F, and 9, 10, and 11 are C, respectively.
A buffer accessed by the CPU via the PU bus,
5, 12゜13, 14, 15 are gates, 6 is R
OM (Read-only tnernary),
RAM (Random-accessme)
It is a CPUfi3 with 7A and CPU: 7A. It is assumed that the buffer 9 is normally low and the buffer 10 is normally low.

Next, the operation of the first embodiment will be explained using FIG.

First, after the power is turned on, the timing generator 1 starts oscillation using an external oscillator made of crystal or ceramic, a capacitor, etc., and generates each timing clock. At this time, the reset terminal R5T2 is in a low reset state, and the counter 2 is cleared through the gate 12, the CPU section 6 is cleared through the gate 13, the latch 8 is cleared through the gate 15, and the latch 3. Latch 4. Clear each of F/F7.

Next, when the reset terminal R5T2 becomes high, the clear state is canceled and each part starts operating. CLKI causes the counter 2 to count up, and the CPU section 6 operates from the reset state according to the program stored in the ROM. During the program, instructions to write 1 to the buffer 9 are interspersed to prevent the counter 2 from overflowing. However, for some reason, the program in part 010 6 goes out of control and stops accessing buffer 9.
Counter 2 overflows and through gate 13,
The 010 unit 6 is reset and the 010 unit 6 restarts from the reset state.

Now, in this embodiment, buffer 9 (register)
has a 2-bit configuration.

First, bitl is set to 1 during the first access to buffer 9.
When , latch 3 becomes latch enable and 1 is latched. At this time, latch 4 is disabled. If the program in part 6 of 010 advances to the next step and releases buffer 9, the bitl of buffer 9 becomes O.
Returning to , the output of the latch 3 is set to 1 by the latch 4 being enabled. Note that the latches 3 and 4 may have a F/F configuration to prevent hair loss.

Then, during the second access to buffer 9, buffer 9
When 1 is written to bitO of , gate 5 becomes active and F/F 7 is set to 1 by CLKI. F
The output of /F7 clears counter 2 via gate 12. The inverted output of F/F7 clears latches 3 and 4 through gate 14, and as a result, F/F7 is reset (set to 0) by 1 in the next CL, and counter 2
is cleared, and counter 2 counts up again.

If the above operation is programmed to be repeated at a cycle shorter than the cycle in which the counter 2 overflows, the watchdog will not be reset. However, if the program goes out of control and no longer operates as described above, the counter 2
overflows and passes through gate 13 to 010 part 6
Reset. At the same time, the latch 8 is set.

In order to determine whether this reset is caused by a signal from the reset terminal R3T2 or a watchdog reset, the output of the latch 8 is configured so that it can be read by the CPU 6 via a buffer 11. You can know whether it is true or not. For example, a reset using the reset terminal R3T2 clears the RAM of the CPU 6, but a watchdog reset does not clear the RAM, making it possible to restore the system to a state close to the state before the watchdog reset. In this case, the latch 8 is reset via the buffer 10.

Next, a second embodiment of the present invention will be described using FIG. 2.

The difference between the second embodiment and the first embodiment is that the second embodiment is different from the first embodiment.
In the embodiment, the counter 2 can be cleared even if programming is performed so that "11" is always written to the buffer 9, whereas in the second embodiment, "10" and "01" must be intentionally written. The only difference is that the counter 2 is configured so that it cannot be cleared, and the other configurations are the same as in the first embodiment, so repeated explanation will be omitted.

FIG. 2 shows the configuration of a second embodiment, in which the above functions are realized by arranging gates 16 and 17. With this configuration, “10” and “01”
Since only the following are permitted, safety against the runaway can be increased.

Next, a third embodiment of the present invention will be described using FIG. 3.

The third embodiment differs from the second embodiment in that the second embodiment is further configured such that after writing "10", "01" must be written. In other words “
After writing ``10'', if ``10'' is written again, latch 3 is cleared and ``10'' and ``01'' must be written again in this order. Therefore, as shown in FIG. A gate 18, 19 and a buffer 20 are arranged in the buffer 20 so that the CPU 6 can read the output of the latch 4. If the output of the latch 4 is 0, "10" is written to the buffer 9, and the output of the latch 4 is read. If is 1, "01" is written to the buffer 9. When "10" is written to the buffer 9 while the output of the latch 4 is 1, the latch 3 is cleared by the gate 18 via the gate 19. When the access to buffer 9 is finished, latch 4 is cleared. Therefore, in that case, "10"
Unless "01" is written next, counter 2 will not be cleared and a watchdog reset will occur. In this way, by making the clearing operation of the counter 2 more complicated, safety against runaway increases, but if it becomes too complicated, the program capacity, etc. will increase. However, if it is about the level of the third embodiment, the influence will be small.

Next, a fourth embodiment of the present invention will be described with reference to FIG. 4.

The fourth embodiment relates to a configuration for killing the watchdog timer function. During program development, you may want to disable the watchdog timer function. Normally, when developing a program, the procedure is often to design the entire program and then, after completing the entire design, to intersperse watchdog timer reset instructions throughout the program. Otherwise, a watchdog reset may occur unexpectedly during debugging, interfering with debugging.

Therefore, as shown in FIG. 4, there is a buffer 2 in FIG.
2,23. and a latch 21 and an EMLT terminal are arranged,
The watchdog function may be stopped by setting this EMLT terminal high to kill the watchdog timer during emulation, or by using a special signal generated during emulation. In FIG. 4, latch 21 is set by a reset signal during emulation and continues to clear counter 2 via gate 12. Further, during normal use, the EMLT terminal is low, the latch 21 continues to be reset, and the watchdog timer is not affected.

There are also cases where it is desired to emulate whether watchdog instructions are appropriately placed in a program.

At this time, if the latch 21 can be reset by the CPU 6 via the buffer 22, watchdog emulation becomes possible. As shown in FIG. 4, although the watchdog function can be activated from the CPU 6, it cannot be stopped, so even if the watchdog goes out of control, the watchdog function will not be stopped.

〔Effect of the invention〕

As explained above, according to the present invention, in a microprocessor with a built-in watchdog timer, the watchdog timer is reset by using a register to set a plurality of bits at different timings, so that all bits are set at different timings. This has the effect of providing a watchdog timer that can increase the accuracy and safety of runaway detection.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a watchdog timer and its peripheral parts in a first embodiment of the invention, FIG. 2 is a block diagram of a second embodiment of the invention, and FIG. 3 is a block diagram of a third embodiment of the invention. Fig. 4 is a block diagram of the fourth embodiment of this invention;
The figure is a configuration diagram of a conventional watchdog timer. 1... Timing generator 2...
Counter 3.4, 8.21---Latch 7...-F/F 9.10, 11, 20, 22.23...Buffer Note that the same symbols in the figure are the same. or a corresponding portion.

Claims (1)

[Scope of Claims] A watchdog timer formed on the same chip as a CPU, RAM, ROM, timing generation circuit, etc., which counts with a clock generated by the timing generation circuit, and when a predetermined value is reached, a count means for issuing a reset interrupt to the CPU; a register accessible from the CPU; and a count means for issuing a reset interrupt to the CPU;
A watchdog timer comprising: count clearing means for determining a value to be set from a PU and clearing the counting means when the plurality of bits are set according to a predetermined procedure.