JPS599937B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention divides main memory into a hardware area and a software area, the software area stores programs that can be viewed by the operating system, and the hardware area stores a specific program. The instruction execution procedure for processing compound instructions and the instruction execution procedure for processing to be performed when a specific event occurs are stored, and when a specific compound instruction or a specific event is detected, an interrupt is generated. Therefore, the present invention relates to an information processing apparatus that is capable of executing the instruction execution procedure of the above-mentioned hardware area.

In conventional information processing devices, instructions are processed by microprograms stored in fixed logic circuits or control memory. Instructions include instructions that are used very infrequently and instructions that are executed by extremely complex and diverse processing, but if you try to execute such instructions on a conventional information processing device such as the one described above, Fixed logic circuits become very complex, microprograms increase, and control memory capacity increases. Furthermore, it has been extremely difficult to add new instructions to the above-mentioned information processing apparatus. The present invention eliminates the above-mentioned drawbacks, and is capable of easily adding specifications, and is capable of performing extremely complex and diverse processing without complicating fixed logic circuits or increasing microprograms. An object of the present invention is to provide an information processing device that can execute instructions that are frequently used or instructions that are used infrequently.

In addition, when certain events occur, existing operating
The purpose is to substitute functions for specific events that should be added to the system or are difficult to add. For example, every time one instruction is completed, an interrupt is made and the statistical information thereof is obtained. Interrupts at regular intervals to discover and correct 1-bit errors in main memory. This can be used to interrupt machine checks, obtain more detailed statistical information, perform hardware recovery operations, etc. Therefore, the information processing device of the present invention includes a main memory, an interrupt mechanism, a memory access control means, various registers, and a register access means, and the main memory is theoretically The software area is divided into a fixed area and a hardware area, and the software area is provided with a fixed area and stores normal software, and the hardware area is provided with a fixed area and stores specific instructions or instructions for specific events. A sequence of execution procedures is stored, and the interrupt mechanism transmits the current program state word to the hardware when the specific instruction is issued or the occurrence of a specific event is detected under the condition that a specific register has a specific value. The new program status word stored in the fixed area of the hardware area is stored as the old program status word in the fixed area of the area, and the new program status word stored in the fixed area of the hardware area is set as the current program status word. The memory area is configured to start execution of a sequence of instruction execution steps in the area.
The access control means prohibits access to the hardware area from the normal software, allows access to the software area from a sequence of instruction execution procedures in the hardware area, and provides other specified information. If the sequence of instruction execution steps in the hardware area is executed under the condition that the register has a specific value, the main memory is accessed using the real address and the memory is protected. If the instruction execution procedure sequence in the hardware area is executed under the condition that the other specific registers mentioned above do not have a specific value, then the instruction execution sequence sequence is executed. The register access means is configured to perform control for accessing the main memory according to the mode of the current program state word immediately before an interrupt to which control is passed occurs, and the register access means controls the instruction execution procedure in the hardware area. When executing a sequence of instructions, it is possible to use not only registers that can be used by normal software but also special registers inside the information processing device that cannot be used by normal software. The present invention is further characterized in that interrupts other than hard machine check interrupts and program interrupts are prohibited during execution of the sequence of instruction execution procedures in the software area. Hereinafter, the present invention will be explained with reference to the drawings.
1 to 4 show one embodiment of the main part of the present invention, in which FIG. 1 is a diagram illustrating division of the main memory, and FIG.
3 is a block diagram of address generation means at the time of an interrupt, FIG. 3A is a diagram for explaining access to registers, and FIG. 4 is a block diagram of memory access control means.

As shown in FIG. 1, the main memory is divided into a hardware area HA and a software area SA.

A fixed area HAP is provided in the hardware area HA,
Similarly, a fixed area SAP is provided in the software area SA as well. Fixed areas HAP and SAP are prefix areas. The hardware area stores a sequence of instruction execution procedures for processing specific compound instructions stored in the software area, a sequence of instruction execution procedures for processing to be performed when a specific event occurs, etc. has been done. The new PSW and old SPW are stored in the fixed area HAP. The same applies to the fixed area SAP. The boundary address is an address that separates the hardware area HA and software area SA. FIG. 2 shows means for generating an address at the time of an interrupt (for example, at the time of a program interrupt).

In FIG. 2, 1 to 3 are gates, 4 is a base register, 5 is an index register, 6 is a three-input adder, and 7 is a flip-flop. When a specific compound instruction is detected while executing a program in software area SA, gate 2 or 3 turns "l" on condition that the corresponding bit in the operational status register is on. The flip-flop 7 is set and the hardware mode signal becomes "1". When a program interrupt occurs, constant 1281 is first input into index register 5.
Also, since the hardware mode signal becomes [1],
The contents of the boundary address are set in base register 4. Then base register 4 and index register
The contents of the register 5 are added by a three-input adder 6, and the addition result is sent to the S unit (storage control unit).
The addition result output from the 3-input adder 6 is in the fixed area H
This shows the address of the old PSW for program interrupts in the AP.
SW is set to old PSW.

Constant 6681 is then input to index register 5, and the contents of base register 4 and index register 5 are similarly added by three-input adder 6. The result of this addition is the new PSW of the fixed area HAP.
This shows the address of the new PSW to the current PSW.
SW is set. Current PSW before replacement and current P after replacement
Although the instruction address is different from SW, other parts such as the memory protection key and mode bits are almost the same. When the execution of the corresponding instruction execution procedure sequence is completed and the interrupt processing is completed, the fixed area HAP is
The old PSW of is set to the current PSW, but this LOAD
When the PSW instruction is executed, the return signal becomes "1" and flip-flop 7 is reset, thereby causing the hardware mode signal to become "O". In this way, a sequence of instruction execution procedures in the hardware area HA corresponding to a specific compound instruction in the software area SA is executed. The above describes an example in which when a specific compound instruction is detected, a sequence of corresponding instruction execution procedures in the hardware area HA is executed by an interrupt. However, when a specific event is detected, Also, a sequence of corresponding instruction execution procedures in the hard area HA is executed. 3A and 3B illustrate access to the register.

In FIG. 3A, 8 indicates a register stack. The register address for selecting a register has a 5-bit configuration. The first bit is set to logic ``1'' when entering hardware mode or selecting a floating point register. As shown at the beginning of FIG. 3, when the first bit is "0", it becomes possible to select any one of the 16 general-purpose registers. If the first bit is "1" and the second bit is "O", it is possible to select any one of the eight floating point registers. Also, if the first bit is "1" and the second bit is "1", then 8
It becomes possible to select any one of the internal registers. As can be seen from Figure 3B, instructions in the software area SA cannot access floating point registers and internal registers, and as a general rule, the sequence of instruction execution procedures in the hardware area HA is limited to general-purpose registers. cannot be accessed. However, in special cases, the general register can be accessed even in hardware mode by turning off the first bit. FIG. 4 is a block diagram of the memory access control means.

In FIG. 4, 9 is an address register, 10 is a boundary address register, 11 is a comparator, and 12 is a flip-flop register.
Flop, 13 is NOT gate, 14 to 16 are AN
Each D gate is shown. If not in hardware mode, when the contents of address register 9 exceed the contents of boundary address register 10, the operating system is notified of the occurrence of an address exception condition. This means that instructions in the software area SA are prohibited from accessing the 2-to-ware area HA.
It means. In the hardware mode, the operating system is notified of the occurrence of an address exception condition when the access address exceeds the maximum storage capacity of the main memory. This means that the sequence of instruction execution procedures in the hardware area HA is not prohibited from accessing all areas of the main memory. The base register (not shown) has a 32-bit configuration, and bits 8 to 31 indicate the memory address. When bit O of the base register is a logic "1", the address information is This indicates that it is real address information, and the bit [
0] is logical "0", it means that whether the address information is real address information or logical address follows the current PSW. When in hardware mode, if bit O of the base register is a logic ``1'', flip-flop 12 is set and AND gate 16 outputs a logic ``1''. When the output of the AND gate 16 becomes logic "1", main memory access is performed using real addresses and memory protection is prohibited. Further, in the hardware mode, if bit O of the base register is logic "0", the main memory is accessed according to the contents of the current PSW. As mentioned earlier, the current PSW's memory protection key and mode bits are the same as the old PSW's mode. When the sequence of instruction execution procedures accesses the -toware area HA, real addresses are used and memory protection is prohibited. In addition, when the sequence of instruction execution procedures accesses the software area SA, the current PS
Access is performed according to the contents of W. A sequence of instruction execution procedures in the hardware area HA corresponds to one specific compound instruction in the software area.

In order to treat this series of instruction execution procedures as the same as one compound instruction, interrupts other than hard machine checks and program interrupts are prohibited while this series of instruction execution procedures is being executed. Interrupts other than hard machine checks and program interrupts are similarly prohibited even when a sequence of instruction execution procedures corresponding to a specific event is being executed. As is clear from the above description, according to the present invention, new instructions can be easily added and extremely complex and diverse processing can be performed without complicating fixed logic circuits or increasing microprograms. It is possible to execute instructions that are executed or instructions that are used infrequently.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 to 4 show an embodiment of the main part of the present invention, in which FIG. 1 is a diagram illustrating division of the main memory, and FIG.
3 is a block diagram of the address generation means at the time of an interrupt, FIG. 1 to 3...gate, 4...base register, 5...index register,
6...3-input adder, 7...flip-flop, 8...register stack, 9...
... Address register, 10 ... Boundary address register, 11 ... Comparator, 12.
...Flip Flop, 13...NO
T gate, 14 to 16...AND gate.

Claims (1)

[Claims] 1 comprises a main memory, an interrupt mechanism, a memory access control means, various registers, and a register access means, and the main memory is theoretically divided into a software area and a hardware area, The software area is provided with a fixed area and stores normal software, the hardware area is provided with a fixed area and stores a sequence of instruction execution procedures for specific instructions or specific events, and the interrupt mechanism includes: When the specific instruction is issued or the occurrence of a specific event is detected under the condition that the specific register has a specific value, the current program status word is stored in the fixed area of the hardware area as the old program status word, and The new program status word stored in the fixed area of the hardware area is set as the current program status word, and the execution of the sequence of instruction execution procedures in the hardware area corresponding to the specific instruction or specific event is thereby started. The memory access control means prohibits access to the hardware area from the normal software, and prohibits access to the software area from a sequence of instruction execution procedures in the hardware area. If the sequence of instruction execution steps in the hardware area is being executed under the condition that other specific registers have specific values, access to the main memory can be accessed from the real address. If the sequence of instruction execution steps in the hardware area is executed under the condition that the above other specific registers do not have specific values, and this is not subject to memory protection, The register access means is configured to perform control for accessing the main memory according to the mode of the current program state word immediately before an interrupt occurs that transfers control to the instruction execution sequence, and the register access means When executing a sequence of instruction execution procedures in a software area, not only registers that can be used by normal software are used for the sequence of instruction execution means, but also special registers inside the information processing device that cannot be used by normal software are used. What is claimed is: 1. An information processing device configured to enable this, and further characterized in that interrupts other than hard machine check interrupts and program interrupts are prohibited during execution of a sequence of instruction execution procedures in the hardware area.