JPH0471050A - Stack area protecting circuit - Google Patents

Abstract

PURPOSE:To execute detailed and efficient memory protection for a stack area by deciding whether an address is included or not in a range indicated by the upper-limit and lower-limit addresses in a specific stack area in each access to the stack area. CONSTITUTION:When the check of a stack boundary is instructed by a memory access instruction signal 74 at the time of generating an access, a memory access control circuit 70 activates a stack boundary check valid signal 73. When a memory access address 71 is larger than an upper limit address 32, an upper limit address comparator 40 activates a stack upper limit over detection signal 42. Similarly, a lower limit address comparator 41 activates a stack lower limit over detection signal 43. When either one of the signals 42, 43 is active, an interruption is requested to a control circuit 60 and the start of exceptional processing against stack area protection is requested.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides memory protection in computer systems;
In particular, the present invention relates to a stack area protection circuit that protects a stack area.

[Prior Art] Normally, in a computer system, multiple programs run in parallel to increase usage efficiency. For this reason,
It is necessary to protect memory (storage area) in order to protect information between these programs and to prevent system stoppage if a program goes out of control. For this reason, many computers have a circuit for memory protection. Various methods have been used to protect memory, but a typical method is to incorporate a memory protection mechanism into the address translation mechanism used for memory management. There is a paging method in the address translation mechanism that is currently widely used (References 2 O8 Overview, written by Hideshi Kubo, published by Kyoritsu Shuppan, P, 80, P, 84-P,
88).

FIG. 2 shows an example of memory protection using a paging method. In the paging method, a storage area is divided into fixed sizes, and addresses are converted from logical addresses to physical addresses for each page, which is a unit of division.

In order to perform this conversion, a page table PT is prepared, and a physical address is extracted from the page table using the logical address at this time as an index to the page table. In the case of Figure 2, the page address (j+3
) to search the page table and subtract the page address (1+3) of the physical address. When extracting this physical address, write the physical address and protection level on the page table. This protection level includes, for example, readability,
Describe whether or not writing is possible, whether or not execution is possible, etc. Protection for pages is achieved by checking this protection level during address translation. In the example in Figure 2, R, W, and E indicate read, write, and execution rights, respectively; 1'' indicates the right, and ``Ou'' indicates no right. It shows that the page has only the right and no other rights.Therefore, this page can only be read and cannot be written.

The above has described memory protection using the paging method, and one of the characteristics of the paging method is that it does not depend on the purpose of memory use.

Computer memory can usually be logically separated into a program area, data area, stack area, etc. depending on the purpose of use. The paging method does not logically divide the information according to the purpose of use, but instead divides the information into fixed sizes. However, in order to achieve actual protection, it is desirable to be able to provide detailed protection for individual areas. For example, if you try to protect the stack area,
Although the actual amount of memory used is small, in order to achieve protection in the paging method, allocation is required in page units.

This stack area is a first-in, last-out memory in which data is stacked one after another, and when data is retrieved later, it is taken out in order from the top. This stack plays a major role in making software easier to create. Therefore, it is extremely important to know whether the stack area is operating as expected, and it also contributes to increasing the efficiency of program development. Therefore, protecting this stack area not only protects the memory contents but also contributes to improving the efficiency of program development and the reliability of software.

[Problem to be solved by the invention] Although the memory protection using the paging method described so far is a highly versatile and excellent method, there is a problem in that the minimum unit of memory protection is limited to the size of a page. . This problem is a big problem in the application fields described below.

For example, communication systems, which are one application field of computer systems, are characterized by an extremely large number of programs running in parallel at the same time. Therefore, in order to protect the code, data, and stack areas of these programs, different pages must be individually allocated for each program and each area. In other words, pages with poor memory usage efficiency will occur.

As a result, in communications applications where the amount of memory used by individual regions is relatively small, more memory than is actually needed must be allocated to achieve memory protection.

However, in the field of communication applications, it is undesirable to increase the amount of memory installed in devices in order to reduce costs.

Therefore, for the purpose of memory protection, it is necessary to have a larger amount of memory than necessary or to limit the number of programs that can run concurrently, making it possible to realize a device with low cost and excellent functionality/performance. There was a problem with that.

An object of the present invention is to solve the problem of memory protection by the paging method, and to realize efficient memory protection for the stack area even in a system having an address translation mechanism by the paging method and only a small memory capacity. An object of the present invention is to provide a stack area protection circuit.

[Means for Solving the Problems] The present invention has a paging-based address translation mechanism,
This address translation mechanism is applied to a computer system having a page-based memory protection mechanism and a stack operation function, and the stack area protection circuit of the present invention is added to this computer system.

As shown in Figure 1, an area (block) of a predetermined size
A first circuit is provided for specifying a specific area and an upper limit address 32 and a lower limit address 33 of a stack area to be set within this specific area, respectively, for each area of the memory space divided into two areas. This first circuit includes a stack boundary register 10, a selector 20, an upper limit address generation circuit 30, and a lower limit address generation circuit 31.

The device further includes a second circuit that determines, each time the stack area is accessed, whether or not the current address is within a range indicated by the upper and lower limit addresses in the specific area. This second circuit consists of an upper limit address comparison circuit 40, a lower limit address comparison circuit 41, and a stack boundary over detection circuit 50.

Memory protection for the stack area is performed based on the output of this second circuit (stack boundary over detection signal 51).

[Each time a stack operation is performed to access the working cost stack area, the first circuit identifies the range of the stack area to be operated, and the second circuit compares and determines the range with the access address. Ru. When an access outside the stack area set in the memory occurs, a stack boundary over detection signal 51 is output from the second circuit, and an exception process is executed by interrupting the stack area protection violation. By executing this interrupt processing, the stack operation is stopped and stack data is prevented from being destroyed due to a runaway program.

The range of the stack area can be arbitrarily determined without being restricted by pages by using one stack boundary register prepared separately from the memory address register that specifies the page.

[Embodiment Section 1 shows an embodiment of a stack area protection circuit to which the present invention is applied. This stack area protection circuit has a paging-type address conversion mechanism, and this address conversion mechanism is added to a computer system that has a page-based memory protection mechanism and a stack operation function. Therefore, the computer system of this embodiment provided with the stack area protection circuit coexists with the paging method and memory protection mechanism shown in FIG.

In FIG. 1, 10 is a stack boundary register indicating a stack area to be protected. Multiple protections,
For example, in a computer capable of L level protection, the stack boundary register 10 is not provided. The inside of this register 10 is divided into three fields, 11
indicates the block address (n bits), 12 indicates the upper limit within the block (p bits), and 13 indicates the lower limit within the block (q bits).

20 is a selector, L stack boundary registers 1
0 to the stack boundary register 10 corresponding to the operating level at the time of execution indicated by the control circuit 60, and block address 21, upper limit within block 22, lower limit within block 2, respectively.
Output each part of 3.

30 and 31 are an upper limit address generation circuit and a lower limit address generation circuit, respectively. The upper limit address generation circuit 30 receives the block address 21 and the intra-block upper limit 22 as inputs, and outputs the stack upper limit address 32 to the stack upper limit address bus. Similarly, the lower limit address generation circuit 31 receives the block address 21 and the intra-block lower limit 23 as inputs, and outputs the stack lower limit address 33 to the stack lower limit address bus.

40 and 41 are an upper limit address comparison circuit and a lower limit address comparison circuit, respectively. The upper limit address comparison circuit 40 compares the stack upper limit address 32 and the memory access control circuit 7.
The memory access address 71 starting from 0 is input, the two are compared in magnitude, and the result is output as the stack upper limit over detection signal 42. Similarly, the lower limit address comparison circuit 41 inputs the stack lower limit address 33 and the memory access address 71, compares the two in magnitude, and outputs the result as the stack lower limit over detection signal 43.

Reference numeral 50 denotes a stack boundary over detection circuit, which inputs a stack upper limit over detection signal 42, a stack lower limit over detection signal 43, a memory access request signal 72, and a stack boundary check valid signal 73, and finally detects a stack boundary violation. and outputs the stack boundary over detection signal 51.

A control circuit 60 controls the stack area protection circuit. The stack boundary over detection signal 51 is input to this control circuit 60, thereby starting interrupt processing. The control circuit 60 also includes a control register for instructing execution of a stack boundary check. Also, when accessing the memory, the memory access instruction signal 74 is used.
The instruction is given to the memory access control circuit 70.
Reference numeral 70 denotes a memory access control circuit which performs memory access in response to a memory access instruction from the control circuit 60, and which outputs a memory access address 71, a memory access request signal 72,
A stack boundary check enable signal 73 is output. In addition,
Address bus 75 for output of memory access control circuit 70
is an address translation device using paging method (not shown)
The address is connected to the address bus, and address translation is performed on the address on the address bus.

The stack boundary check operation during memory access will be explained below. The stack boundary check is performed to protect the stack area because if the access address specifies an address outside the stack area when the stack area is accessed, the program will run out of control and an abnormal situation such as a system stop will occur. Because it is necessary to do so. If an address outside the boundary is detected by the stack boundary check, exception processing for stack area protection violation is activated to prevent such a situation from occurring.

Memory access is instructed by a memory access instruction signal 74 from the control circuit 60 and executed by the memory access control circuit 70. Memory access control circuit 7
0 sends out the memory access address 71 to be accessed to the address bus 75 and activates the memory access request signal 72 when access is performed. Further, when a stack boundary check is instructed by the memory access instruction signal 74, the stack boundary check valid signal 73 is activated.

On the other hand, it is assumed that information regarding the range to be checked is set in advance in the stack boundary register 10.

Stack boundary register 10 has three stack boundary registers as shown in FIG.
It is divided into three fields: block address 11, intra-block upper limit 12, and intra-block lower limit 13.

FIG. 3 shows a method of specifying a stack area to be protected based on the contents of the stack boundary register. The memory is divided into blocks, which are relatively large fixed areas, and each block can be protected. Here, it is assumed that the memory address is N pinto (the number of bits of the stack boundary register). Set the block address congestion to n bits (the number of bits of the block address written as N+1)
Then, the size of one block is 2<N-n) bytes. Protection is performed within the range of this block, and the range to be protected is indicated by the stack upper limit and stack lower limit. The stack upper limit and the stack lower limit each indicate an offset value within the block, and the stack upper limit address 32 and the stack lower limit address 33 are calculated by combining each with the block address. This stack upper limit address 32 and stack lower limit address 33
The space between this and the stack area is the stack area, and if an area outside this area is accessed, an interrupt process is activated as a stack area protection violation. Stack space is usually smaller than a page.

The contents of the stack boundary register 10 corresponding to the protection level at that time are selected by the selector 20 from among the L stack boundary registers having the three fields in which protection area values are set in advance, and the block address 2 is selected by the selector 20.
1, the intra-block upper limit 22 and the intra-block lower limit 23 are output. The selected address information is input to the upper limit address generation circuit 30 and the lower limit address generation circuit 31. Each circuit 30.31 uses a means such as addition from the block address and the stack upper limit/stack lower limit to create a stack upper limit address 32 and a stack lower limit address 33.
and sends the respective addresses to the stack upper limit address bus and stack lower limit address bus.

The generated stack upper limit address 32, stack lower limit address 33, and memory access address 71 output from the memory access control circuit 70 are input to the upper limit address comparison circuit 40 and the lower limit address comparison circuit 41.

Upper limit address comparison circuit 40: Yo stag upper limit address 3
2. The memory access address 71 is input, the magnitude of the two is compared, and if the memory access address 71 is larger than the stack upper limit address 32, the stack upper limit over detection signal 42 is activated. Similarly, the lower limit address comparison circuit 41 includes the stack lower limit address 33,
The memory access address 71 is input, the magnitude of the two is compared, and if the memory access address 71 is smaller than the stack lower limit address 33, the stack lower limit over detection signal 43 is activated.

The stack boundary over detection circuit 50 receives as input a stack upper limit over detection signal 42, a stack lower limit over detection signal 43, a memory access request signal 72 sent from the memory access control circuit 70, and a stack boundary check valid signal 73, If the boundary check valid signal 73 is active, the memory access request signal 72 is active, and either the stack upper limit over detection signal 42 or the stack lower limit over detection signal 43 is active, the stack area indicated by the stack boundary register 11 is It is determined that the access is outside the
activating the stack boundary over detection signal 51;
An interrupt is requested to the control circuit 60 to request activation of stack area protection violation exception handling.

As described above, according to this embodiment, the stack area can be protected in units smaller than the page size, and memory usage efficiency can be improved, compared to storage protection using only the paging method. In particular, if applied to the communication field, where there are an extremely large number of programs running concurrently and each area uses a relatively small amount of memory, it may be necessary to use more memory than is necessary for the purpose of memory protection.
Since there is no need to impose restrictions on the number of programs that run in parallel, it is possible to realize a device with excellent functions and performance at low cost.

Furthermore, the designation of the stack area to be protected can be easily changed using an independent dedicated stack boundary register. This means that a stack area of any size can be protected without being restricted by pages, and it is also possible to protect a stack area that spans pages. Furthermore, if the stack area to be protected is larger than the page, by protecting the stack area, it becomes possible to protect the corresponding page area as well.

[Effects of the Invention] As explained in detail above, according to the present invention, even in a computer system using the paging method, even in a system having an address translation mechanism using the paging method and having only a small memory capacity, the paging method can be used. Fine-grained and efficient memory protection can be performed for the stack area without sacrificing any benefits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a stack area protection circuit showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of memory protection using a conventional paging method, and FIG. 3 is an explanation of stack area protection according to an embodiment of the present invention. It is a diagram. 10 is a stack boundary register, 20 is a selector, 30 is an upper limit address generation circuit, 31 is a lower limit address generation circuit,
32 is an upper limit address, 33 is a lower limit address, 40 is an upper limit address comparison circuit, 41 is a lower limit address comparison circuit, 50
Reference numeral 51 indicates a stack boundary area over detection circuit, and 51 indicates a stack boundary over pressure detection signal.

Claims (1)

[Scope of Claims] 1. In a computer system having a paging-type address conversion mechanism, this address conversion mechanism having a page-based memory protection mechanism, and a stack operation function, an area of a predetermined size. Regarding the memory space divided into
A first circuit that specifies an upper limit address and a lower limit address of a specific area and a stack area set within this specific area, using each area as a unit; and a second circuit that determines whether or not the upper and lower limit addresses in the specific area are within the range indicated, and memory protection for the stack area is performed based on the output of the second circuit. Stack area protection circuit. 2. The stack area protection circuit according to claim 1, wherein the computer system is capable of specifying a level of memory protection, and the stack area protection is performed for each protection level.