JPH03113548A - Extension memory controller - Google Patents

Abstract

PURPOSE:To facilitate a multi-tasking operation and to protect a memory by providing an extension memory control circuit via another hardware to fetch the control instruction and the address information of a microprocessor circuit and giving these instruction and information to the extension memory. CONSTITUTION:The control instruction and the address information of a microprocessor circuit 1 are fetched and then given to an extension memory 3. That is, it is decide whether the address information inputted from the circuit 1 is used to give an access to the memory 3 or not. If so, a base address of an active page is read out of the access information to be inputted. Then an offset address set previously is added to the read base address and outputted. The propriety and the presence/absence of protection are checked for the output address information. Then a memory access is carried out. As a result, a multi- tasking operation is facilitated and the memory can be protected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to a computer system. The present invention relates to an apparatus capable of accessing and protecting an extended memory beyond the real address space of a microprocessor circuit, and easily performing multi-sking on the extended memory.

〔overview〕

The present invention provides an extended memory control device that includes a microprocessor circuit, a main memory, and a circuit memory, and provides a circuit for controlling the extended memory using separate hardware.
By taking control commands and address information from the microprocessor circuit and providing address information and control commands to this expanded memory, application programs can be developed without having to be aware of the expanded memory, and multitasking can be easily performed. It is designed to provide protection.

[Conventional technology]

A conventional expansion memory controller includes a microprocessor circuit, a main memory that is accessed by the microprocessor circuit and whose read output is applied to the microprocessor circuit, and an expansion memory whose read output is applied to the microprocessor circuit. In preparation, the extended memory 3 is divided into a plurality of logical pages X and YSZ, as shown in FIG. 6, and in order to map these, a specific address range on the main memory 2 is associated as a physical page frame 5. . The physical page frame 5 is composed of four 16KB pages, and can access logical pages of up to 64KB. Access and control of logical pages is performed by an Expanded Memory Manager (8MM).
anager).

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, when configuring a small-scale computer system using a microprocessor circuit, there are problems such as the microprocessor circuit having no memory protection function and an extremely narrow address space. Extended memory specification (BM) is one method of memory expansion control.
S: Bxpanded Memory Specific 1
However, it is inconvenient to execute programs and access data on logical pages, and cannot achieve sufficient performance, making it unsuitable for real-time multitasking applications, and has the following problems.

■ All the procedures for referencing data on extended memory and executing programs must be written in the user program, which is a heavy burden.

■ With conventional extended memory and control devices (for example, PC98/RA manufactured by NEC Corporation), when accessing data on extended memory, a logical page on the extended memory is mapped or unmapped to a physical page on main memory. 16KB of data is transferred each time, making it unsuitable for real-time processing.

■ Associating physical pages with logical pages takes too much processing time. For example, in the PC98/RA, 6111
8. Furthermore, if the extended memory specification (BMS) is realized by hardware, the time will be significantly improved to 140 μS, but the load will be too large for real-time processing.

■ Physical pages are not necessarily consecutive depending on the machine, and physical page frames are as narrow as 16 KB, so data access or program execution across pages is not necessarily guaranteed.

■ Since there is no memory protection function for extended memory, it is not possible to protect access to data and programs, which is necessary in a multitasking environment.

■ Interrupts are prohibited during page switching, which is unfavorable for overall system performance.

The present invention solves these problems, and when a computer system is configured with a microprocessor circuit that has a narrow address space and does not have a memory protection function, it is possible to develop application programs without having to be aware of expanded memory. , multitasking with ease,
The purpose is to provide a device that can protect memory.

[Means for solving problems]

The present invention provides an expansion memory comprising a microprocessor circuit, a main memory accessed by the microprocessor circuit and whose read output is taken into the microprocessor circuit, and an expansion memory whose read output is taken into the microprocessor circuit. In the control device, an extended memory control circuit that takes in control commands and address information from the microprocessor and provides address information and control commands to the extended memory is provided by separate hardware, and this extended memory control circuit receives input from the microprocessor. means for determining whether the address information to be input is one that should access the extended memory; and when the determining means determines that the address information to be input is one that should access the extended memory, the base of the active page is determined from the input address information. A means for reading an address, a calculation means for adding a preset offset address to a base address given by the reading means, and an address for checking the validity of the output address information of this calculation means and the presence or absence of protection settings. The invention is characterized by being equipped with an inspection means.

[Effect]

Captures control instructions and address information for the microprocessor circuit and provides address information and control instructions to expanded memory. That is, it is determined whether the address information input from the microprocessor circuit should access the extended memory or not, and when it is determined that the address information input from the microprocessor circuit is the one that should access the extended memory, the active page is determined from the input address information. Read base address. A preset offset address is added to this read base address and output, the validity of this output address information and the presence or absence of protection setting are checked, and memory access is executed.

This facilitates multitasking with real-time operating systems and improves system reliability due to memory protection.

Furthermore, task switching can be performed at high speed, making it easy to migrate to higher-level microprocessor circuits.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the extended memory control circuit 4 of the embodiment of the present invention, and FIG. 3 is a block diagram showing the software configuration of the embodiment of the present invention. FIG.

The extended memory control device according to the embodiment of the present invention includes a microprocessor circuit 1, a main memory 2 that is accessed from the microprocessor circuit 1 and whose read output is taken into the microprocessor circuit, and a main memory 2 whose read output is taken into the microprocessor circuit 1. Furthermore, an extended memory control circuit 4 which takes in control commands and address information from the microprocessor circuit 1 and provides address information and control commands to the extended memory 3 is provided by separate hardware, and this extended memory control circuit 4 is provided with separate hardware. The circuit 4 includes an address determining means 41 for determining whether address information input from the microprocessor should access the extended memory 3, and an address determining means 41 for determining whether the address information input from the microprocessor should access the extended memory 3.
A readout means 42 reads out the base address of the active page from address information input when it is determined that the active page should be accessed, and a preset offset address is added to the base address given from the readout means 42. and an address checking means 44 that checks the validity of the output address information of the calculation means 43 and the presence or absence of protection settings.

The microprocessor circuit 1 has a 20-bit address bus and a 16-bit data bus, and a part of the address space is mapped to an extended memory 3 by an extended memory control circuit 4. Page switching is performed by a human output command from system software (not necessarily an operating system) residing in the main memory 2.

The expansion memory control circuit is interposed between the microprocessor circuit 1, the main memory 2, and the expansion memory 3, and controls the expansion memory by referring to an internal table set in advance by the system software using the 20-bit address output from the microprocessor circuit 1. 3 to a 32-bit address. At the same time, the memory read (MRD) and write (MWR) output from the microprocessor circuit 1
) signal, performs an access protection check, and performs page switching at high speed (with one command).

The extended memory 3 can be addressed up to 4 GB (32 bits), and a loader can store a plurality of programs of up to IMB in order to efficiently perform multitasking. Each logical page corresponds to a page frame on the main memory 2, and is viewed by the microprocessor circuit 1 as a continuous address space.

System software that instructs switching of extended memory mapping resides on the main memory 2.

A multitasking operating system is not necessarily required; it may be a simple function key interrupt or a keyboard interrupt handler that switches pages and executes a program.

Next, an address conversion method of the extended memory control circuit 4 according to the embodiment of the present invention configured as described above will be explained. Fourth
Figures (a), (b), and (C) are diagrams showing the active page register, page frame management register, and extended memory control circuit address conversion table of the embodiment of the present invention, and Fig. 5 shows the processing of the embodiment of the present invention. It is a flowchart showing the flow. WP in FIG. 4C indicates write protection, and the access level indicates protection between tasks; for example, a level 1 task cannot access a level 0 area.

First, the 20-bit address sent by microprocessor circuit 1 is stored in the page frame (extended memory access).
The address determining means 41 checks whether the address is outside the page frame, and if it is outside the page frame, accesses the main memory 2 for writing (MMWR) or reading (MMRD) (step 2).

Page number that the extended memory control circuit 4 is currently mapping
, the page number of the active page register holding ,
Refers to the extended memory control circuit address conversion table from , and performs address conversion and protection check. The contents of this register are changed by the system program in the main memory 2 (step 2).

Next, the page base address is indexed from the page number currently being mapped (step ■), and the offset address, which is the 20-bit physical address on the main memory 2 given from the microprocessor circuit 1, is indexed from the page number on the extended memory 3. Becomes an offset address (step ■
).

A 32-bit physical address on the extended memory 3 is generated by adding the 20-bit address given from the microprocessor circuit v@1 and the page base address (step 2). Checks whether the 32-bit physical address on the expansion memory 3 generated in step (3) is within the active page, and if the address is outside the range, sends a bus error (BERR) to the microprocessor circuit 11. do.

A protection check is performed to determine whether the access to the extended memory 3 is legal based on the memory read (MRD) and memory write (MWR) signals sent from the microprocessor circuit 1, and if it is illegal, a protection check is performed on the microprocessor circuit 1. Step ■) to send a protection error (PERR), and if it is valid, write extended memory (
Execute memory access by sending EMWR) or extended memory read (EMRD) signal (step ■) In this way, the functions of the extended memory driver (page management and program execution) required by the extended memory specifications are memory management. This is done by the controller (MMC) and the system program on the memory, so the user does not need to create or execute an application program that is aware of the program address on the extended memory 3. In addition, the memory management controller (MMC) It has task-aware segment management and memory protection functions.

The segments managed by the memory management controller (MMC) are VECTOR (interrupt vector area),
DATA (data area), C0DE (code area),
There are 5TACK (stack area) and C0MM0N (shared memory), and memory protection functions include segment-based access protection and access level.

Furthermore, a maximum of IMB of continuous memory can be allocated to one page based on an arbitrary address on the extended memory 3, and one task can be allocated to one page in a multitasking environment. Physical frames can be placed anywhere in main memory 2 except for interrupt vectors and operating system areas, and access levels and protection can be specified for pages in extended memory 3. When loading a program onto the computer, the code section can be specified to be automatically write-protected, and since page switching is implemented in hardware, task switching can be performed quickly.

〔Effect of the invention〕

As explained above, according to the present invention, multiple programs of maximum IMB can be resident and run in parallel, which facilitates multitasking using a real-time operating system, and in a multitasking system that runs relatively large software. Since memory protection can be achieved, system reliability can be improved. In addition, by allowing one task to correspond to one page and performing page switching using hardware, task switching in the scheduler of a real-time operating system can be performed quickly, and furthermore, an interface that is aware of expanded memory is not introduced during programming. This has the effect of making it easier to migrate to higher-level microprocessor circuits that have protection functions and large address spaces.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of an extended memory control circuit according to an embodiment of the present invention. FIG. 3 is a diagram showing the software configuration of the embodiment of the present invention. FIGS. 4A, 4B, and 4C are diagrams showing an active page register, a page frame management register, and an extended memory control circuit address conversion table according to an embodiment of the present invention. FIG. 5 is a flowchart showing the processing flow of the embodiment of the present invention. FIG. 6 is a diagram explaining the conventional expansion memory specifications. 1... Microprocessor circuit, 2... Main memory,
3... Expansion memory, 4... Expansion memory control circuit, 2... Physical page frame, 41... Address determination means, 42... Reading means, 43... Arithmetic means, 44.
...Address inspection 6 means.

Claims (1)

[Claims] 1. A microprocessor circuit (1), a main memory (2) that is accessed from the microprocessor circuit and whose readout output is taken into the microprocessor circuit, and a main memory (2) whose readout output is taken into the microprocessor circuit. an extended memory control device comprising an extended memory (3) in which the microprocessor circuit (1) is installed; (4) is provided by separate hardware, and this extended memory control circuit (4) determines whether the address information input from the microprocessor circuit (1) should access the extended memory (3). means for reading the base address of the active page from the input address information when it is determined by the determining means that the expanded memory should be accessed; and a base address given by the reading means. 1. An expansion memory control device comprising: arithmetic means for adding an offset address set in advance to .