JP2003271463A - Doubling memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To protect important data, and to easily detect the occurrence of abnormality in a doubling memory device for doubling a memory accessible from a processor. <P>SOLUTION: This doubling memory device has doubled memories 3 and 4 accessible by the processor 1, and a memory switching device 2. This memory switching device 2 has the constitution connected in a switching system to write the same data in the same address of the memories 3 and 4 of doubled one and the other at data writing time when imparting a memory protective condition, connected in a switching system to transfer the data read out of one memory 3 to the processor 1 at data reading-out time, connected in a switching system to write the data only to the doubled other memory 4 at data writing time when imparting no memory protective condition, and connected in a switching system to transfer the data read out of the other memory 4 to the processor 1 at data reading-out time. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a dual memory device capable of memory protection and memory abnormality detection in a computer system.

[0002]

2. Description of the Related Art In a computer system in which various kinds of data and programs are stored in a memory and a processor performs various kinds of information processing, a read-only memory ROM only reads the written data. A normal ROM is impossible. However, in the random access memory RAM, it is easy to rewrite data. Therefore, there is known a configuration in which a writing area of important data is set in advance so that it cannot be rewritten by another program.

It is also known to improve the reliability of information processing by duplicating a computer system. In that case, there is a case where a memory is shared by one system and the other system. There is a case where a memory is provided in each of the system of the other side and a complete duplex configuration, and in the hot standby method of this complete duplex configuration, the same data is stored in the memory of the system of one side and the other side. By writing, it is possible to switch between the active and standby.

[0004]

[Problems to be Solved by the Invention]
In the system, even if the important data write area is set, if the data is written beyond the area used by other programs, a part of the important data write area will be May be used. This will destroy important data. When such a situation occurs and important data includes a system management program, there is a problem that causes a system down. Moreover, there is a problem that it is not easy to analyze the factor. The present invention aims to protect important data and maintain the reliability of the important data.

[0005]

The dual memory device of the present invention will be described with reference to FIG. 1. The dual memory 3, 4 accessed by the processor 1 and the dual memory 3, 4 with the processor 1. Between the address bus and the data bus, the memory switching device 2 is provided, and the memory switching device 2 has a dual structure when writing data when a memory protection condition is given. Switching connection is made so that the same data is written to the same address in the memories 3 and 4 as the other memory, and one memory 3 is used when reading data.
The data read from the memory is switched and connected so as to be transferred to the processor 1, and when the data is written when the memory protection condition is not given, the data is read and written to the other memory 4 which is duplicated. In addition, when data is read, the data read from the other memory 4 is switched and connected so as to be transferred to the processor 1.

[0006] In addition, the memory 3 and 4 of one and the other which are duplicated
It has a data comparator for comparing the data read from the same address. An address storage device that stores an address at the time of writing data to one of the memories 3,
It has an address comparator for comparing the address stored in this address storage device with the address at the time of writing data to the other memory 4. Another memory 3
By an address storage device for storing the address at the time of writing data to the memory, an address comparator for comparing the address stored in the address storage device with the address at the time of writing data to the other memory 4, and the address comparator. It has a data comparator which compares data read from the same address of the memories 3 and 4 of one side and the other side by comparison and coincidence.

Further, the present invention has an abnormality information storage device for storing information including address and data at the time when an abnormality occurs when the address comparator compares and compares and when the data comparator does not compare. Memory switching device 2
Has a memory protection setting register for setting memory protection conditions for controlling the switching connection to the one and the other memories 3 and 4 that are duplicated with the processor 1 in accordance with a program request.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of a first embodiment of the present invention, in which 1 is a processor (CPU), 2 is a memory switching device, and 3 and 4 are dual memories of one and the other. Reference numeral 5 denotes a program storage area such as a read only memory (ROM). The memory switching device 2 includes an address bus (shown by a single line) and a data bus (shown by a double line) connected to the processor 1, an address bus (shown by a single line) and a data bus (shown by a single line) for the duplicated memories 3 and 4. (Shown by a double line) is for switching connection.

When writing important data from the processor 1 into the memory, for example, by the program A, the memory switching device 2 sets the memory protection condition so that the address bus and the data bus of the processor 1 are duplicated. The address bus and the data bus of 3 and 4 are switched so as to be connected to each other, and the write address and the write data from the processor 1 are added to the memories 3 and 4 of one and the other, and the same address is used. The data of is written.

When data is read by the program A, the memory switching device 2 switches and connects the address bus of the processor 1 and the address buses of the memories 3 and 4 to connect the data bus of the processor 1 and the data bus of the memory 3. The data read from one of the memories 3 by switching connection is read by the processor 1
Transfer to. In addition, for example, when writing or reading unimportant data by the program B to or from the memory, the memory switching condition is not set because the memory protection condition is not set.
Switch-connects the address bus of the processor 1 and the address bus of the other memory 4, and switches and connects the data bus of the processor 1 and the data bus of the other memory 4 so that only the other memory 4 receives data. Write and read. As a result, the content of the memory 3 on which the important data has been written can be protected.

In this case, the memory switching device 2 can be configured to perform switching connection by the internal control means depending on whether or not a memory protection condition is set. Alternatively, the control may be performed based on the processing judgment of the processor 1.

FIG. 2 is an explanatory diagram of the second embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same parts, and 6 indicates a data comparator. The control of writing in the duplicated memories 3 and 4 is the same as that shown in FIG. 1, but for example, when important data is read by the program A in which the memory protection condition is set, the memory switching device 2 is important. The address bus and data bus in the memory 3,
4, the same data is read out from the memories 3 and 4 at the same address and compared by the data comparator 6, and when the comparison and coincidence is normal, the read data is processed in the processor 1. If the comparison does not match, it indicates that the data has been rewritten or the data has been changed due to the damage of the memory element, and therefore the processor 1 is interrupted. Thereby, the reliability of important data can be improved.

FIG. 3 is an explanatory view of the third embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same parts, 7 is an address comparator, and 8 is an address storage device. The address storage device 8 stores, for example, an address when writing important data by the program A in which the memory protection condition is set to the duplicated one and the other memories 3 and 4. Then, for example, the address at the time of writing data by the program B in which the memory protection condition is not set and the address stored in the address storage device 8 are compared by the address comparator 7, and in the case of comparison match. Is memory 4
Important data is rewritten, an interrupt is made to the processor 1 to protect the important data.

FIG. 4 is an explanatory view of the fourth embodiment of the present invention, in which the same reference numerals as those in FIGS. 1, 2 and 3 indicate the same parts. This embodiment is a combination of the embodiments shown in FIG. 2 and FIG. 3. For example, the address at the time of writing important data by the program A that sets the memory protection condition is stored in the address storage device 8. When the data is stored and read from the memories 3 and 4, the data comparator 6 compares the data to detect whether or not the data has been rewritten, and the non-important data by the program B in which the memory protection condition is not set. The address comparator 7 compares the address at the time of writing with the address stored in the address storage device 8, and in the case of a comparison match, it indicates that important data in the memory 4 is rewritten. Interrupt to.

FIG. 5 is an explanatory view of the fifth embodiment of the present invention, in which the same reference numerals as those in the above-mentioned drawings indicate the same parts, and 9 indicates an abnormality information storage device. The abnormal information storage device 9 stores information including an address, data, and read / write at the time of comparison disagreement in the data comparator 7,
In addition, the address comparator 7 stores information including address, data and read / write at the time of comparison match. Therefore, by referring to the accumulated information of the abnormality information accumulating device 9, the situation of the abnormality occurrence can be recognized, which facilitates the search for the cause of the abnormality occurrence.

FIG. 6 is an explanatory view of a sixth embodiment of the present invention, in which the same reference numerals as those in the above-mentioned drawings indicate the same parts, and 10 indicates an abnormality occurrence reporting device. On the basis of the detection signals when the data comparator 6 does not compare and when the address comparator 7 compares, the abnormality occurrence reporting device 10 interrupts the processor 1 and determines the address at that time. Information including data and read / write is stored in addition to the abnormality information storage device 9.

FIG. 7 is an explanatory diagram of a seventh embodiment of the present invention, in which the same reference numerals as those in the above-mentioned respective drawings indicate the same parts, and 11 indicates a direct memory access control unit (DM).
A) 2-1 is a memory protection setting register. The dotted line path indicates the control signal path, and the alternate long and short dash line path indicates the detection signal path. Further, a state in which the programs A and B are stored in the program storage area 5 is shown.

The memory protection setting register 2-1 of the memory switching device 2 sets the above-mentioned memory protection conditions. For example, the memory protection setting is performed according to the memory protection request for storing important data from the program A. Set memory protection in register 2-1. And program A
The memory switching device 2 performs switching connection so as to exert the memory protection function. That is, in response to the access from the program A, the address bus and the data bus of the processor 1 are switched and connected to the address buses and the data of the duplicated memories 3 and 4, and the same connection is made to the duplicated memories 3 and 4. Add the address of. That is, the memory switching device 2 refers to the memory protection setting register 2-1 according to the read / write control signal, and controls the connection between the processor 1 side and the memories 3 and 4 according to the presence / absence of the memory protection condition setting. It has a configuration and can be realized by a relatively simple logic circuit or software.

Direct memory access controller 1
1 directly writes and reads data by directly accessing only the memory 4. The address in this case is also compared in the address comparator 7,
In the case of comparison and coincidence, the data read from one memory 3 and the data read from the other memory 4 are compared in the data comparator 6 to determine whether important data has been changed.

Further, in response to a comparison mismatch detection signal in the data comparison section 6 or a comparison match detection signal in the address comparator 7, the abnormality occurrence reporting device 10 interrupts the processor 1 (NMI: Non-Maskable). Int
The error information storage device 9 is notified. In accordance with this notification, the abnormality information storage device 9 stores information including the address at that time, data, and read / write. Further, the processor 1 preferentially starts the interrupt processing by the interrupt.

FIG. 8 is an explanatory diagram of a switching connection state of the memory switching device, (a) shows a state at the time of reading data by the program A in which a memory protection condition is set, and RD shows a read control signal. The memory switching device 2 is the processor 1
Is connected to the address buses of the duplicated memories 3 and 4, and the data bus of the processor 1 and the data bus of one memory 3 are connected to both the memories 3 and 4.
The same data is read from the same address of
The data read from is transferred to the processor 1. Further, the data read by a data comparator (not shown) is compared.

Further, FIG. 8B shows a state at the time of data writing by the program A in which the memory protection condition is set,
WT indicates a write control signal. The memory switching device 2 includes an address bus of the processor 1 and duplicated memories 3 and 4.
, And the data bus of the processor 1 and the data buses of the duplicated memories 3 and 4 are connected. As a result, the same data is written at the same address in both of the duplicated memories 3 and 4.

Further, FIG. 8C shows a state at the time of reading data by the program B in which the memory protection condition is not set, and the memory switching device 2 includes the address bus of the processor 1 and the duplicated memories 3 and 4. The data bus of the processor 1 and the data bus of the memory 4 on one side are connected, and data is read from the same address of the memories 3 and 4 on one side and the other side by the read control signal. Only the data from the other memory 4 is transferred to the processor 1. In this case, for example, the data by the program A is
It is also possible to read the program B for reference.

Further, FIG. 8D shows a state at the time of writing data by the program B in which the memory protection condition is not set, and the memory switching device 2 includes the address bus of the processor 1 and the address of the other memory 4. The data bus of the processor 1 and the data bus of the other memory 4 are connected to each other, and data is written only to the memory 4. As a result, the write access to the one memory 3 storing the important data is prohibited, so that the important data can be protected.

FIG. 9 shows a program for which memory protection is set in the embodiment shown in FIG. 6, for example, program A.
FIG. 7 is an explanatory diagram at the time of reading data by the memory switching device 2 according to a read control signal.
Since the memory protection request by the program A is set to 1, the address bus of the processor 1 and the address buses of the duplicated memories 3 and 4 are connected, and the data bus of the processor 1 and the data bus of the memory 3 are connected. And the read control signal RD is applied to both memories 3 and 4. As a result, data is read from the same address in both memories 3 and 4, respectively.

Then, the data read from both memories 3 and 4 are compared by the data comparator 6, and in the case of comparison match, the data read from the memory 3 is processed in the processor 1 and in the case of comparison mismatch. Applies the detection signal to the abnormality occurrence notifying apparatus 10, and the abnormality occurrence notifying apparatus 10 interrupts (NMI) the processor 1 and notifies the abnormality information accumulating apparatus 9, and the abnormality information accumulating apparatus 9 , And stores information including the address, data, and read / write at that time.

FIG. 10 is an explanatory diagram at the time of writing data by the program for which the memory protection is set in the embodiment shown in FIG. 6, for example, the program A, and the memory switching device 2 is controlled by the write control signal WT. Since the memory protection condition by the program A is set in the memory protection setting register 2-1, the address bus of the processor 1 and the address buses of the duplicated memories 3 and 4 are connected to each other, and the data bus of the processor 1 is connected. , The data buses of the duplicated memories 3 and 4 are connected, and the write control signal WT is applied to both memories 3 and 4. As a result, both memories 3, 4
The same data will be written to the same address. The address at that time is stored in the address storage device 8.

FIG. 11 is an explanatory diagram at the time of reading the data by the program without the memory protection setting, for example, the program B in the embodiment shown in FIG. 6, in which the memory switching device 2 is controlled by the read control signal RD. Since the memory protection condition is not set in the memory protection setting register 2-1, the address bus of the processor 1 and the address buses of the memories 3 and 4 are connected to connect the data bus of the processor 1 and the data bus of the memory 3. Are connected, and the read control signal RD is added to each part.

As a result, the address stored in the address storage device 8 (the address when the data is written in the memory 3) and the address on the address bus are compared by the address comparator 7, and if they do not match, Since the address for the memory 4 this time is different from the address of the data written in the memory 3, the data read from the memory 4 is transferred to the processor 1. In the case of comparison match in the address comparator 7, since the memories 3 and 4 are accessed with the same address, the data comparator 6 compares the data read from the memories 3 and 4. In the case of comparison match, it is determined that the data written in the duplicated memories 3 and 4 is normal, and the data read from the memory 4 is processed by the processor 1.
Transfer to. If the comparison does not match, it indicates that the data for which the memory protection is set has been changed, and therefore the abnormality occurrence notification device 10 interrupts (NMI) the processor 1.
Then, the information including the address, data, and read / write at that time is stored in the abnormality information storage device 9.

FIG. 12 is an explanatory diagram at the time of writing data by a program, for example, program B, in which the memory protection is not set in the embodiment shown in FIG. 6, and the memory switching device 2 is operated by the write control signal WT. Since the memory protection setting memory 2-1 has no memory protection condition set, the address bus and the data bus of the processor 1 are connected to the address bus and the data bus of the memory 4, and the write control signal WT is set. Add to each part.

The address comparator 7 includes an address storage device 8
The address stored in 1 is compared with the address of this time. If there is no comparison, the address of the data written in one memory 3 is different, so the data is written in the other memory 4. When the address comparison by the address comparator 7 indicates a comparison match, the address of the data written in the one memory 3 is the same, so the data written in the other memory 4 is rewritten. Therefore, the comparison coincidence detection signal is applied to the abnormality occurrence notification device 10 and an interrupt (NMI) is performed to the processor 1 to stop the writing in this case. As a result, it is possible to prevent the important data written in the other memory 4 from being rewritten. Further, information including the address, data, and read / write at that time is stored in the abnormality information storage device 9.

The processor 1 can search for the cause of the abnormality on the basis of the information on the occurrence of the abnormality stored in the abnormality information storage device 9. Therefore, the factor can be removed and stable information processing can be performed. Further, the address storage device 8 and the abnormality information storage device 9 may have a register configuration, and the abnormality occurrence notification device 10 may be an interrupt signal generation means for the processor. Further, as the duplicated memories 3 and 4, not only the semiconductor integrated memory, but also known memories of various configurations can be applied.

[0033]

As described above, according to the present invention, the one and the other memories 3 and 4 which are duplicated to be accessed by the processor 1 are switched by the memory switching device 2, and important data are protected by the memory. By setting the conditions, it becomes easy to determine whether or not the data has been changed by writing data to the same address in the memories 3 and 4 on one side and comparing data read from the same address. If you have not set the protection conditions,
By writing and reading data only to the other memory 4, important data can be protected. Therefore, regarding the data used for each program,
Data that is prohibited from being changed by other programs can be securely protected.

When data is written from a program in which the memory protection condition is not set, the address at that time is compared with the data write address by the program in which the memory protection condition is set, and when a comparison is made, Since important data is rewritten, it is possible to interrupt the processor to avoid it. In addition, by accumulating addresses and data when an error occurs,
There is an advantage that it is easy to search the cause of the abnormality.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a second embodiment of the present invention.

FIG. 3 is an explanatory diagram of a third embodiment of the present invention.

FIG. 4 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 5 is an explanatory diagram of a fifth embodiment of the present invention.

FIG. 6 is an explanatory diagram of a sixth embodiment of the present invention.

FIG. 7 is an explanatory diagram of a seventh embodiment of the present invention.

FIG. 8 is an explanatory diagram of a switching connection state of the memory switching device.

FIG. 9 is an explanatory diagram at the time of reading data by a program for which memory protection is set.

FIG. 10 is an explanatory diagram at the time of writing data by a program for which memory protection is set.

FIG. 11 is an explanatory diagram at the time of reading data by a program that does not perform memory protection setting.

FIG. 12 is an explanatory diagram at the time of writing data by a program that does not perform memory protection setting.

[Explanation of symbols]

1 processor (CPU) 2 Memory switching device 3,4 memory 5 Program storage area

Claims (6)

[Claims] 1. A dual memory that is accessed by a processor, and a memory switching device that performs switching connection between an address bus and a data bus between the processor and the dual memory, the memory switching device comprising: When data is written when a memory protection condition is given, switching connection is made so that the same data is written to the same address of the duplicated one and the other memories, and one is read when reading the data. Switched to transfer the data read from the above memory to the processor, and when writing the data when the memory protection condition is not given, switch to write the data to the other memory which is duplicated. When the data is read out and connected, the data read from the other memory is switched and connected so as to be transferred to the processor. Dual memory device. 2. The dual memory device according to claim 1, further comprising a data comparator for comparing data read from the same address of the one memory and the other memory of the dual memory. 3. An address storage device that stores an address when writing data to the one memory, and an address that compares the address stored in the address storage device with an address when writing data to the other memory. The dual memory device according to claim 1 or 2, further comprising a comparator. 4. An address storage device that stores an address when writing data to the one memory, and an address that compares the address stored in the address storage device with an address when writing data to the other memory. 2. The dual memory device according to claim 1, further comprising a comparator and a data comparator for comparing data read from the same address of the one memory and the other memory by comparing and matching by the address comparator. 5. An abnormality information accumulating device for accumulating information including an address and data at that time is defined as an abnormal occurrence when a comparison match by the address comparator and a comparison mismatch by the data comparator. The dual memory device of claim 4, wherein the dual memory device is a memory device. 6. The memory switching device has a memory protection setting register that sets a memory protection condition for controlling switching connection between one and the other of the memories duplicated with a processor according to a request from a program. The dual memory device according to claim 1, wherein the dual memory device comprises: