JP2006260393A - Cpu system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an obstacle caused by invalid data in a common memory in a host unit being a new operation system. <P>SOLUTION: In this CPU system, the host unit constitutes a redundant configuration, only the host unit of the operation system can access, it has a common memory 3 arranged on a common bus, and processing is transferred when switching system of the host unit. A condition of the common bus at timing when switching of system of the host unit occurs is held. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a CPU system, and more particularly to a CPU system capable of switching a host unit system.

  A host unit equipped with a processor (hereinafter referred to as a CPU) has a redundant configuration and can be accessed only when the host unit is switched over by having a common memory that can be accessed only by the active host unit and placed on a common bus. The configuration of the conventional CPU system will be described with reference to FIG. 5, and the state of the common bus when a failure occurs in the active host unit will be described with reference to FIG.

  In this configuration, when the host unit 1 is in the operating state and the host unit 2 is in the standby state, the host unit 1 sends data (information) for causing the CPU system to function via the common bus 103. Write to or read from.

  When the host unit system switching control is executed by the maintenance person in this state, the host unit 1 software waits for the host unit 2 with respect to the host unit 2 by the switching signal 101 after completing the process in the middle of execution. And the host unit 2 that has been in the normal standby state notifies the host unit 1 of the transition to the operation state by the switching signal 102.

  As a result, the system switching is completed in accordance with the normal system switching procedure mediated by software.

On the other hand, when a hardware failure occurs in the active host unit 1 or when a forced reset is executed, the host system 2 cannot be operated with respect to the host unit 2 by the switching signal 101 regardless of the processing being executed. The host unit 2 that has been in the normal standby state is forcibly switched over by transitioning to the operating state.
Japanese Patent Laid-Open No. 01-099138

  However, the host unit switching method in the conventional redundant configuration has the following problems.

  The problem is that if a hardware failure occurs in the active host unit 1 or if a forced reset is executed, the system is forcibly switched regardless of the processing being executed. At this time, the host unit 1 If the bus access to the common memory unit 3 is being executed, the bus access on the common bus 103 is interrupted, and if it is a write access, the data at that address may be rewritten as illegal data. When the host unit 2 that has become a new active system uses the data at the address as a processing takeover of the host unit 1, the host unit 2 may also fail and fall into a system down state because it is illegal data. It is.

  Accordingly, an object of the present invention is to prevent a failure caused by illegal data in a common memory in a host unit that has newly become an active system.

  As a means for solving the above problems, the present invention provides a host unit system having a redundant configuration and having a common memory that can be accessed only by the host system in an operational system and disposed on a common bus. A CPU system that takes over processing at the time of switching includes a common bus state recording unit that holds the state of the common bus at the timing when the system switching of the host unit occurs.

  In the CPU system in which a plurality of the host units whose load is distributed by the host unit is an active system, the host unit is changed to a switching signal of the host unit that triggers holding a common bus state. Use signals that indicate operational status.

  According to the present invention, in the CPU system in which the host unit has a redundant configuration, only the active host unit can be accessed, and has a common memory arranged on the common bus, so that processing is taken over when the host unit is switched over. Therefore, it is possible to prevent a failure caused by illegal data in the common memory in the host unit that has become a new operational system.

  The reason for this is that the status of the common bus at the timing when the host unit switchover occurred is maintained, so that the host unit that became the new active system has an interrupted bus access or not. This is because when there is an access, it is possible to recognize specific data in the common memory that may have been rewritten from the address information to illegal data.

  According to the present invention, not only in the case where the host unit has a redundant configuration, but also in a CPU system in which a plurality of host units for the purpose of load distribution are all active, a failure caused by illegal data in the common memory has not occurred. Can be prevented.

  The reason for this is that instead of using a host unit switching signal that triggers the maintenance of the common bus state, a signal indicating the host unit operating status is used, so that the host unit that continues to operate is the host unit that has failed If there is an interrupted bus access, it recognizes specific data in the common memory that may have been rewritten from the address information to invalid data. This is because it becomes possible.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

[Description of configuration]
As one embodiment of the present invention, the host unit has a redundant configuration, and only the active host unit is accessible and has a common memory arranged on the common bus, so that processing is taken over when the host unit is switched over. The configuration around the host unit and the common memory in the CPU system will be described with reference to FIG. 1, and the internal configuration of the common bus state recording unit 4 will be described with reference to FIG.

  In FIG. 1, host units 1 and 2 are connected to a common memory unit 3 via a common bus 103, and write and read data stored in the common memory unit 3.

  The common bus 103 is also connected to the common bus state recording unit 4, and the bus access on the common bus 103 executed by the host units 1 and 2 is also input to the common bus state recording unit 4.

  Switching signals 101 and 102 for controlling system switching between the host unit 1 and the host unit 2 are wired between the host units and are also input to the common bus state recording unit 4.

  In FIG. 2, the common bus 103 input to the common bus state recording unit 4 is connected to the common bus latch unit 5, and the switching signals 101 and 102 are connected to the latch signal generation unit 7.

  When the switching signal 101 or 102 detects that the system switching of the host unit has occurred, the latch signal generation unit 7 generates a latch signal to be connected to the common bus latch unit 5, and the common bus latch unit 5 operates on the common bus 103 at that timing. The common bus state at the time of system switching, which includes transfer address such as address, data, transfer method indicating writing or reading, and transfer attributes such as transfer size, is held.

  Reading of the common bus state at the timing of occurrence of system switching of the host unit is executed by read bus access to an address assigned in advance to the common bus state recording unit 4, and the buffer control unit 8 receives the address bus of the common bus 103 and When it is detected from the transfer attribute that the bus access started by the host unit is an address pre-assigned to the common bus state recording unit 4 and read access, the enable signal of the read buffer 6 is validated.

  The enabled read buffer 6 relays the information held in the common bus latch unit 5 to the data bus of the common bus 103, and the host unit indicates the state of the common bus 103 at the system switching occurrence timing when the own unit becomes the active system. Obtainable.

[Description of operation]
FIG. 1 shows a configuration around the host unit and the common memory in the CPU system, FIG. 2 shows an internal configuration of the common bus state recording unit 4, and FIG. 3 shows an operation flowchart when a system switchover occurs due to a failure of the active host unit. The operation of the present invention will be described.

  When the host unit 1 is in the operating state and the host unit 2 is in the standby state, the host unit 1 writes data (information) for causing the CPU system to function to the common memory unit 3 via the common bus 101, or Reading is executed at any time, the bus access on the common bus 103 executed by the host unit 1 is also input to the common bus state recording unit 4, and the switching signals 101 and 102 for controlling the host unit system switching are also in the common bus state. Input to the recording unit 4.

  When the host unit system switching control is executed by the maintenance person in this state, the host unit 1 software waits for the host unit 2 with respect to the host unit 2 by the switching signal 101 after completing the process in the middle of execution. And the host unit 2 that has been in the normal standby state notifies the host unit 1 of the transition to the operation state by the switching signal 102.

  As a result, the system switching is completed in accordance with the normal system switching procedure mediated by software.

  In the common bus state recording unit 4, the latch signal generation unit 7 that has detected that the system switching of the host unit has occurred due to the change of the switching signal 101 generates a latch signal connected to the common bus latch unit 5, and the common bus latch unit 5 holds the common bus state at the time of system switching, which includes addresses on the common bus 103 at that timing, data, a transfer method indicating writing or reading, and transfer attributes such as transfer size.

  At this time, since there is no process in the middle of being executed by the host unit 1, there is no bus access being executed on the common bus 103, and the common bus latch unit 5 holds the inactive common bus state.

  The host unit 2 that newly becomes the active system by the system switching executes the read bus access to the address assigned in advance to the common bus state recording unit 4.

  The buffer control unit 8 to which the address bus and transfer attribute of the common bus 103 are input detects that the bus access started by the host unit 2 is an address previously assigned to the common bus recording unit 4 and is a read access. Then, the enable signal of the read buffer 6 is validated.

  The enabled read buffer 6 relays the information held in the common bus latch unit 5 to the data bus of the common bus 103, and the host unit 2 is in the state of the common bus 103 at the time of system switching occurrence when its own unit becomes the active system. That is, a state indicating an inactive state (all signals are Hi level in the case of pull-up termination) is obtained, and it is recognized that there is no data that may be illegal in the data stored in the common memory unit 3. Then, take over the processing as the active host unit.

  On the other hand, system switching that does not follow the regular system switching procedure represented by hardware failure or forced reset is performed by the switching signal 101 to the host unit 2 regardless of the processing that the host unit 1 is executing. The host unit 2 that is in a normal standby state is notified that it has become inoperable, and system switching is forcibly performed by transitioning to the operational state.

  As in the case of normal system switching, in the common bus state recording unit 4, the latch signal generation unit 7 that detects that the system switching of the host unit has occurred due to the change of the switching signal 101 is latched to the common bus latch unit 5. A signal is generated, and the common bus latch unit 5 holds the common bus state at the time of system switchover including transfer addresses such as an address on the common bus 103 at that timing, data, a transfer method indicating writing or reading, and a transfer size.

  If the host unit 1 is executing bus access to the common memory unit 3 at the time of system switching, the bus latch unit 5 holds the address, data, and transfer attributes indicated by the bus access. Holds the common bus state of the state.

  The host unit 2 that newly becomes the active system by the system switching executes the read bus access to the address assigned in advance to the common bus state recording unit 4.

  The buffer control unit 8 to which the address bus and transfer attribute of the common bus 103 are input detects that the bus access started by the host unit 2 is an address previously assigned to the common bus recording unit 4 and is a read access. Then, the enable signal of the read buffer 6 is validated.

  The enabled read buffer 6 relays the information held in the common bus latch unit 5 to the data bus of the common bus 103, and the host unit 2 is in the state of the common bus 103 at the time of system switching occurrence when the self unit becomes the active system. That is, if the host unit 1 is executing bus access to the common memory unit 3 at the time of system switching, the address, data, transfer attribute indicated by the forcibly interrupted bus access, and inactive if the bus access is not being executed A state indicating the state (if the pull-up termination is used, all signals are at the Hi level) is obtained.

  If the state of the common bus is inactive, the processing as the active host unit is continued after recognizing that there is no data that may be illegal in the data stored in the common memory unit 3, When a write access to the common memory unit 3 is indicated, it is determined that there is a possibility that the data at the address has been rewritten as illegal data, and the data is invalidated, for example, not used in subsequent processing. Take over the processing as.

[Other embodiments]
Another embodiment of the present invention will be described with reference to FIG.

  The host unit shown in FIG. 1 has a redundant configuration and has a common memory arranged on a common bus, so that the host unit and the common memory peripheral configuration in the CPU system that takes over processing when the host unit is switched over, The common memory unit has a redundant configuration of 3-1 and 3-2, the common memory switching signals 301 and 302 are input to the common bus recording unit 4, and the common bus state recording unit 4 generates system switching of the common memory unit. Even when the switching signal 301 or 302 changes, it is detected that a system switching of the common memory unit has occurred, and the state of the common bus 103 at that timing is held.

  Note that the bus access to the common memory units 3-1 and 3-2 is executed only to the operating system address, and in the write access, the same data is written to the standby system common memory simultaneously with the writing to the operating system common memory. Then, it is assumed that only the operational common memory outputs data.

  In this embodiment, since it is possible to check the state of the common bus at the timing when system switching of the common memory unit occurs, system switching occurs due to a failure such as a memory failure in the operating system common memory unit. In this case, there is a new effect that useful information can be obtained for failure investigation such as identification of a defective part.

  The present invention can be used for a CPU system that prevents a failure caused by illegal data in a common memory.

It is a block diagram which shows the structure of CPU system as one embodiment of this invention. It is a block diagram which shows the internal structure of a common bus state recording part. It is a block diagram which shows the operation | movement of CPU system as one embodiment of this invention. It is a block diagram which shows the structure of other embodiment of this invention. It is a block diagram which shows the structure of the conventional CPU system. FIG. 6 is a block diagram showing a state of a common bus when a failure occurs in an active host unit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Host unit 2 Host unit 3 Common memory part 4 Common bus state recording part 5 Common bus latch part 6 Read buffer 7 Latch signal generation part 8 Buffer control part 101 Switching signal 102 Switching signal 103 Common bus

Claims (6)

In the CPU system in which the host unit has a redundant configuration, and only the active host unit is accessible and has a common memory arranged on a common bus so that processing is taken over when the host unit is switched over,
A CPU system comprising: a common bus state recording unit that holds a state of a common bus at a timing when system switching of the host unit occurs. In a CPU system in which a plurality of the host units whose host units are intended for load distribution are all active,
A CPU system, wherein a signal indicating an operation state of the host unit is used instead of the switching signal of the host unit which is an opportunity to hold a common bus state. The common bus state recording unit detects a occurrence of system switching of the host unit and generates a latch signal;
The CPU system according to claim 1, further comprising a common bus latch unit that holds a common bus state at the time of occurrence of system switching, which includes transfer attributes on the common bus. A buffer control unit for detecting that the bus access initiated by the host unit from the input address bus and transfer attribute of the input is an address pre-assigned to the common bus state recording unit and a read access; The CPU system according to claim 3, further comprising: The CPU system according to claim 1, comprising a plurality of the common memories. 6. The CPU system according to claim 5, wherein there are two common memories.

Images