JPH0944273A - Storage device initializing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To construct an electronic computer having high reliability by performing high-speed initialization when turning on a power source in the case of providing a main storage device with error correction information or a cache storage system. SOLUTION: A storage device initializing circuit is provided with an initialization data circuit 5 to be operated only when turning on the power source, address generation circuit 6, reset holding circuit 7, timing generation circuit 8, write control circuit 9, data selector 12 and address selector 13 in addition to a CPU 1 main memory 2, error correction generating circuit 10 and error detection circuit 11 constituting a conventional electronic computer system. Thus, even when any error is generated at the time of read from a storage device at the time point when the CPU starts working, the fault can be detected and a high-reliability system can be constructed. Besides, the start-up time of electronic computer can be shortened.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a central processing unit (hereinafter CP
A memory for initializing the information in the memory when the normal operation cannot be expected in the situation where the initial values of the information held by the main memory (hereinafter referred to as U) and the tag memory are indeterminate. The present invention relates to a device initialization circuit.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional electronic computer in which an error correction function is added to a main memory. In this system, the reset circuit outputs the reset signal 25 when the power is turned on. The reset signal 25 initializes the CPU 1, but the contents of the main memory 2 remain in an indefinite state when the power is turned on. Since the error correction information is added to the main memory 2 in order to improve the reliability of the electronic computer, when the CPU 1 reads the main memory 2 without initializing the memory contents, the error detection circuit 11 detects the data and the data. An error occurs when a mismatch with the error correction information corresponding to is detected.

In order to prevent this inconsistency, the firmware 36 (hereinafter referred to as a boot loader) that operates when the power is turned on performs a write operation to the main memory 2 before operating the basic software such as the operating system. Correct error correction information is generated by the error correction generation circuit 10, and the main memory 2 is initialized.

FIG. 7 shows the configuration of another electronic computer system which incorporates a cache storage system. The reset signal 25 output by the reset circuit in response to power-on or a reset request from the operator initializes the CPU 1 and the cache controller 33. However, the contents of the tag memory 4 are indefinite when the power is turned on. Further, when the data is initialized by the reset request, all the data cached before the reset must be invalidated, but it is determined that the data is valid because the data has not been initialized. Therefore, if the CPU 1 starts up without performing initialization,
It reads meaningless data and does not operate normally. In order to prevent such a problem, the contents of the tag memory 4 are initialized in the boot loader 36 in a state where the cache is not performed.

[0005]

As the performance and functionality of hardware and software have increased, the capacity of main memory and cache memory that must be initialized increases,
There is a problem that the processing time when initialization is performed by software becomes long. In particular, for an electronic computer used in a system that needs to be turned on and off frequently, the waiting time from when the system is activated until the function is actually exhibited becomes long, and the responsiveness of the system is lost. There was a problem.

Further, when the initialization is executed by the boot loader, there is an error in the initialization operation itself, and the CPU reads an uninitialized address or executes an invalid instruction during the initialization operation. There is a possibility that it will happen, and it is hard to say that it is a highly reliable system.

[0007]

In the first embodiment, a main memory to which error correction information is added, and a circuit for controlling initialization of the main memory when power is turned on (hereinafter referred to as main memory initialization circuit). By writing known data in the main memory during the reset operation of the CPU without software intervention, the correspondence between the data and the error correction information corresponding thereto is corrected (hereinafter referred to as initialization). This provides normal memory access after power is turned on.

In the second embodiment, a main memory including a plurality of banks to which error correction information is added and a main memory initialization circuit are provided, and during the reset operation of the CPU,
A plurality of storage elements in different banks are simultaneously initialized to provide normal memory access after power is turned on.

In the third embodiment, a main memory having error correction information, which is composed of a dynamic random access memory (hereinafter referred to as DRAM), and its DRA.
A circuit in which an initialization circuit is added to a circuit for reading / writing and refreshing M (hereinafter referred to as a DRAM controller with initialization) is provided to initialize the DRAM while outputting a reset signal to the CPU when the power is turned on. Provide normal memory access after input.

In the fourth embodiment, the main memory to which the error correction information is added and the direct memory access (hereinafter referred to as DM
A. ), And a circuit (hereinafter, referred to as an initialization control circuit) for setting the DMA controller to perform initialization when the power is turned on. Initializes all main memory and provides normal memory access after power on.

The fifth embodiment is provided with a cache memory, a tag memory, and a control circuit (hereinafter referred to as a cache initialization circuit) for initializing the tag memory at power-on or reset operation, without software intervention. During the CPU reset operation, the contents of the tag memory are rewritten to a state in which the cache is invalid, and normal tag information after reset is provided.

[0012]

The initialization circuits of the first, second, third and fourth embodiments guarantee a normal operation for the reading operation of the main memory after the power is turned on.

The cache memory initialization circuit of the fifth embodiment guarantees reading from the main memory for the read operation of the CPU by invalidating all the contents of the cache memory after reset, and the system after reset is reset. Guarantee normal return.

[0014]

【Example】

Embodiment 1 FIG. FIG. 1 is a block diagram showing the first embodiment.
Conventionally, the CPU 1 and the main memory 2 were directly connected by the internal bus, but in the present invention, they are connected via the address selector 13 and the data selector 12. The data signal line 22 of the main memory is connected to either the data bus 21 selected by the data selector 12 or the output of the initialization data circuit 5 in which the data to be filled in the main memory is preset. . Further, either the address bus 20 selected by the address selector 13 or the address generated by the address generation circuit 6 is connected to the address signal line of the main memory.

When the power-on signal is generated by turning on the power, the reset holding circuit 7 outputs the reset signal to the CPU 1 and the timing generation circuit 8. Upon receipt of this reset signal, the timing generation circuit 8 switches between the address selector 13 and the data selector 12, and the main memory 2
CPU1 is cut off from. Also, the address generation circuit 6
Sequentially generates all the addresses of the main memory 2. The write control circuit 9 controls the write of the main memory 2 in synchronization with the address generation circuit 6.

When writing data, the error correction generating circuit 10 calculates error correction information matching the write data, and then writes both the data and the error correction information to the main memory 2.

The address generating circuit 6 sequentially increases the address in synchronization with the timing signal from the timing generating circuit 8. When all the addresses have been generated, the timing generation circuit 8 notifies the reset holding circuit 7 of the completion of initialization, and releases the reset signal to the CPU 1.

Embodiment 2 FIG. FIG. 2 is a block diagram showing the second embodiment. The CPU 1 and the main memory 2 are connected via the address selector 13 and the data selector 12. Data to be filled in the main memory is preset in the initialization data circuit 5. In this example, the main memory 2 has two banks, a bank A14 and a bank B.
Since it is composed of 15, the access from the CPU 1 is via the bank selector 14 which switches the bank according to the address.

The reset holding circuit 7 outputs a reset signal to the CPU 1 and an initialization request to the timing generation circuit 8 when a power-on signal is input by turning on the power.

In response to the initialization request, the timing generation circuit 8 switches the address selector 13 and the data selector 12 and disconnects the CPU 1 from the main memory 2. Further, the address generation circuit 6 sequentially generates all the addresses in one bank forming the main memory 2. The write control circuit 9 is synchronized with the address generation circuit 6 and forms a bank A14 and a bank B1 that constitute the main memory 2.
At the same time, write control is performed on 5. At this time, the error correction generation circuit 10 adds appropriate error correction information.

The address generation circuit 6 sequentially increases the addresses in the bank in synchronization with the timing signal from the timing generation circuit 8. When the address generation circuit 6 finishes generating all the addresses in the bank, it outputs an end signal to the timing generation circuit 8, and the reset holding circuit 7 outputs C.
Release the reset signal to PU1.

Example 3. FIG. 3 is a block diagram showing the third embodiment. There is a main memory 3 composed of a CPU 1 and a DRAM, and a DRAM controller 30 with initialization is interposed for access from the CPU 1 and peripheral circuits (not shown). The conventional DRAM controller controls the timing of reading and writing to the DRAM by the timing generation circuit 8, performs the refresh operation at each time set by the refresh timer 16, and further arbitrates the normal read / write and the refresh operation. Perform at 17.

The configuration circuit of the DRAM controller with initialization 30 includes, in addition to the above DRAM controller, an initialization circuit 15, an address generation circuit 6, an initialization data circuit 5, an address selector 13, and a data selector as shown in FIG. 12
Is provided. The initialization circuit 15 receives a power-on signal when the power is turned on and generates a control signal for initializing all DRAMs.

Initialization circuit 15 receiving the power-on signal
Is a refresh timer 16 and a timing generation circuit 8
Reset to. The timing generation circuit 8 generates an idle read cycle for normal operation of the DRAM after reset, and notifies the initialization circuit 15 when this is completed. Upon receiving this notification, the initialization circuit 15 switches the data selector 12 to the initialization data circuit 5 side, and the initialization data circuit 5 generates data. At the same time, the address selector 13 is switched to the address generation circuit 6 side, and the address generation circuit 6 sequentially generates the addresses of all the main memories. Further, the arbitrator 17 is requested to write the initialization data, and the refresh timer 16 requests the refresh operation and performs the arbitration. When the address generation circuit 6 finishes generating all addresses, the initialization circuit 15
Is notified, the reset to the CPU 1 is released, and the initialization operation ends.

Example 4. FIG. 4 is a block diagram showing the fourth embodiment. The CPU 1, the main memory 2, and the DMA controller 31 share the address bus and the data bus, and
The MA controller 31 includes a reset holding circuit 7 that receives a power-on signal generated by power-on and generates a reset signal, and a DMA controller 31 that receives the power-on signal.
An initialization control circuit 32 for performing initialization and data transfer is connected.

The initialization control circuit 32 receives the power-on signal and resets the DMA controller 31, and thereafter sets the DMA transfer source and transfer destination to the head address of the main memory 2 and sets the number of transfer words in the main memory. Set to the total number of words and request DMA. DMA controller 3
When 1 reads the transfer source address, the data selector 12 is switched to the initialization data circuit 5 to force the initialization data to be read. At this time, since an error occurrence is predicted in the main memory 2, this error occurrence signal is suppressed by the error disconnector 35.

When the DMA controller 31 writes to the transfer destination address, the data selector 12 uses the DMA
The controller 31 is switched to and the initialization data is written to the main memory 2. When all the transfers are completed and the transfer completion notification is generated from the DMA controller 3, the reset holding circuit 7 releases the reset to the CPU 1 and ends the initialization operation.

Example 5. FIG. 5 is a block diagram showing the fifth embodiment. All memory access from the CPU 1 is entrusted to the cache controller 33. When the direct mapping method is used as the method of configuring the cache memory, the tag memory 4 and the cache memory 34 are connected as shown in FIG.

In the conventional cache controller, CP
In response to the read access from U1, the tag in the tag memory 4 is first referred to, and if the data is valid, the data is read from the cache memory 34. If it is invalid, the reading operation of the corresponding address to the main memory 2 is performed, and at the same time, the writing to the cache memory 34 and the tag update are performed. Regarding writing, in the case of the write-through method, the corresponding tag in the tag memory 4 is updated and writing is performed in both the cache memory 34 and the main memory 2.

The cache initialization circuit according to the present invention comprises a reset holding circuit 7, a timing generation circuit 8, an address generation circuit 6, an initialization data circuit 5, and an address selector 13 in addition to the above cache controller.

When a reset request circuit (not shown) requests a reset, the reset holding circuit 7 causes the CPU 1
Can be reset. During this time, the address generation circuit 6 generates tag addresses for the number of tags in the tag memory 4, and in synchronization with the timing generation circuit 8, the data of the initialization data circuit 5 indicating that the cache is invalid is added to the tag memory. Write to 4. When the generation of all tag addresses is completed, the reset holding circuit 7 releases the reset, and the CP
U1 starts.

[0032]

Since the present invention is configured as described above, it has the following effects.

When a series of initialization operations according to the inventions of the first, second, third and fourth embodiments is completed, the CPU
When the main memory is read, it is guaranteed that the data to be read and the error information corresponding to this data are consistent, so no error occurs.
Further, if an error occurs, it can be detected that the circuit storing the data has a failure, and a highly reliable system can be constructed. Further, since this initialization circuit is realized by hardware, it is faster than the writing operation executed by software, and initialization can be executed in a short time even for a large capacity main memory.

In addition to the above, the effect of the second embodiment is as follows.
Since a large-capacity memory system is usually managed by being divided into a plurality of banks, this feature is utilized to implement the first embodiment.
The present invention is modified so that memories of different banks can be simultaneously written. Therefore, when there are n banks of the main memory, the initialization is completed in 1 / n of the time required for the initialization according to the invention of the first embodiment, and there is an effect that the speed can be increased.

The effect of the third embodiment is that the large-capacity memory system is composed of the normal DRAM, and the relatively small-scale circuit is added to the existing memory system. This has the effect of enabling high speed conversion and improving reliability.

The effect of the fourth embodiment is that a relatively small circuit is added to the DMA controller, which is included in a general computer system, to perform initialization at high speed and to obtain high reliability. There is.

The effect of the fifth embodiment is that, when the initialization of the large capacity cache memory is executed by software, the complicated and redundant access must be executed after sufficiently understanding the cache mechanism. It takes time to produce and execute. By performing this by hardware, it is possible to initialize a large-capacity cache memory in a short time, and there is an effect that the trouble of creating an initialization program can be saved.

Further, since all the caches are invalidated at the time of resetting, the malfunction caused by the uncertain cache information appearing in the cache memory when the power is turned on is eliminated. Further, even in the case of a fatal state where a reset is required, the operation at the time of restart can be guaranteed by eliminating invalid cache information, and high reliability can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention.

FIG. 6 is a block diagram of a conventional computer using a main memory including error correction information.

FIG. 7 is a block diagram of an electronic computer using a cache memory system of a direct mapping system according to a conventional technique.

[Explanation of symbols]

1 CPU, 2 main memory, 3 main memory (D
RAM), 4 tag memory, 5 initialization data circuit, 6
Address generation circuit, 7 reset holding circuit, 8 timing generation circuit, 9 write control circuit, 10 error correction generation circuit, 11 error detection circuit, 12 data selector, 13 address selector, 14 bank selector, 15
Initialization circuit, 16 refresh timer, 17 arbitrator, 18 DRAM write control circuit, 19 multiplexer, 20 address bus, 21 data bus, 22
Data signal line, 23 error correction signal line, 24 error occurrence signal line, 25 reset signal line, 30 D with initialization
RAM controller, 31 DMA controller, 32
Initialization control circuit, 33 cache controller, 34
Cache memory, 35 error disconnector, 36 boot loader.

Claims (5)

[Claims] 1. A central processing unit, an error detection circuit for detecting whether or not the information read from the main storage unit by the central processing unit has an error, and an error correction circuit for correcting the detected erroneous information. , A reset generation circuit that generates a reset signal when the power is turned on, a reset holding circuit that holds this reset signal during the initialization operation, and a timing that outputs a timing signal that gives a fixed time interval during the output of this reset signal A generation circuit, an address generation circuit whose address increases according to this timing signal, a write control circuit that performs a write operation to the main memory device in synchronization with the timing signal, and an address line and a data line are switched during the output of a reset signal. A storage device initialization circuit including an address selector and a data selector. 2. The storage device initialization circuit according to claim 1, further comprising a main storage device including a plurality of banks, wherein the plurality of banks are switched by a bank selector. 3. A memory element constituting a main memory device is a dynamic random access memory, and a refresh timer for activating a refresh operation at regular intervals for controlling the memory element, the refresh operation, and a central processing. The arbitrator for arbitrating access to the main memory by the device, a write control circuit for performing access permitted by the arbitrator, and a multiplexer for supplying an address in a time division manner. Memory device initialization circuit. 4. An initial stage comprising a direct memory access control circuit for executing a direct memory access, wherein the direct memory access control circuit performs a setting for continuously writing predetermined information to a main memory device during output of a reset signal. An initialization control circuit, an initialization data circuit that holds the predetermined information, and a data selector that switches the initialization data and a normal data line during a reset signal output. A storage device initialization circuit as described. 5. A central processing unit, a main memory, a cache memory having a copy of a part of the information held by the main memory and accessing at a speed higher than that of the main memory, and information held by the cache memory. A tag holding memory for holding information for determining whether it is valid or invalid, a reset holding circuit that outputs a reset signal in response to a reset request to the central processing unit, and a timing at predetermined time intervals during the output of the reset signal. A timing generation circuit that outputs a signal, an address generation circuit that sequentially increases the address of the cache memory in synchronization with the timing that the timing generation circuit outputs, an address generated by the address generation circuit, and an address line during normal operation And an initialization data circuit for holding predetermined information. Storage device initialization circuit.