JPH1078919A - Device for preventing illegal access - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an illegal access preventing device in which not only the illegal processing of a processor part but also the writing of illegal data or the illegal operation of an outside device can be prevented. SOLUTION: A reference memory part 5 stores illegal access detection data. At the time of the access check of a memory part 3 and an I/O part 4, an address or a command or the like is compared with the illegal access detection data, and the permission/inhibition of read and write, access to an unused area, and the normality/abnormality of an address or the like is checked. When the access is normal, a gate 3-3 or 4-3 of the memory part 3 or the I/O part 4 is opened so that the access can be attained. When illegal access is generated, the gate 3-3 or 4-3 is left closed so that the illegal access to the memory part 3 or the I/O part 4 can be inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an unauthorized access prevention device, and more particularly to an unauthorized access prevention device for a computer system.

[0002]

2. Description of the Related Art A processor (CPU) of a computer system is connected via a bus line to a ROM (Read Only Memory) or a RAM (Random Access Memory).
And an external device such as an input / output device or a peripheral device is accessed and controlled via an I / O interface. Access from the processor unit is performed based on each address. For example, accessing an address of an unused memory system or an address of an I / O interface to which a peripheral device or the like is not connected is called illegal (address) access. This unauthorized access occurs due to a software bug, pulse noise, or the like, and causes a runaway of the processor unit (CPU).

In Japanese Patent Application Laid-Open No. Hei 4-21040, all illegal addresses to be detected are stored in a reference memory in advance. Then, the address output when the device is actually accessed is monitored and compared with the contents of the reference memory. When an illegal access occurs, an interrupt is notified to the processor. The processor stops processing by this interrupt. A method has been proposed.

[0004]

Problems to be Solved by the Invention
In the case of the proposal described in Japanese Patent Application Laid-Open Publication No. H08-209, if illegal data is read due to illegal address access, illegal processing of the processor is prevented by stopping the processor processing by interruption due to detection of illegal access. It is not possible to prevent the danger that unauthorized data is written or that an external device (such as an input / output device or a peripheral device) performs an illegal operation by address access.

An object of the present invention is to provide an unauthorized access prevention device which can prevent not only unauthorized processing of a processor unit due to an unauthorized address access but also writing of unauthorized data and unauthorized operation of an external device.

[0006]

According to the present invention, there is provided an apparatus for preventing unauthorized access of a computer system in which a processor section including a computer controls while accessing an address of a first memory or an external device via a bus line. A second memory connected to a bus line and previously storing unauthorized access detection data corresponding to the address, a gate circuit inserted between the bus line and the first memory or an external device, and the processor Access for controlling access to the processor unit by opening the gate circuit only when it is detected that there is no unauthorized access by comparing an address to be accessed by the unit with the unauthorized access detection data corresponding to the address; And control means.

The operation of the present invention is as follows. In FIG. 1, a reference memory unit 5 has a memory unit 3 in advance.
And unauthorized access detection data at the time of access by the I / O unit 4. The reference memory unit 5 outputs unauthorized access detection data according to the address output by the processor unit 1.

The access check of the memory unit 3 and the I / O unit 4 includes an address for accessing the memory unit 3 and the I / O unit 4, a command such as read or write, and an unauthorized access output from the reference memory unit 5. The detected data are compared with each other to check whether read permission / prohibition, write permission / prohibition, access to an unused area, normal / abnormal address, and the like are performed. If the access is normal, the gate 3-3 or 4-3 of the memory unit 3 or the I / O unit 4
Open and allow access.

When an illegal access occurs due to a software bug or a hardware failure, etc., an inconsistency occurs between the address and the command and the illegal access detection data, so that the gate 3-3 or 4-3 is closed. The unauthorized access to the memory unit 3 or the I / O unit 4 is prohibited. Also, when unauthorized access occurs,
Immediately notifies the processor unit 1 of the occurrence of unauthorized access 6.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In FIG. 1, a processor unit (CP
U) 1 is constituted by a microprocessor or the like, and controls data input, processing and output according to a program (software) stored in the memory unit 3.

The memory unit 3 includes a memory 3-1 composed of a semiconductor memory or the like, an access error check circuit 3-
2, and a gate 3-3. The memory 3-1 stores data or the like input or output according to a program executed by the processor unit 1. The access error check circuit 3-2, based on the unauthorized access detection data output from the reference memory section 5, performs unauthorized access to the memory 3-1 (permission / prohibition of read, permission / prohibition of write, access to unused area). Access, address normal / abnormal).

When the access is normal, the gate 3-3
By instructing the gate to open, the memory 3-
1 can be accessed. At the time of unauthorized access, the gate 3-3 is kept closed to prohibit access to the memory 3-1 and notify the processor unit 1 of the unauthorized access. The gate 3-3 is controlled by a control signal from the access error check circuit 3-2.
The access to the memory 3-1 is controlled.

The I / O unit 4 comprises an I / O interface 4-1 with external devices (input / output devices, peripheral devices, etc.), an access error check circuit 4-2, and a gate 4-3. Is basically the same as the memory unit 3, and the description of the operation is omitted.

The reference memory section 5 is composed of a semiconductor memory or the like, and stores unauthorized access detection data for the access error check circuit 3-2 or 4-2 to detect unauthorized access. Then, it monitors the address line 2-1 of the bus line 2, and outputs unauthorized access detection data corresponding to the address to the access error check line 2-5.

The bus line 2 includes an address line 2-1, a data line 2-2, a command line 2-3, a ready line 2-4, and an access error check line 2-5. The address line 2-1 transmits an address signal output from the processor unit 1. The data line 2-2 transmits data input / output to / from the processor unit 1, the memory unit 3, and the I / O unit 4. The command line 2-3 transmits a predetermined command output from the processor unit 1.

The ready line 2-4 transmits a ready signal output from the memory unit 3 or the I / O unit 4 when access is permitted. Access error check line 2-5
Transmits the unauthorized access detection data output from the reference memory unit 5.

FIG. 2 shows a memory map of the memory 3-1. For example, as shown in the figure, access to the memory 3-1 is performed in such a manner that a work area from 000000H to 00FFFFH is permitted to read and write, a program area from 010000H to 01FFFFH is permitted to read only, and a data recording area from 020000H to 02FFFFH is permitted only to write. Unused areas from 030000H to FFFFFFH are prohibited from reading and writing.

As shown in FIG. 3, the reference memory unit 5
As the unauthorized access detection data, address error detection data, read permission / prohibition status, and write permission / prohibition status are set for all addresses. In addition,
It is conceivable to add 1-bit parity or error correction data having a multi-bit structure to the address error detection data. In the case of this embodiment, description will be made assuming that 1-bit parity is added.

The reference memory unit 5 first stores 000000H to 0
Read permission, write permission, and address parity are stored in 0FFFFH. Similarly, data is stored from 010000H to FFFFFFH.

The data set in the reference memory unit 5 is defined as follows. Bit 1 (D0) is for read enable /
The prohibition status is set, and 0: permitted and 1: prohibited. Bit 2 (D1) sets a write permission / prohibition status, where 0: permission and 1: prohibition. Bit 3 (D
3) sets the address parity and sets 0 for each address.
Or set 1.

After executing the program, the processor unit 1 accesses the memory unit 3 and the I / O unit 4 via the bus line 2. When the processor unit 1 accesses the memory unit 3, an address signal is output from the processor unit 1 via the address line 2-1 and at the same time, a command such as data reading is sent to the memory unit 3 via the command line 2-3. Output to

At this time, the reference memory unit 5 monitoring the address line 2-1 outputs unauthorized access detection data corresponding to the address to the memory unit 3 via the access error check line 2-5. For example, the processor unit 1
When accessing the address 000000H (see FIG. 2) of the memory unit 3 (of the memory 3-1), the 00 of the reference memory unit 5 is accessed.
The data at address 0000H (see FIG. 3) is output.

In the memory section 3, the address, command, and unauthorized access detection data sent via the address line 2-1, the command line 2-3, and the access error check line 2-5 are sent to the access error check circuit 3-2. Enter and check for unauthorized access. In this unauthorized access check, address data and commands (read, write, etc.) are checked as follows.

When the processor unit 1 makes a normal access, the access error check circuit 3-2 determines that the access is normal, outputs an enable signal to the gate 3-3, opens the gate 3-3, and opens the memory 3-1. Data is output to the data line 2-2 from the corresponding address. After the access to the memory unit 3 is completed, a ready signal indicating the end of the access is output to the processor unit 1 via the ready line 2-4. Note that, for convenience of explanation, the ready signal is always on (access end).

The processor unit 1 stores 0000 in the memory 3-1.
When an attempt is made to access the address 00H (work area), an error occurs in the address line 2-1 of the bus line 2 due to a hardware failure or the like, and the address becomes, for example, 000001.
If the address has changed to address H, the access error check circuit 3-2 detects the parity error by comparing with the address parity of the illegal access detection data, the gate 3-3 remains closed, and the access to the memory 3-1 is continued. Access is forbidden and protects data. At the same time, an unauthorized access is notified to the processor unit 1 via the unauthorized access notification line 6.

Due to a bug in the program, the processor unit 1 is permitted to read only the memory 3-1.
When trying to write to the address (program area)
The access error check circuit 3-2 detects an unauthorized access because the write permission / prohibition status of the unauthorized access detection data is prohibited. And gate 3-
3 remains closed, access to the memory 3-1 is prohibited, and the data is protected. At the same time, processor unit 1
Is notified of the unauthorized access via the unauthorized access notification line 6.

The processor unit 1 determines that only writing to the memory 3-1 is permitted due to a bug in the program or the like.
When trying to read the address (data recording area)
The access error check circuit 3-2 detects the unauthorized access because the read permission / prohibition status of the unauthorized access detection data is prohibited. And gate 3-
3 remains closed, access to the memory 3-1 is prohibited, and the data is protected. At the same time, processor unit 1
Is notified of the unauthorized access via the unauthorized access notification line 6.

Due to a program bug or the like, the processor unit 1 sets the read / write prohibition of the memory 3-1 to 030000H.
When accessing the address (unused area), the access error check circuit 3-2 detects the illegal access because the read permission / prohibition status and the write permission / prohibition status of the unauthorized access detection data are both prohibited. . Then, the gate 3-3 remains closed, and access to the memory 3-1 is prohibited. At the same time, an unauthorized access is notified to the processor unit 1 via the unauthorized access notification line 6.

In each case, when the unauthorized access is notified to the processor unit 1, the processor unit 1 performs processing for the unauthorized access (notification of occurrence of unauthorized access to the outside, notification of the processing, and the like).

As shown in the timing chart of FIG.
The address a is output from the processor unit 1, and at the same time, a certain command (memory read, memory write, I /
O read, I / O write, etc.) b are output. At the time of data writing, the data line 2-
2, the data c is output. At the time of data reading, data d is output from the memory unit 3 and the I / O unit 4 to the data line 2-2.

For convenience of explanation, the ready signal (ready line 2-4) e is kept on. When the address a is output from the processor unit 1, the unauthorized access detection data f is read from the reference memory 5 by the access error check line 2.
Output to -5. When an unauthorized access occurs, an unauthorized access is notified to the processor unit 1 via the unauthorized access notification line 6.

[0033]

As described above, the present invention detects an illegal access (read error, write error) due to a program bug or the like, and an address error due to a hardware failure, etc. This has the effect of preventing unauthorized access to external devices (such as input / output devices and peripheral devices) through I / O, protecting data and preventing unauthorized operation of the external devices.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a memory map of a memory unit.

FIG. 3 is a diagram illustrating an example of data storage in a reference memory.

FIG. 4 is a timing chart of the embodiment of the present invention.

[Explanation of symbols]

 1 Processor Unit 2 Bus Line 2-1 Address Line 2-2 Data Line 2-3 Command Line 2-4 Ready Line 2-5 Access Error Check Line 3 Memory Unit 3-1 Memory 3-2, 4-2 Access Error Check Circuit 3-3, 4-3 Gate 4 I / O unit 4-1 I / O interface 5 Reference memory unit 6 Unauthorized access notification line

Claims (3)

[Claims] 1. An unauthorized access prevention device for a computer system in which a processor unit including a computer controls while accessing an address of a first memory or an external device via a bus line, the processor unit being connected to the bus line. The second memory in which the unauthorized access detection data corresponding to the address is stored in advance, the gate circuit inserted between the bus line and the first memory or an external device, and the processor unit attempts to access. Access control means for opening the gate circuit and accessing the processor unit only when it is detected that the access is not unauthorized by comparing the address to be accessed and the unauthorized access detection data corresponding to the address. A device for preventing unauthorized access. 2. The unauthorized access prevention device according to claim 1, wherein the access control unit notifies the processor unit of the occurrence of the unauthorized access when detecting the unauthorized access. 3. The unauthorized access prevention device according to claim 1, wherein the unauthorized access detection data includes address error detection data, a read permission / prohibition status, and a write permission / prohibition status.