JPH11161548A - Computer with runaway detection function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the damages of a computer in the case that a CPU runs away and to prevent a load from being put on the CPU by simple constitution. SOLUTION: This computer is constituted of the CPU 1, a ROM 2 connected to the CPU 1 through a bus line 50, a RAM 3 connected to the CPU 1 through the bus line 50, an EEPROM 4 connected to the CPU 1 through the bus line 50, a gate array 7 connected to the CPU 1 through the bus line 50 and provided with a register 5 for stack area overflow detection and a stack overflow detection circuit 6 and a CPU reset circuit 10 connected to the CPU 1 through a signal line 8 and connected to the gate array 7 through the signal line 9. In this case, when the CPU 1 runs away, incorrect access executed to a specified memory by the CPU 1 is detected in incorrect memory access detection means (register 5 and detection circuit 6) and the reset request signals of the CPU 1 are outputted to a CPU reset means (CPU reset circuit 10). The CPU reset means to which the output is inputted executes a reset operation to the CPU 1 and stops the runaway of the CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer with a runaway detection function, and more particularly, to a computer with a runaway detection function for detecting illegal memory access of a CPU.

[0002]

2. Description of the Related Art A computer having a runaway detection function of this type is conventionally known as shown in FIG. In the figure, a CPU 900, the CPU 900 and a bus 95
ROM 901 connected through the CPU 900
And a RAM 902 connected via the bus line 950
An EEPROM 903 connected to the CPU 900 via the bus line 950; and a gate array connected to the CPU 900 via the bus line 950 and having a watchdog timer error detection register 905 and a watchdog timer error detection circuit 909. 904, and a CPU reset circuit 908 connected to the CPU 900 via a signal line 906 and connected to the gate array 904 via a signal line 907.

In the above configuration, the CPU 1 accesses the watchdog timer error detection register 905 at a constant cycle. On the other hand, the watchdog timer error detection circuit 909 monitors the access. Here, if the CPU 1 runs away and the access to the watchdog timer error detection register 905 is delayed, and the access to the watchdog timer error detection register 905 is not performed within the time set as the watchdog timer, The watchdog timer error detection circuit 909 detects a watchdog timer error and outputs a reset request signal of the CPU 1 to the CPU reset circuit 908 via the signal line 907. The CPU reset circuit 908 that has received the reset request signal executes the reset of the CPU 1 via the signal line 906.

[0004]

In the above-mentioned conventional computer with a runaway detection function, if the set time of the watchdog timer is too long, detection of the runaway of the CPU is delayed and the damage is increased. There is a problem that the processing load increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a computer with a runaway detection function that has a simple configuration and minimizes damage to the computer when the CPU runs away and does not load the CPU. And

[0006]

According to one aspect of the present invention, there is provided a computer comprising a CPU and various memories, wherein the unauthorized memory detects an unauthorized memory access of the CPU. An access detection unit, a CP connected to the unauthorized memory access detection unit and receiving a CPU reset request signal output by the unauthorized memory access detection unit to reset the CPU;
U reset means is provided.

In the invention according to claim 1, the CPU detects an unauthorized access executed by the CPU to a specific memory when the CPU runs out of control, and the CPU detects the unauthorized access and executes the CPU. A reset request signal of the CPU is output to the reset means. The CPU reset means, which receives this output, executes a reset operation on the CPU to stop the runaway of the CPU.

As described above, the illegal memory access detecting means is configured to reset the CPU when the CPU detects that the CPU has accessed the illegal memory.
A reset request signal is generated for the PU reset means. However, when the CPU runs out of control, the RO
Unauthorized access to the memory except M is performed to continue writing data, but sometimes write access is performed to the ROM. Therefore, the invention according to claim 2 is
2. The computer according to claim 1, wherein the CP
When U performs a write access to the ROM, it has a ROM write detecting means for detecting the write access.

[0009] In the invention according to claim 2 configured as described above, the ROM write detecting means includes the CP write control unit.
If there is an access from U to the address allocated to the ROM and it is a write access,
A reset request signal is output to the reset means. The CPU reset means, which receives this output, executes a reset operation on the CPU to stop the runaway of the CPU.

[0010] Here, the ROM write detecting means is C
The write access to the ROM of the PU may be detected. Therefore, when the CPU accesses a memory such as a ROM, the CPU may select a memory to be accessed and may be incorporated in a memory controller that controls the CPU and the selected memory, or may communicate with the CPU via a bus. connection,
By directly monitoring signals from the CPU, ROM
May be detected.

By the way, at present, it can be said that all factory facilities and the like are controlled using a computer. In such a factory site, runaway of the CPU may cause a serious problem such as a line stoppage. In an unmanned facility continuously operated by a computer, the CPU
If a reset occurs, the CPU operates normally after the reset.
Although it can be determined that an abnormal situation has occurred, it is difficult to determine whether the cause is a reset of the CPU due to a runaway of the CPU or an abnormality of software logic.

According to a third aspect of the present invention, in the computer according to any one of the first and second aspects, the CPU reset means holds a history of executing a reset operation on the CPU. The configuration includes a CPU reset history unit.

[0013] In the invention according to claim 3 configured as described above, the CPU reset history means includes the C reset history means.
When the PU reset means executes a reset operation on the CPU, a history that the operation has been performed is retained or saved. Here, the CPU reset history means only needs to be able to record the fact that the CPU has been reset. Therefore, the history may be held by a hardware circuit such as a flip-flop circuit, or may be written by writing to a hard disk using software logic.

Further, a recent factory is composed of a large number of equipments and a large number of computers for controlling the equipments, and these computers are connected by a network or the like to constitute one system. Of course, those computers will be scattered over a wide area. In some cases, people may be in places where it is difficult for humans to enter, or they may be away from places where people are usually present. In this situation, the CPU
If a runaway occurs, you must go to the computer to investigate.

According to a fourth aspect of the present invention, in the computer according to any one of the first to third aspects, the CPU reset history means includes an external interface of a predetermined standard, and the CPU reset occurs. This is notified to the outside via the external interface.

In the invention according to claim 4 configured as described above, the CPU reset history means includes the C reset history means.
When the PU reset means performs a reset operation on the CPU, it notifies the external device such as a personal computer via the external interface. Here, the above C
The external interface of the PU reset history means only needs to be connected to a personal computer or the like and can transmit and receive signals and data. Therefore, Ethernet or RS232
C may be used. As a simple configuration, an I / O signal line may be used. Further, it is not necessary to use a wired interface, and a wireless interface may be used.

Here, various modes can be considered for detecting runaway of the CPU. For example, a watchdog timer may be used. Therefore, a fifth aspect of the present invention is the computer according to any one of the first to fourth aspects, further comprising a second CPU reset unit using a watchdog timer.

In the invention according to claim 5 configured as described above, the illegal memory access detection means detects the illegal access of the CPU and watches the runaway of the CPU without the illegal access to the memory. Detected by dog timer. That is, in addition to the phenomenon of the illegal access to the memory when the CPU runs away, there is also a phenomenon that the CPU itself stops its operation and does not access anything outside. In this case, the illegal memory access detecting means does not involve an illegal access, so that the runaway of the CPU cannot be detected. That is, the provision of the second CPU reset means by the watchdog timer makes it possible to detect runaway of the CPU.

Further, the computer according to any one of claims 4 and the external device such as a personal computer connected via an external interface of the computer are not necessarily limited to a single device, but may be integrated systems. It can also be handled as As an example, the invention according to claim 6 includes a computer that notifies the outside that the CPU has been reset via an external interface, and a CPU reset notification that is connected to the computer and notified by the computer. And a computer for detecting that a CPU reset has occurred in the computer.
That is, the computer described in claim 5 and an external device such as a personal computer connected via an external interface of the computer can be regarded as one system.

[0020]

FIG. 1 is a block diagram showing a computer according to an embodiment of the present invention. In the figure, a CPU 1, a ROM 2 connected to the CPU 1 via a bus line 50, a RAM 3 connected to the CPU 1 via a bus line 50, and an EEPROM 4 connected to the CPU 1 via a bus line 50. A gate array 7 connected to the CPU 1 via a bus line 50 and having a stack area overflow register 5 and a stack area overflow register detection circuit 6;
And a CPU reset circuit 10 connected via a signal line 8 and connected to the gate array 7 via a signal line 9.

Here, an address map of each device accessed by the CPU 1 of this embodiment will be described with reference to FIG. In the figure, a ROM area 21 corresponding to the ROM 2 for storing data and a program, a register area 22 corresponding to the stack area overflow detection register 5, a stack RAM area 23 corresponding to the RAM 3 and a data RAM area 24 And the above EEP
An EEPROM area 25 corresponding to the ROM 4 and a register area 26 of the gate array 5 are provided.

When the CPU 1 is operating normally, the CPU 1 stores the stack information in the stack RAM area 2.
In this embodiment, a register area 22 corresponding to the stack area overflow detection register 5 is set immediately after the stack RAM area 23 is exceeded.

Accordingly, the stack area overflow register 5 and the stack area overflow register detection circuit 6 constitute an illegal memory access detection means, and the CPU reset circuit 10 constitutes a CPU reset means.

FIG. 3 is a flowchart showing the contents of the CPU reset request processing performed by the stack area overflow register detection circuit 6. When the CPU 1 accesses a register mounted on the gate array 7, the stack area overflow register detection circuit 6 determines whether or not the address is the address of the stack area overflow register 5. (Steps S100 to S101).

If the address is not the address of the stack area overflow register 5, the process ends. On the other hand, if the access to the stack area overflow register 5 is made, the stack area overflow register detection circuit 6 detects the illegal access of the CPU 1 to the memory (step S102) and at the same time, via the signal line 9. A CPU reset request signal is transmitted to the CPU reset circuit 10 (step S10
3). The CPU reset circuit 10 receives the CPU reset request signal (step S104), and
To the reset signal (step S10).
5). The CPU 1 is reset by the reset signal (step S106).

Next, an operation when the CPU 1 runs out of control and accesses the register area 22 in this embodiment having the above configuration will be described. When the CPU 1 goes into a state of continuously writing the stack information in the RAM while running away, the stack information is written from the upper address to the lower address. Therefore, the writing proceeds from the RAM area 23 to the register area 22.

Here, when the access of the CPU 1 reaches the register area 22 (step S100), the stack area overflow register detection circuit 6
Checks the address of the access (step S1).
01), since this is the address of the register area 22,
A reset request signal is transmitted to the CPU reset circuit 11 (steps S102 to S103). The CPU 1 is reset by the reset request signal (Step S
104 to S106).

FIG. 4 is a block diagram showing a computer according to another embodiment of the present invention. In the figure, the CPU 21, the CPU 21 and the bus line 150 are shown.
A ROM 22 connected to the CPU 2, a RAM 23 connected to the CPU 21 via a bus line 150,
EEPROM 24 connected to bus 1 via bus line 150
, The stack area overflow register 25, the stack area overflow register detection circuit 26 and the RO
Gate array 2 having M write access detection circuit 40
7, and a CPU reset circuit 30 connected to the CPU 21 via a signal line 28 and connected to the gate array 27 via a signal line 29.

FIG. 5 is a flowchart showing the contents of the CPU reset request processing performed by the ROM write access detection circuit 40. The ROM write access detection circuit 40 reads control contents and addresses accessed by the CPU 1 via the bus line 150 (steps S200 to S201). Next, it is determined whether the address in the access is for a ROM (step S202). If the access is to the ROM, it is determined whether the control content of the access is read or write (step S203). If the access is to the ROM area 21, the ROM write access detection and detection circuit 40 detects an unauthorized access of the CPU 1 to the memory (step S204) and at the same time, the CPU reset circuit 30 through the signal line 29. Is transmitted to the CPU (step S
205).

The CPU reset circuit 30 is connected to the CP
Upon receiving the U reset request signal (step S206),
A reset signal is transmitted to the CPU 21 (step S207). The reset signal causes the CPU 21
Is reset (step S208). of course,
In steps S202 and S203, the ROM
If the read access is not the access to the ROM but the access to the ROM, the process ends.

[0031]

As described above, the present invention can detect an abnormality during runaway of a CPU and prevent an abnormal operation of a device controlled by a computer for resetting the CPU. Further, it is possible to provide a computer with a runaway detection function capable of minimizing illegal writing to a memory.

Further, according to the second aspect of the present invention,
Since the write access to the ROM by the CPU can be detected, the contents of the ROM are not destroyed by the runaway of the CPU. Further, according to the invention according to claim 3,
Since the history of resetting the CPU remains as a history, the cause of the abnormal phenomenon can be identified from the history.

Further, according to the invention according to claim 4,
The occurrence of the runaway can be detected from an external device such as a computer connected to the computer in which the CPU has runaway. Furthermore, according to the invention of claim 5, C
It is possible to detect both memory destruction and operation stop due to PU runaway. Further, according to the invention according to claim 6, it is possible to provide a computer system with a runaway detection function capable of detecting runaway of a CPU by an external device connected via a network or the like.

[0034]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a computer with a runaway detection function according to an embodiment of the present invention.

FIG. 2 is a CPU address map of the embodiment.

FIG. 3 is a flowchart illustrating processing performed by a stack area overflow register detection circuit according to the embodiment;

FIG. 4 is a block diagram illustrating a configuration of a computer with a runaway detection function according to another embodiment of the present embodiment.

FIG. 5 is a flowchart illustrating processing performed by a ROM write access detection circuit according to the embodiment;

FIG. 6 is a block diagram showing a configuration of a conventional computer with a runaway detection function.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 RAM 4 EEPROM 5 Stack area overflow register 6 Stack area overflow register access detection circuit 7 Gate array 8 Signal line 9 Signal line 10 CPU reset circuit

Claims (6)

[Claims] 1. A computer comprising a CPU and various memories, wherein the unauthorized memory access detection means detects an unauthorized memory access of the CPU, and the unauthorized memory access detection means is connected to the unauthorized memory access means. CP for inputting a CPU reset request signal output from the access detection means and resetting the CPU
A computer with a runaway detection function, comprising: a U reset unit. 2. The computer according to claim 1, wherein the CPU detects a write access to the ROM of the CPU.
A computer with a runaway detection function, comprising M write access detection means. 3. The computer according to claim 1, wherein said CPU reset means includes a CPU reset history means for retaining a history of executing a reset operation on said CPU. Computer with runaway detection feature. 4. The computer according to claim 1, wherein said CPU reset history means has an external interface of a predetermined standard, and reports that a CPU reset has occurred via said external interface. A computer with a runaway detection function characterized by notification to the outside. 5. The computer according to claim 1, further comprising a second CPU reset unit using a watchdog timer. 6. A computer for notifying that the CPU has been reset to an external device via an external interface,
A computer system having a runaway detection function, comprising: a computer connected to the computer, receiving a CPU reset notification notified by the computer, and detecting that a CPU reset has occurred in the computer.