JPS58141500A - Memory management protecting system - Google Patents

Abstract

PURPOSE:To manage a memory and protect stored data, by managing addresses of instructions to be executed to detect the illegality of address designation and trapping instructions which probably damage the memory. CONSTITUTION:An address control block 3-b constitutes the principal part of an address management block 3 as the center of a memory management protecting mechanism and inhibits the write operation to a memory device in accordance with conditions and performs the address conversion. Operation processings are performed on a basis of an address signal A1 from a processor 1, an operation state signal S1 of the processor (I cycle/E cycle), a read/write signal S2 from the processor 1 to the memory device 2, a mode signal S8 from a mode register 3-a, and a signal from an address management register 3-c, and the control of a memory data read/write signal S3 to the memory device and the transmission of a memory address signal or a prescribed address conversion are performed and control whether an instruction control block 3-d should be operated or not.

Description

Detailed Description of the Invention: Memory management protection that manages memory and protects memory data by managing the address of an instruction to be executed and detecting invalidity in address specification. It is related to the method.

Generally, in general-purpose computers and minicomputers, the system is operated under a so-called operating system (monitoring program), and a memory management protection mechanism within this system plays an important role. When a computer system becomes large-scale and performs repetitive work, it is important to ensure that the data in the storage device is accurate to prevent the spread of hardware malfunctions and failures, programming errors, and program damage. This is because stability and long-term stability are issues and are required. In addition, time-sharing systems (T
SS) Nizo has the problem of destruction and misuse of memory contents by non-users, so a memory management protection mechanism is important. For this reason, various memory management protection schemes have been developed. The memory protection mechanisms of these general-purpose computers are highly sophisticated systems due to their importance, and the system programs and hardware that run them have to be complex and expensive. .

By the way, personal computers have a memory protection mechanism based on cost considerations and the recognition that it is not very important when a small capacity storage device is used personally and for simple work. do not have. However, even in personal computers, as their functions become more advanced and they are applied to complex tasks, a memory management protection mechanism becomes necessary. Is the memory management protection mechanism similar to that used in computers for θ programs and hardware configurations? n
It is complicated and expensive, so please use the key J',
A memory management protection mechanism of a scale and configuration suitable for so-called personal computers is desired. General storage protection in hardware is achieved by a combination of operation and storage area restrictions and permissions. Memory protection through operation restrictions prohibits and prohibits memory write operations, read operations, etc.
By allowing permissions to be set individually, data is protected from destruction and misuse. Furthermore, storage protection by limiting the storage area includes, for example, specifying a specific area of the memory using a register or the like to limit the range that can be accessed.

As shown in Figure 1, two registers are used to manage addresses; one contains the start address of the protected area, and the other contains the final address of the protected area. This method prohibits the use of storage areas.

In order to protect the contents of memory, there is a method of permanently or semi-permanently prohibiting writing to a specific block in the memory area, or a method of controlling memory write operation by setting conditions.
A method that uniformly prohibits or allows read operations cannot control memory management during instruction execution, and although it protects memory, it prohibits all programs from writing data, causing the system to crash. It did not serve as a memory management protection mechanism.

A first object of the present invention is to provide a memory management protection system suitable for small-scale computer systems such as so-called personal computers. A second object of the present invention is to control memory management by executing instructions;
The object of the present invention is to provide a memory management protection method as a memory management mechanism for maintaining the system.

To achieve these objectives, the present invention provides, by means of a particularly simple configuration, the ability to manage the addresses of executed instructions to detect incorrect addressing, thereby reducing the possibility of damaging memory. It is characterized by trapping certain instructions to manage memory and protect memory data.

L;l l-1 An embodiment of the memory management and maintenance system of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram of a Combi-1 Utah system to which the memory management protection method of the present invention is applied. 1 is a processing device, a so-called microprocessor. 2 is a memory device. In a normal system configuration, the processing device 1 and the memory device 2 are generally connected by an address bus Al and a data bus D3 to form a computer system. In a computer system to which the memory management protection method according to the present invention is applied, as shown in FIG.
An address management control block 3 is inserted into an address bus connecting a processing device 1 and a memory device 2. This address management control block 3 is also inserted into the data bus connecting the processing device 1 and the memory device, but it can also be configured so that it is not inserted into the data bus. Address □ Management control block 3 manages addresses generated by the processing device 1 to the memory device 2, and depending on conditions, the processing device 1
The address where the error occurred is sent as is to the memory device 2.

Depending on other conditions, the processing device 1 operates to appropriately convert the generated address and send it to the memory device 2. The address management block 3 has a mode register 3-a.
, address control block 3-b.

Address management register 3-C1 instruction control block 3-d
, and a specific address generation block 3-e. Next, to explain the main signal lines and their signal lines (signals on the plate) in the system block diagram of FIG.
Address signal line to b.

A2 is the memo 1) device 2 from the address control block 3-b.
DI is a data signal from the memory device 2 to the instruction control block 3-d, D2 is a data signal from the instruction control block 3-d to the processing device 1, and D3 is the data signal between the processing device 1 and the memory device. 2 and C9. S
l is a status signal of the processing device 1 and is an instruction fetch cycle (I
A signal 82 indicating the status of the instruction execution cycle (cycle) and the instruction execution cycle (E cycle) is also a status signal of the processing device 1, indicating completion of reading from the memory device 2 (Read) and writing to the memory device (Write).

This is a signal indicating that an operation is being performed. S3 is a signal indicating memory data read/write from the address control block 3-b to the memory device 2, 84 is a mode signal storage control signal '+'l to the Hammode register 3-a, and 85 is a signal from the mode register 3-a. The mode signal 11'V output control signal, 86 is a control signal indicating whether or not to operate the instruction control block, S8 is the mode signal of the mode register 3-a, and 89 is the control signal of the address space from the address management register 3-c. This is a determination and also serves as a detection signal as to whether the set area is a monitoring program area or a user program area.

An outline of the operation of each component constituting the address management block 3 will be described below.

The mode register 3-a holds the program mode signal S8 indicating whether the state of the program to be executed is the monitoring program mode or the user program mode, and is transferred to the mode register 3-a at the end f of the instruction fetch cycle (■ cycle). By the mode signal storage control signal S4,
Store program mode signal S8. The mode signal retrieval control signal S5 retrieves the mode signal S8 stored in the mode register 3-a at the beginning of the ■ cycle and at the beginning of the instruction execution cycle (E cycle) with memory access, and extracts the mode signal S8 stored in the mode register 3-a and addresses the address to determine the program state. It appears in the control block 3-b as a control signal.

The address control block 3-b constitutes the main part of the address management block 3, which is the core of the memory management protection mechanism of the present invention, and prohibits write operations to the memory device and performs address conversion depending on conditions. It is also something that is done. An address signal AI from the processing device 1, an operating state signal Sl (■ cycle/E cycle) of the processing device 1, a read/write signal S2 from the processing device 1 to the memory device 2.
Mode signal S8. from mode register 3-a. It performs arithmetic operations based on the signals from the address management register 3-c, controls the memory data read/write signal S3 to the memory device, and passes the memory address signal or performs predetermined address conversion.

Also, I wonder if I will operate the instruction control block 3-b.)
It also controls C.'C. This operation will be described later according to the flowchart shown in FIG.

The address management register 3-c is used to divide the memory area associated with the address space generated by the processing device and manage the address space according to the management degree. and set the user program area. Management and setting of the address space is performed by setting the address space area using a fixed or semi-fixed switch, FROM, or the like. For example, to determine a certain mid-management address space, set the start address and end address of that address space, and issue a determination signal when an address between them is detected. , Abirev No. 111 may be obtained, and a predetermined address space may be determined based on a coincidence detection signal with the signals of the upper several digit bits of Abirev No. 111.

The platform control block 3-d sends special instructions (for example, input/output processing instructions, stop instructions, etc.) that control instructions executed in the user program area, and instructions that are not defined in the processing device to a predetermined location in the monitoring program area. It can be replaced with a branch instruction to an address.

The specific address generation block 3-e generates the address of an instruction to be executed in the monitoring program after an instruction in the user program area transfers control to an instruction in the monitoring program area. This address is designated by a fixed or semi-fixed switch, PROM, or the like.

Referring to FIG. 4, an overview of the operation of the address management control block 3, which constitutes the main part of the memory management protection system of the present invention, will be explained using a flowchart.

In the present invention, by managing the addresses generated by the processing device 1 when executing an instruction and detecting the invalidity of the address, it is possible to trap instructions that may damage the program and prevent the user program from running out of control or from being manipulated. One mistake, yo.
We try to avoid abnormal conditions in the computer system. In the computer system according to the present invention,
At power-on or initial reset, the mode register 3-a of the program is always set to the monitoring program state SP (31). When the mode register 3-a is set to the supervisory program state SP, as is clear from the flowchart of FIG. is sent to the memory device 2 as is. However, in this case, depending on the status signal of the processing unit's I cycle or E cycle, the command from the memory device is always received in the I cycle of instruction fetch. r, −A inclusion, so the signal S
3 is forcibly placed in a memory reading state (38), and even if the processing device 1 generates a write signal to the memory due to a failure or the like, the memory is protected by not giving it to the memory device. That is, when the mode register 3-a of the program is set to the congested program state mode, in the cycle (2), 32.33°35, 38.
40.42.44.32.33.35・・・・・・・・・
Repeat the loop of... Also, moving to the E cycle, 32, 49.53.54.44.32.49.53.
Repeat the loop of ・・・・・・・・・・・・. At this time, the address is not checked for invalidity. When the contents of the mode register 3-a of the program are changed to the user program state UP mode setting by an instruction in the monitoring program, the address invalidity check routine 34. or 51, address management is performed. Mode register 3-a is in user program state UP
If the mode is set to , the address is managed in cycle (2) and the contents of the fetched instruction are also checked (45). That is, the instruction control block 3-d is operated to check whether the instruction taken out from the memory in the instruction fetch cycle is a specific instruction or a specific instruction. Inappropriate address settings and command settings in the user program are handled by this address management routine 3415.
1. It is checked by the instruction check routine 45, and any write instruction to the memory device that may cause an abnormal state of the computer system due to a runaway of the user program or an operational error is trapped and invalidated. Furthermore, in the E cycle of instruction execution in the user program mode, the address is managed, and if the address is not appropriate, the memory is read to the memory device 2.
7' The write signal S3 is forced to become a read signal, and careless memory writing causes the memory contents to become tllr.
, so as not to damage it. In addition to protecting memory by managing these addresses, it also manages invalid instruction codes in the program to prevent execution of supporting commands that may destroy memory contents (this routine In the flowchart of FIG. 4, this is indicated by 44, 45, 46, 47, 48, and in FIG. If the control block 3 is not inserted between the data buses D3 but is inserted only into the address bus, the routine for managing the invalidity of this instruction code can be omitted.

It turns out. This function can be sufficiently realized only by memory protection through address management.

The general operation of the address management control block 3 has been described above, and the advantages and effects of the memory management protection system according to the present invention are listed as follows.

lal If the size of the monitoring program is fixed, if the area setting of the monitoring program area in the memory area is fixedly connected, the address line can be used as is, and the software configuration can be simplified. In addition, in cases where the size of the monitoring program changes, it is recommended to set the area of the monitoring program area/user program area using an external switch or programmatically. Hey.

(By setting the instruction code to be trapped in the instruction control block appropriately, you can avoid executing the instruction code that is too complicated for the processing device.

(C1 The conventional memory management program within the operating system (monitoring program) has been changed to a node-like configuration in the present invention. Reduced.

(By diversifying the memory area settings and program status mode settings, multiple program modes can be set, and each program can be managed independently by combining the area and program status setting modes.)

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of storage protection by limiting the accessible storage area, Fig. 2 is a block diagram of a general computer system to which the present invention is applied, and Fig. 3 is a memory management protection method according to the present invention. FIG. 4 is a block diagram of a computer system to which the present invention is applied. FIG. 4 is a schematic flowchart illustrating the operation of the memory control block which is the main part of the present invention. 1: Processing device 2: Memory device 3 Near address management control block: 3-a: Monitoring program mode/user program mode setting mode register 3b = Address control block 3-C Near address management register; 3d: Instruction control block 3-e : Specific address generation block A1: Address signal from the processing device to the address management control block A2 Address signal from the near address management control block to the memory device D1: Data signal from the memory device to the instruction control block D2: Processing from the instruction control block Data signal D3 to the device: Data signal line Sl between the processing device and memory device: Status signal of the processing device;
Signal indicating E cycle S2: Signal that controls memory read/write from the processing device S3 Signal that controls memory read/write from the near address management control block S4: Mode signal Storage control signal S5: Mode signal retrieval control signal S6: Enable that controls the operation of the instruction control block
/]) enable signal S8 Niprogram mode status signal S9 Near address space determination/setting area detection signal '9J1
Diagram 2

Claims (1)

[Scope of Claims] (11) A memory area associated with an address space generated by a processing device is divided into a plurality of areas, and the address space corresponding to the divided area is defined as a management unit. There is an address management register that is set in the user program area, a mode register that stores the mode state of the program to be executed, and a processing unit that generates data according to the contents of this address management register and mode register. control means for managing and controlling the address of the instruction to be executed, and controlling the address of the instruction to be executed to trap and invalidate the IJ write instruction to the supervisory program area or other user program area of the instruction in the user mode. (2) The control means for managing and controlling the addresses generated by the processing device according to the contents of the address management register and the mode register is means for generating a specific address and converting the address. It manages the address of the instruction to be executed, and converts the address of the instruction to be executed when a memory write instruction to the instruction monitoring program area or other user program area in user mode is trapped. The memory management protection method according to claim (1). (3) A memory area associated with an address space generated by a processing device is divided into a plurality of areas, and the divided area is An address management register that sets the address space of a management unit to a monitoring program area and multiple user program areas, with the corresponding address space as a management degree, a mode register that stores the mode state of the program to be executed, and this address management register and It is equipped with a control means for managing and controlling the addresses generated by the processing unit according to the contents of the mode register, and an instruction control means for replacing an instruction with a branch instruction to a specific address in the supervisory program area, and controlling the address of the instruction to be executed. 1. A memory management protection method, which traps a memory write instruction to a supervisory program area or another user program area by an instruction in a user mode, and replaces it with a branch instruction to a specific address in the supervisory program area.