JPS6232544A - Abnormally detecting circuit for information processor - Google Patents

Abstract

PURPOSE:To detect immediately an abnormality generated in not only a random access memory but also a read-only memory, and to check the generation of a wrong alarm, and a malfunction as well by controlling an output of two kinds of abnormality signals to the outside, until a prescribed time elapses after a central processor is reset. CONSTITUTION:When an abnormality is generated in a RAM 12 and a.ROM 11, and when a data write access to the ROM 11 is executed by a CPU 10, a memory parity checking circuit 15 and an illegal write detecting circuit 17 provide an output to an OR circuit 22. Both of these two kinds of signals are applied to one input terminal of an AND circuit 23. As for these two kinds of abnormality signals, an output to its outside is controlled by a gate circuit 20 until a prescribed time elapses after the logical level of a reset signal 10b becomes '1' instantaneously, while a logical level of a signal is outputted from a one shot timer 18 given to the other input terminal of the AND circuit 23 and is inverted through an inverter circuit 19, namely, when the CPU 10 is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an abnormality detection circuit for an information processing device.

[Conventional technology]

FIG. 2 is a block diagram showing an example of the configuration of an abnormality detection circuit of a conventional information processing apparatus published in Japanese Utility Model Application Publication No. 59-174642.

In FIG. 2, 1 is a computer main body, and 10 is a central processing unit (hereinafter referred to as rCPUJ) of the computer main body 1.
, 11 is a read-only memory (hereinafter referred to as rROMJ)
, 12 is a random access memory (hereinafter referred to as rRAMJ), 13 is a memory parity generation circuit, 14 is a parity bit memory RAM, 15 is a memory parity check circuit, and 17 is a 110 port.
They are each connected to a bus 16 extending from 10.

Next, the operation of the abnormality detection circuit of the information processing apparatus configured as described above will be explained.

The CPU 10 executes a program stored in the ROM 11, and according to the program, the RAM 2
Writing calculation data to or reading calculation data from the RAM 12 is performed. The CPU 10
When writing all the operation data to AM[2, the memory parity generation circuit 13 calculates the parity of the write data, and the result of the calculation is written into the parity bit RAM 14 by the memory parity generation circuit 13. . When the CPU 10 reads operation data from the RAM 12, the memory parity check circuit 15 calculates the parity of the read data, and the memory parity check circuit 15 stores the result of the calculation and the harness bit RAM 14. data (parity value) is compared. If it is determined that the two match as a result of the comparison, the memory parity check circuit 15 outputs a signal instructing the CPU 10 to continue executing the process.

If it is determined that the two do not match as a result of the comparison, the RAM abnormality signal 15m is activated by the memory parity check circuit 15 to alert the outside that an abnormality has occurred in the RAM 12, and the memory parity check circuit 15 activates the RAM abnormality signal 15m. 15 outputs a signal instructing the CPU 10 to interrupt the execution of processing.On the other hand, abnormality diagnosis of the ROM 11 is performed by a so-called sum check. That is, the value obtained by adding all the data contents of the ROM 11 word by word is stored in CPtJlo in advance, and the value obtained by the addition of the data of the ROM 11 performed by the CPU 10 using the free time of program execution and the value obtained by the addition are stored in CPtJlo in advance. This is a method in which the CPUI Q itself checks whether the added value is equal to the previously stored added value. As a result of the sum check, if an abnormality is detected in the ROM11, the I10 port 17
The POM abnormal signal 17a to be output from the CPU 10
The software that defines the processing operation of the CP sets the logic level to ``1'' and alerts the outside.
The processing execution of U10 also stops being interrupted.

[Problem that the invention seeks to solve]

The abnormality detection circuit of a conventional information processing device is configured as described above. 9. Since the abnormality diagnosis of the ROM 11 is performed by the so-called sum check described above, free time outside the time normally spent on program execution is saved. Until it comes, ROM1
It was not possible to fully check whether an abnormality had occurred in 1. Therefore, even if a ROMI IK abnormality occurs, the abnormality cannot be detected immediately.Furthermore, since the abnormality detection was performed by software that specified the processing operation of the cPU 10, the software was complicated. There was a problem. In addition, even if a situation occurs in which a false alarm is issued when an abnormality actually occurs or the CPU 10 malfunctions, it is impossible to check these situations [1].

This invention was devised to solve the above-mentioned problems, and is capable of immediately detecting not only abnormalities occurring in the RAM but also abnormalities occurring in the ROM, as well as preventing the occurrence of false alarms and malfunctions of the CPU. It is an object of the present invention to obtain an abnormality detection circuit for an information processing device that can also check.

[Means for solving problems]

The abnormality detection circuit of the information processing device according to the present invention calculates the parity of data when the central processing unit writes the data to the read-only memory or the random access memory, and outputs the calculated value data by the parity calculation means. death,
The calculation value data output from the parity calculation means is stored in the parity calculation value data storage means, and when the central processing unit reads out the data stored in the read-only memory and the random access memory, respectively, the data is While calculating a parity value, the calculated value is compared with the parity calculation value data stored in the parity calculation value data storage means, and when the two do not match, a memory abnormality signal is outputted by the abnormality detection means, When it is detected that a data write access has occurred from the central processing unit to the read-only memory, an unauthorized write error signal is output by the unauthorized write detection means, and a certain period of time after the central processing unit is reset. The output of the abnormality signal from the memory abnormality detection means and the output of the abnormality signal from the unauthorized write detection means are regulated by the abnormality signal regulation means until a good result occurs.

[Effect]

The abnormality detection means in this invention calculates the parity value of the data when the central processing unit reads the data stored in the read-only memory and the random access memory, respectively, and stores the calculated value and the parity calculation value data. The unauthorized write detection means compares the parity calculation value data stored in the means and outputs a memory abnormality signal when the two do not match, and the unauthorized write detection means receives data write access from the central processing unit to the read-only memory. When it detects that this has occurred, it outputs an unauthorized write error signal,
The abnormal signal regulating means regulates the output of the abnormal signal from the memory abnormality detection means and the output of the abnormal signal from the unauthorized write detection means for a certain period of time after the central processing unit is reset until the central processing unit is reset. It is.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an abnormality detection circuit of an information processing apparatus according to an embodiment of the present invention.

Note that the reference numerals 1.10 to 16 in FIG. 1 are exactly the same as those shown in FIG. 2 described above, so their explanation will be omitted.

In FIG. 1, 17 is an unauthorized write detection means, that is, an unauthorized write detection circuit, 18 is a one-shot timer forming a part of the above-mentioned abnormal signal regulation means, and 19 is a part of the above-mentioned abnormal signal regulation means. Inverter circuit 20
is a gate circuit constituting a part of the above-mentioned abnormal signal regulation means.The memory parity generation circuit 13 functions as the parity calculation means, and the parity bit memory functions as the parity calculation value data storage means. For R
In the AM 14, the memory parity check circuit 15 has a function as a memory abnormality detection means.

The unauthorized write detection circuit 1T is connected to the aforementioned bus 16 and is also connected to the input side of the gate circuit 20. The unauthorized write detection circuit 17 sets the unauthorized write occurrence signal 17b to a logic level @1# when the CPU 10 executes data write access to the ROM 11.
shall be. The one-shot timer 18 has its input side connected to the reset signal output terminal of the CPU 10, and its output side connected to the input terminal of the inverter circuit 19. The one-shot timer 18 is
The inverter circuit 19 is configured to continuously output a signal at the logic level "1" for a predetermined period of time due to the reset signal 10b outputted from the inverter circuit 10 instantly becoming the logic level "12". Its output terminal is connected to the input side of the gate circuit 20 described above, and the logic level of the signal output from the one-shot timer 18 is inverted and outputted to the gate circuit 20.Gate circuit 20 is composed of an OR circuit 22 and an AND circuit 23.The OR circuit 22 combines the output signal 15b from the memory parity check circuit 15 and the output signal 17b from the unauthorized write detection circuit 1T. The logical product circuit 23 calculates the logical product of the output signal from the one-shot timer 18 whose logic level has been inverted by the inverter circuit 19 and the output signal from the logical sum circuit 22. Output to outside.

The gate circuit 20 determines whether the operation of the CPU 10 is normal or abnormal in the following manner. ■After the parity pit of ROM11 is set, the ROM11
If no data write operation is performed on the CPU
10 is determined to be operating normally and the logic level @1"
does not output the signal.

■After the output of the one-shot timer 18 reaches logic level 10# (that is, after several seconds, which is the time required to set the parity value of the ROM 11), the unauthorized write is output from the unauthorized write detection circuit 1T. When the logic level of the signal 15b indicating that the process has been performed becomes "BI", the CPU 10 determines that it is in an abnormal state and outputs a signal of logic level "1" to the outside.

Note that the reset signal 10 output from the CPU 10
b is set to the logic level 11# instantly after the CPU 10 is reset.

Next, the operation of the abnormality detection circuit of the information processing apparatus configured as described above will be explained below.

When the CPU 10 writes data to the RAM 12 or ROM 11, the memory parity generation circuit 13
calculates the parity of the write data and writes the calculation result to the parity bit memory RAM 14. On the other hand, when the CPU 10 reads data stored in the ROM 11 or the RAMI 2, the memory parity check circuit 15 calculates the parity value of the read data and stores it in the parity bit memory RAM 141C. The parity value is read out and compared with the calculated parity value.

If it is determined that the two do not match as a result of the comparison, R
The logic level of the memory abnormality signal 15b output to the OR circuit 22 is set to 1'' in order to warn the outside that an abnormality has occurred in the AM12 and ROM11.When the CPU 10 executes data write access to the ROM11, , the illegal write detection circuit 17 sets the logic level of the illegal write occurrence signal 17b output to the OR circuit 22 to 11''.

Both of the above two types of signals are applied to one input terminal of the AND circuit 23. However, both of the above two kinds of abnormal signals are outputted from the one-shot timer 18 applied to the other input terminal of the AND circuit 23 and inverted via the inverter circuit 19, and the logic level of the signal becomes "O". In other words, when the CPU 10 is reset, the logic level of the reset signal 10b changes instantly.
The output to the outside is regulated by the gate circuit 20 until a predetermined time has elapsed after the signal becomes 1''.

The reason why the 2m abnormal signal is prevented from being output to the outside as long as the logic level of the output signal from the inverter circuit 19 is "1" is as follows.

That is, as soon as CPolo is reset and the reset signal 10b instantly becomes the logic level g"1", the unauthorized write generation signal 17b is reset), and the data stored in the ROM 11 is reset to 1 for the entire memory space of the ROM 11. 1 when the CPU 10 is performing operations such as reading each word and rewriting the read data.
In parallel with this, the memory parity generation circuit 13 outputs the ROM 1 to the parity bit memory RAM 14.
This is to prevent a false alarm from being output from the gate circuit 20 during the writing operation of the parity bit of 1. After CPol 0 is reset, a predetermined period of time elapses and one-shot timer 1
8 becomes logic level "02," the illegal write occurrence signal 1Tb and the memory abnormality signal 15b are output from the gate circuit 2.
Since it will be output without being regulated by 0, R
As soon as an abnormality is detected in the operation of the OM 11, RAM 12, or CPU 10, the logic level of the signal output from the gate circuit 20 becomes "1#". When the signal becomes "l", the signal is used as an alarm output to the outside or as a processing execution interrupt command signal to the CPU 10.

Note that the delay time of the one-shot timer 1B mentioned above is set to be the same as the time for the CPU 10 to set the parity bit of the ROM 11, or slightly longer, in order to completely prevent a false alarm from being output when the parity bit is set. By setting the delay time in this way, it is possible to reliably detect abnormalities and unauthorized writing in the ROM 11 during normal processing operations.

In the embodiment according to the present invention described above, a memory parity check circuit is provided as a memory check circuit, but an EC is used instead of the memory parity check circuit.
There is no problem even if the C circuit is used.

〔Effect of the invention〕

As described above, according to the present invention, when the parity calculation value of data read from the read-only memory or random access memory and the parity calculation value data stored in the parity calculation value data storage means do not match, the parity calculation value data stored in the parity calculation value data storage means is stored in the memory. An abnormality signal is output, and when it is detected that a data write access has occurred from the central processing unit to the read-only memory, an unauthorized write abnormality signal is output, and the output of these two types of abnormality signals to the outside is controlled by the central processing unit. Since we decided to restrict the amount until a certain period of time has passed after the processing device is reset, it is possible to immediately detect abnormalities that occur not only in random access memory but also in read-only memory, and to prevent the occurrence of false alarms. This has the effect of providing an abnormality detection circuit for an information processing device that can also check for malfunctions in the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration of an abnormality detection circuit of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of an abnormality detection circuit of a conventional information processing apparatus F. In the figure, 1 is a central processing unit, 10 is a CPU, 11 is a ROM, 12 digits of RAM, 13 is a memory parity generation circuit, 14 is a parity bit memory control, 15 is a memory parity check circuit, 16 is a bus, and 17 is an invalid A write detection circuit, 18 is a one-shot timer, 19 is an inverter circuit, 20 is a gate circuit, 22 is an OR circuit, and 23 is an AND circuit. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A parity calculation means for calculating the parity of the data when the central processing unit writes the data into the read-only memory or the random access memory and outputting the calculation value data, and the calculation value data output from the parity calculation means. a parity calculation value data storage means for storing a parity calculation value; memory abnormality detection means for comparing the parity calculation value data stored in the parity calculation value data storage means and outputting a memory abnormality signal when the two do not match; and the central processing unit for the read-only memory. unauthorized write detection means for outputting an unauthorized write abnormality signal when detecting that a data write access has occurred from the memory abnormality detection means for a period of time until a certain period of time has elapsed after the central processing unit was reset; An abnormality detection circuit for an information processing apparatus, comprising an abnormality signal regulating means for regulating the output of an abnormal signal from the unauthorized writing detector and an abnormality signal regulating means for regulating the output of the abnormal signal from the unauthorized writing detecting means.