JPH0797335B2 - Computer runaway detection device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an improvement of a runaway detection device for detecting abnormal operation of a computer.

[Conventional technology]

As shown in FIG. 3, the basic configuration of a device using a microcomputer is such that a ROM (read only) is output to an address bus 2 and a data bus 3 output from a central processing unit 1 (hereinafter referred to as CPU). ·memory)
4 and a RAM (random access memory) 5 are connected, the CPU 1 reads out program data stored in the ROM 4 or the RAM 5, and necessary processing is performed based on the data.

By the way, in the above-described device using the microcomputer, it is often found that the CPU 1 performs an abnormal operation due to external noise, defective programs, or the like. This is usually read as a runaway CPU1.

Conventionally, various detection methods have been developed for detecting such a CPU runaway. Among them, the watchdog timer (WD
The method using T) is often used. This is the form to access as illustrated Lee area is within a predetermined time T ₁ at pre-programmed as shown in FIG. 4, a predetermined time T ₁
This is a method of determining that the CPU 1 is out of control when there is no access even after the time T ₂ (T ₁ <T ₂ ) is exceeded, for example.

[Problems to be solved by the invention]

However, when using the above runaway detection method, CPU1
There is a problem that abnormalities of can not be detected quickly. That is, when the watchdog timer (WDT) is used, the abnormality can be detected only after the minimum time T ₂ despite the abnormality of the CPU 1. Therefore, during this period, there is a risk that the program data and the like will be damaged due to the abnormality of the CPU 1, and a serious accident will occur in other devices controlled by the CPU 1 and the controlled object. Therefore, it is necessary to detect the runaway of the CPU 1 promptly, and for this reason, it is conceivable to reduce the time T ₁ , for example, but in this case, the processing time of the program becomes short as shown in Fig. 4B, Problems arise that reduce the processing capacity. On the other hand, it is conceivable to make the time T ₂ closer to the time T ₁ , but there is a risk that it may be judged to be abnormal although it is normal due to a slight delay in timing, and it is extremely reliable as a computer-using device. Inevitably it will be low.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a computer runaway detection device capable of quickly detecting a runaway of a CPU and suppressing its adverse effects to a minimum and promptly returning to normal operation. To do.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention latches the program data with a data latch means at the timing when the CPU reads the program data, and the fixed data which is written in a portion other than the program area in the data storage unit in advance. Fixed data that is read when the area other than the program area is read is stored, the data in the data storage unit is compared with the data latched by the data latch means, and when the number of coincidence reaches a predetermined number, the CP
An interrupt signal indicating that there is an abnormality is sent to U.

[Action]

Therefore, by using the above means, when the data latched by the latch means and the fixed data match a predetermined number of times consecutively due to the abnormality of the CPU, the CPU runs out to detect that it is abnormal. Can be quickly detected, the adverse effect can be minimized, and normal operation can be restored.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. In the figure, an address bus 12 and a data bus 13 are derived from the CPU 11, and a ROM 14 is provided on these buses 12 and 13.
And RAM15 is connected. These ROM14 and RA
Program data is stored in one or both of the M15s by occupying at least a partial area.

Reference numeral 16 is a data latch means for latching program data, which is a timing signal M for reading out a command fetch cycle signal from the CPU 11, that is, program data.
And a data latch circuit 18 for latching the program data K on the data bus 13,
The latch circuit 18 receives the timing signal M input from the CPU 11 through the signal line 17 and latches the program data K on the data bus 13. Reference numeral 19 denotes a fixed data storage unit, which stores fixed data to be stored in an address other than the normal access of the ROM 14 or the RAM 15 of the CPU 11, that is, an area other than the program data area. The reason is that, for example, a CPU having a prefetching function for the corresponding command word and other CPUs may read an area other than the program data area when the CPU is abnormal. Therefore, the data stored in the fixed data storage unit 19 is data that the CPU 11 does not read as an instruction word several times in succession during normal operation, and is written in an area other than the program data area or other than the program data area. The data read when is read is used. Reference numeral 20 is a comparison unit that compares the latched data of the latch circuit 18 latched by the program data output timing signal M with the fixed data of the fixed data storage unit 19, and outputs a coincidence signal S when they coincide. 21 is the comparison section
The coincidence signal S2 output from 20 is counted by the timing signal M, and when the predetermined number of times is reached, it is determined that the operation is an abnormal operation, that is, a runaway due to external noise or program failure, and the interrupt signal I is sent to the CPU 11. This is a counting unit for sending.
That is, the CPU 11 reads the no-program area, but this is not necessarily an abnormality, but since there is a possibility that the CPU 11 may continuously read the no-program area every time when some abnormality occurs in the CPU 11, the counting section 21 is predetermined. The value of is set.

Next, regarding the operation of the apparatus configured as described above,
It will be described with reference to the drawings. CPU11 specifies address and ROM
When the program data is read out from the RAM 14 or the RAM 15 and sent out to the data bus 13, the program data read timing signal M is inputted to the latch circuit 18 and the counting section 21, whereby the latch circuit 18 outputs the program data K on the data bus 13. To latch. And this latch circuit
The latch data K of 18 is sent to the comparison unit 20. Here, the comparison unit 20 is a latch circuit 18 latched by the timing signal M.
Of the latch data K and the fixed data in the fixed data storage unit 19 are compared, and when the result of the comparison indicates that they match, a match signal S is output. The coincidence signal S is counted by the counter 21, and when the coincidence signal S is counted a predetermined number of times each time the timing signal M is input, the counter 21 outputs an interrupt signal I.
It is sent to COPU11. This interrupt signal I normally enters the CPU 11 as an emergency interrupt, but here the CPU 11 causes the program to jump to a routine for abnormal processing. The cross mark of the latch data K shown in FIG. 2 indicates that the latch data K and the fixed data match.

Therefore, according to the configuration of the above embodiment, the program data on the data bus 13 is latched at the timing of sending the program data, and the latched data is compared with the fixed data in the area other than the program area, and the coincidence is found. Since the interrupt signal I is sent to the CPU 11 when it reaches the predetermined number of times in succession, when the CPU 11 runs out of control due to some trouble during program execution, it immediately detects if an instruction other than the program area is fetched. Is possible. Therefore, the occurrence of an abnormality can be detected quickly, the processing after the occurrence of the abnormality can be performed quickly and accurately, and the influence on other devices and control targets can be suppressed to a minimum. Further, since the runaway is detected by using the read timing signal of the program data and the data comparing means which is usually used in general, it can be realized with a very simple configuration. In addition, when operating the CPU 11 using ROM data, for example, if the fixed data is set to FF consisting of 16 "1" ... "1", the data of ROM14 before writing is "FF". Therefore, it is easy to create fixed data, and runaway ROM14
It is very effective when you want to read out other than the program data write area.

It should be noted that the above-described embodiment can be applied to all computer utilizing devices that read and execute command words from the memory. In addition, the present invention can be modified in various ways without departing from the scope of the invention.

〔The invention's effect〕

As described above in detail, according to the present invention, a computer that can detect an abnormality immediately when the CPU has run out of operation and some abnormalities occur during program execution, and can restore the normal operation by suppressing the adverse effects to a minimum. Can provide a runaway detection device.

[Brief description of drawings]

FIG. 1 and FIG. 2 are shown for explaining one embodiment of the present invention. FIG. 1 is a configuration diagram of main parts, and FIG. 2 is an operation timing chart for explaining the operation of the device of the present invention. FIG. 3 is a schematic configuration diagram of a conventional general computer utilizing apparatus, and FIG. 4 is an operation timing chart of a system using a watchdog timer. 11 …… CPU, 13 …… Data bus, 14 …… ROM, 15 …… RA
M, 16 ...... Data latch means, 18 …… Latch circuit, 19 ・ ・ ・
… Fixed data storage, 20 …… Comparison, 21 …… Counter.

Claims (1)

[Claims] 1. A computer utilizing device for executing a program command based on program data read from a memory by a CPU, wherein data latch means for latching data sent to a data bus using a read timing signal for the program data. A fixed data storage unit for storing fixed data written in an area other than the program data area in advance or fixed data read when an area other than the program data area is read; data in the fixed data storage unit; A runaway detecting device for a computer, comprising: runaway detecting means for comparing the data latched by the latch means and sending an interrupt signal to the computer when the number of coincidences reaches a predetermined number.