JPH01228055A - Multi-processor system - Google Patents

Abstract

PURPOSE:To efficiently execute an error processing by storing by the cycle of which processor a memory error occurs and executing an error generation information to a processor to generate an error. CONSTITUTION:Plural processors 1A and 1B are connected through a bus BS to a memory 2. When an error occurs at the memory 2, it is detected by a memory error detecting means 3 and sent to an error signal informing means 4. The error signal informing means 4 stores by the access cycle of which processor the memory error occurs, and at the time of the access cycle of the said processor, the stored error signal is informed to the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multiprocessor system comprising a plurality of processors and a shared memory commonly accessed by the plurality of processors. The present invention relates to a multiprocessor system in which, when a memory error signal occurs, the processor that causes the error can be reliably notified of the memory error signal.

(Prior Art) A computer system having a memory device uses, for example, a parity check to detect errors to determine whether memory access has been performed normally.

FIG. 4 is a conceptual diagram showing an example of a computer system having an error detection circuit.

Processor 1 and memory 2 are connected via data bus DB, and when error detection circuit 3 detects an error when accessing memory 2, it notifies processor 1 of an error detection signal.

Here, error detection by the error detection circuit 3 requires a certain amount of time, and if the processor 1 were to wait for an error notification signal, there is a problem that the access time to the memory 1 would be extended.

For this reason, it is conceivable to notify the occurrence of an error (this error notification signal uses an interrupt or a special signal indicating an access abnormality) in the next access cycle. This method is effective in that it does not require sacrificing normal operating speed due to rare errors.

(Problem to be solved by the invention) However, in a system in which multiple processors are connected to the data bus DB and the memory 2 is shared, the cycle in which a memory error occurs and the cycle in which the memory error is notified coincide with each other. A problem arises in that the error signal is sent to another processor instead.

FIG. 5 is a time chart showing the above-mentioned operation in the case of a system using two processors IA and IB.

The present invention has been made in view of these problems.The purpose of the present invention is to store in which processor cycle a memory error occurs in a multiprocessor system, and to notify the actual error occurrence. The object of the present invention is to realize a system that can access the processor that was executing the access in the cycle in which the error occurred.

(Means for Solving the Problems) FIG. 1 is a block diagram showing the basic configuration of the present invention. In FIG. 0, IA and IB represent a plurality of processors,
2 is a shared memory commonly accessed by these plurality of processors IA and IB; 3 is a memory error detection means for detecting a memory error in the shared memory 2;

4 holds which processor among the plurality of processors IA and IB was accessing the memory when the memory error detection means 3 detected a memory error;
This is an error signal notification means for notifying a memory error signal to a corresponding processor at the time when the processor accesses the memory.

(Function) When the memory error detection means 3 detects a memory error,
The error signal notification means 4 stores in which processor access cycle the memory error occurred,
At the time of the access cycle of the relevant processor, the stored error signal is notified to that processor.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 0 illustrating a system in which two processors IA and IB share one memory 2, 5 is a memory access right control circuit that controls the memory access rights of the two processors IA and IB so that they do not conflict with each other.

In the error signal notifying means 4, 41a and 41b are gates to which the memory error signal MER from the error detecting means 3 and the signal BCY indicating the bus cycle are respectively input. The gate 41b receives a signal Aacs indicating that the processor IB has access rights, and a signal Bacs indicating that the processor IB has access rights. 42a is gate 41
Holding means for holding the signal from a, 42b is the gate 41
A holding means for holding the signal from b, for example, a flip-flop is used.

43a and 43b are gates, and one gate 43a receives a signal from the holding means 42a, a bus cycle signal BCY, and a signal Aacs indicating that the processor IA has obtained access rights.

Further, the other gate 43b receives a signal from the holding means 42b, a bus cycle signal BCY, and a signal Bacs indicating that the processor IB has obtained access rights. 44 is an OR gate which inputs the signals from the gates 43a and 43b and sends its output signal as a memory error notification signal to each processor IA and IB.

The operation of the apparatus configured in this way will be explained next.

FIG. 3 is a time chart showing an example of the operation.

The memory access right control circuit 5 includes two processors IA
, IB, and outputs access permission signals Aacs and BacS as shown in (a) and (b) to processor IA and processor IB, respectively, to prevent access conflicts. Each processor I
According to this access permission signal, A and IB access the shared memory 2 in the bus cycle shown in (c).The memory error detection means 3 performs, for example, a parity check on the data read from the memory 2. conduct,
Determine whether there is an error.

Here, for example, if a memory error is detected when the processor IA accesses the memory, the memory error signal MER is outputted at the timing shown in (d).

In the error signal notification means 4, the memory error signal MER from the memory error detection means 3 passes through the gate h41a and is held in the holding means 42a as shown in (e). Note that at this time, the gate 41b receives the access permission signal Bac.
s is low level and closed.

The memory error signal held in the holding means 42a is sent to (to) the next time the processor IA accesses the memory.
As shown in FIG. 4, the signal passes through the gate 43a and the OR gate 44 and is output to the processor IA as a memory error notification signal.

The processor IA receives this memory error notification signal, recognizes that a memory error occurred the last time it accessed the memory, and takes appropriate action against the error, such as retrying. .

Although the above description has been given of the case where a memory error occurs when the processor IA accesses the memory, the operation is the same even when a memory error occurs when the processor IB accesses the memory.

(Effects of the Invention) As described above in detail, according to the present invention, in a system including a plurality of processors, when a memory access error occurs without sacrificing the operating speed of each processor, , it is possible to appropriately notify the relevant processor of a memory error, and it is possible to effectively process the error.

[Brief explanation of the drawing]

Fig. 1 is a basic configuration block diagram of the present invention, Fig. 2 is a configuration block diagram showing an embodiment of the invention, Fig. 3 is a time chart showing an example of its operation, and Fig. 4 is an error detection FIG. 5 is a conceptual configuration diagram showing an example of a computer system having a circuit. FIG. 5 is a time chart showing the operation when the system in FIG. 4 is configured using two processors. IA, IB...Processor 2...Memory 3...Memory error detection means 4...Error signal notification means 5...Memory access right control means Town tnt Figure 4 Figure 5

Claims (1)

[Scope of Claim] A system comprising a plurality of processors and a shared memory commonly accessed by the plurality of processors, comprising: means for detecting a memory error in the shared memory; and the memory error detecting means detecting a memory error. and an error signal notification means for retaining which processor among the plurality of processors is accessing the memory when the memory is detected, and for notifying a memory error signal at the time when the processor accesses the memory. multiprocessor system.