JPS6057439A - Stack overflow detector - Google Patents

Abstract

PURPOSE:To detect a stack overflow by providing a function to identify the writing to a data area from the writing in a stack area. CONSTITUTION:An upper limit comparator 22 compares the value A delivered to an address bus 12 with the value Au of an upper limit register 20 while a signal is delivered to a stack operation detecting signal line 25. Then an overflow signal 1 is delivered when A>Au is satisfied. While a lower limit comparator 23 compares the value A delivered to the bus 12 with the value Al of a lower limit register 21 and delivers an underflow signal 1 with A<Al. Therefore, 1 is delivered to a stack overflow detecting signal line 30 from an OR gate 26 when A>Au or A<Al is satisfied with the value A of a subject address of a stack operation instruction. Thus a stack overflow can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a stack overflow detection device in a computer system using a microprocessor or the like.

Conventional configurations and their problems With the rapid development of microprocessors in recent years, it has become possible to construct computer systems at low cost.

A feature of microprocessor-based products is that they use software to perform functions that were conventionally achieved using hardware. Even if the hardware is the same, if you change the installed software, the product will look like a different product. It is possible to do so. Therefore, it is necessary to develop appropriate software as well as appropriate hardware, and various software development soles have been developed.

The concept of stack is one of the architectural features of microprocessors, and is used to temporarily save and restore internal registers, and to store the return address to the main program when branching to a subprogram. It has the feature that data can be read and written regardless of the address within.

This stack area is physically limited, and a stack pointer is provided in the arithmetic processing unit, which manages addresses for reading and writing from and to the storage device.

However, programs that are in the middle of development are prone to problems such as program runaways due to storing more data than the size of the stack area or retrieving more data than the stored data. It is difficult to pursue this, and a stack overflow detection device has become necessary.

Here, the usage pattern of a storage device is generally shown in FIG. 1. 1 is a program area, 2 is a data area, 3 is a stack area, and 4 is a free area. Program area 1 is typically read-only, data area 2. The stack area 3 can be both read and written.

Storing data in program area 1 or free area 4.

and data area 2. Reading an instruction from the stack area 3° free area 4 is an abnormal process.

By using a signal line that indicates whether the arithmetic processing unit is in an instruction read cycle or an instruction execution cycle,
Data area 2. It is possible to detect an access to the stack area 3 and the free area 4, and similarly, it is possible to detect the storage of data to the program area 1 in an instruction execution cycle.

However, since reading and writing to data area 2 and reading and writing to stack area 3 cannot be distinguished from the outside,
It was not possible to prevent the data in the data area 2 from being destroyed due to stack overflow, and a lot of effort was spent searching for the cause of the abnormal operation.

Furthermore, if the storage device usage pattern is as shown in Figure 2, there is a problem in that it is not possible to prevent the extraction of invalid data or the return of a program to an invalid address due to stack underflow. Ta.

Purpose of the Invention The present invention solves the above-mentioned conventional problems, and provides a stack overflow detection device that can detect stack overflow by providing a function to distinguish between reading and writing to a data area and reading and writing to a stack area. With the goal.

Structure of the Invention The stack overflow detection device of the present invention includes an upper limit register that defines the upper limit of the stack area, a lower limit register that defines the lower limit of the stack area, and an upper limit comparator that compares the value A of the address bus with IfAu of the upper limit register. , a lower limit comparator that compares the value A of the address bus line with the value A2 of the lower limit register, and a control unit that detects that it is a stack manipulation instruction, and can detect program variations due to stack overflow. It is.

Description of examples FIG. 3 is a clock diagram showing an embodiment of the present invention.

In FIG. 3, 1o is an arithmetic processing unit, 11 is a main storage device, 12 is an address bus line, 13 is a data bus line, 14 is an interrupt request line, 15 is an interrupt response cycle display signal (interrupt cycle signal) line, and 16 is a is an instruction fetch cycle display signal (fetch cycle signal) line, 17 is an arithmetic processing unit operation signal (clock signal) line, 20 is a stack area upper limit regulation register (upper limit register), 21 is a stack area lower limit regulation register (lower limit register), 22 is an upper limit comparator, 23
24 is a lower limit comparator, 24 is a control unit, 25 is a stack operation detection signal line, and 30 is a stack overflow detection signal line.

The operation of the stack overflow detection device of this embodiment configured as described above will be described below.

The arithmetic processing bag [10 reads instructions sequentially from the main memory 11 and executes the processing. At this time, as a command related to stack operation, PUSH (saving data to stack)
, POP (recovery of data from stack), C
ALL (branch to the subprogram and save the return address to the main program on the stack).

RET (retrieve the return address to the main program from the stack and return from the subprogram), etc. Upper limit register 20. The upper limit value Au of the stack area is stored in each lower limit register 21 in advance by means not shown in the figures.

The lower limit value Al of the stutter area is stored.

The control unit 24 reads the value of the data bus 13 when 1 is output to the fetch cycle signal line 16, and thereby learns the instructions read by the arithmetic processing unit 10, and issues the stack operation instructions CPUSH, POP, and CALL.

RET, etc.). When a stack manipulation command is detected, the relevant machine cycle is detected from the clock signal line 17 and the stack manipulation detection signal line 25 is determined, since the command specifies the number of machine cycles after which reading and writing to the stack will be performed. Outputs signal 1 to In addition, 1 is connected to the stack operation detection signal line 25.
is being output, the address value A to be subjected to the stack operation is being output to the address mother IfA12.

The upper limit comparator 22 compares the value A output to the address bus 12 with the value ~ of the upper limit register 2o when the signal 1 is output as the stack operation detection signal m25, and
'> Au, it has a function of outputting an overflow signal l. The lower limit comparator 23 similarly compares the value A output on the address bus 12 with the value At of the lower limit register 21, and has the function of outputting an under 70-signal 1 if A<Az.

Therefore, according to the above function, if the address value A targeted by the stack manipulation instruction is A>Au or A<Az, the OR gate 26 generates the stack overflow detection signal Jij.
1 is output to -1i 130, and all stack overflows can be detected.

Further, when an interrupt request is issued to the arithmetic processing unit 10 and data is saved to the stack area, the control unit 24 detects the data saving operation to the stack area using the interrupt cycle signal gauze 15, and the arithmetic processing unit 10 Stack overflow can be similarly detected by comparing the value A of the data storage address with the value A□ of the upper limit register 20 and the value At of the lower limit register 21 according to the timing defined in .

Effects of the Invention According to the stack overflow detection IAfit of the present invention, since stack overflow can be detected, abnormal processing caused by stack overflow can be easily detected.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are schematic diagrams showing how the main memory is used, respectively, and FIG. 3 is a block diagram of a stack overflow detection device in an embodiment of the present invention. 3... Stack area, 10... Arithmetic processing unit, 12
...Address bus, 13...Data bus, 14...
- Interrupt request m, 20... Upper limit register, 21... Lower limit register, 22... Upper limit comparator, 23... Lower limit comparator, 24... Control unit, 25... Stack operation detection Signal line, 3°...Stack overflow detection signal line Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] (1) an upper limit register that defines the upper limit of the stack area; a lower limit register that defines the lower limit of the stack area;
a control unit that decodes an instruction read by the arithmetic processing unit and detects that the instruction is an instruction to read/write data to the stack area (stack manipulation instruction); an upper limit comparator that compares the value A output to the address bus when an operation command is executed with the value Au of the upper limit register to detect whether A>Au; Compare the value At of the lower limit register and find that A<A
A stack overflow detection device comprising a lower limit comparator for detecting whether or not t. (21) The control unit has a function of controlling the upper limit comparator and the lower limit comparator by detecting an operation of saving and storing an internal register in a stack area when accepting an interrupt request of the arithmetic processing unit. Stack overflow detection device according to scope (1).