JPH06250864A - Method for preventing generation of error output from programmable controller - Google Patents

Abstract

PURPOSE:To make a device compact by detecting the runaway of an arithmetic processor, inputting an interruption, determining an output signal from the processor at a safety side level, and supplying the output signal to an output circuit. CONSTITUTION:A central processing unit(CPU) 3 controls the operation of the whole device, executes a sequence program stored in a built-in RAM 5 and executes the automatic control of an electronic apparatus. A monitoring timer 6 is functioned as a watchdog timer to detect the abnormality of the CPU 3, and when time-up is generated, inputs an interrupt to the CPU 3. Receiving the interruption input, the CPU 3 transfers a current program reading address to the leading storing address of an interruption program stored in a built-in program memory 4. Consequently the CPU 3 sends an OFF signal to the output circuit 11 through an I/O port 8. Consequently an exclusive reset signal line and an external timer can be made unnecessary and the device can be made compact.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing erroneous output of a programmable controller for controlling electronic devices controlled by the programmable controller to a safe side when a microcomputer in the programmable controller runs out of control.

[0002]

2. Description of the Related Art Conventionally, a programmable controller receives an operation state signal from an electronic device to be controlled via an input / output device, and sends a control signal to the electronic device to instruct the operation of the electronic device according to the content of the received signal. I am sending. To this end, the programmable controller has a microcomputer built therein, and causes the microcomputer to execute a sequence program to determine the content of the control signal (hereinafter referred to as an output signal). As is well known, a microcomputer may cause a program execution order to be out of order due to noise influence.

Therefore, in a conventional programmable controller, a watchdog timer (see FIG. 4) called a watchdog timer detects runaway. More specifically, the watchdog timer 18 is reset at regular intervals by software execution processing on the microcomputer 2 side before the watchdog timer 18 counts a fixed time, so that the watchdog timer 18 is not counted up. Since the watchdog timer 18 is not reset when the microcomputer 2 runs out of control, the watchdog timer 18 counts a fixed time and generates a time-up signal 19. The time-up signal 19 is sent as a reset signal to the microcomputer 2 and the external input / output port (input / output device) 16. This reset signal releases the microcomputer 2 from the runaway state and sets it to the initial state.

On the side of the external input / output port 16, all the output signals transmitted to the controlled object are set to off by the reset signal. As a result, even if the microcomputer 2 runs out of control, the electronic device to be controlled is controlled on the safe side.

[0005]

Although the microcomputer 2 and the external input / output port 16 are connected by the input / output signal line, the watchdog timer 1
Providing a dedicated reset signal line between the I / O 8 and the external input / output port 16 increases the number of signal lines, leading to an increase in size of the device. Further, some microcomputers have a built-in timer, and such a microcomputer has two timers, which also leads to an increase in the size of the device.

Therefore, in view of the above points, an object of the present invention is to provide a method for preventing erroneous output of a programmable controller that can contribute to downsizing of the device.

[0007]

In order to achieve such an object, the invention of claim 1 controls the operation of the controlled device by an output signal output from the output circuit of the programmable controller to the controlled device. In a method of preventing an erroneous output of a programmable controller, which prevents erroneous output of the output signal to the controlled device when the arithmetic processor of the programmable controller is out of control when the content of the output signal is determined by the arithmetic processor of the programmable controller. The watchdog timer detects runaway of the arithmetic processor, interrupts the detection signal to the arithmetic processor, and in response to the interrupt input, the arithmetic processor determines the output signal to a safe side level. The determined output signal is supplied to the output circuit.

According to a second aspect of the present invention, the operation of the controlled device is controlled by an output signal output from the output circuit of the programmable controller to the controlled device, and the content of the output signal is determined by the arithmetic processor of the programmable controller. In this case, in a programmable controller erroneous output prevention method for preventing erroneous output of the output signal to the control target device when the arithmetic processor runs out of control, a watchdog timer detects the runaway of the arithmetic processor, and detects the runaway. An interrupt signal is input to the arithmetic processor, and the arithmetic processor supplies a reset signal to the output circuit in response to the interrupt input, thereby setting the output signal to a safe level.

[0009]

The present invention focuses on the point that a processor such as a CPU or a microprocessor has an interrupt function, and when an interrupt signal is input from the outside, the storage address of a predetermined interrupt program is automatically set as the program execution address. However, even if the execution address of the arithmetic processor becomes indefinite due to the occurrence of runaway, this interrupt processing normally returns the indefinite execution address to a specific address. According to the invention of claim 1, the level itself of the output signal is determined by the interrupt processing. Therefore, a dedicated reset signal line as in the conventional case is not necessary. According to the second aspect of the present invention, since the reset signal supplied to the output circuit is created by the interrupt processing, it is not necessary to create the reset signal by an external timer.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the main configuration of a programmable controller to which the present invention is applied. The same parts as those in the conventional example of FIG. 4 are designated by the same reference numerals.

In FIG. 1, the following circuits are connected to the internal bus 9. The central processing unit (CPU) 3 controls the operation of the entire apparatus and executes a sequence program stored in the built-in RAM 5 to execute automatic control of electronic equipment. A system program executed by the CPU 3 is stored in the built-in program memory 4. An interrupt program defining the interrupt processing according to the present invention is also stored in the built-in program memory 4. A built-in RAM (random access memory) 5 temporarily stores various data used by the CPU 3. The sequence program is also temporarily stored in this memory.

The monitoring timer 6 functions as a watchdog timer, and when the CPU 3 is in a normal state,
The reset process prevents the time from increasing. In this embodiment, a program for clearing (resetting) the monitoring timer 6 is provided at a predetermined position in the execution program of the CPU 3. The time-up signal 7 of the monitoring timer 6 is input to the interrupt signal input terminal of the CPU 3. In this embodiment, the monitoring timer 6 detects an abnormality of the CPU 3, and when the time is up, interrupts the CPU 3 to release the runaway state and turn off the output signal to the input / output device. It is characterized in that the CPU 3 is caused to execute a countermeasure (erroneous output prevention) process.

The input / output port 8 is an electronic device to be controlled and C
Transfers the input / output signals exchanged with the PU3. The bus expansion buffer 10 connects the external bus 14 and the internal bus 9, and, for example, stores information in the expansion program memory 13 in the CPU.
Transfer to 3. The above circuits are integrated to form a one-chip microcomputer 2. Further, the input / output port 8 of the microcomputer 2 is connected to the input circuit 12 and the output circuit 11. The input circuit 12 converts an input signal sent from the controlled device into a control signal that can be processed by the CPU 3. On the contrary, the output circuit 11 converts the control signal into a signal that can be processed by the controlled device. The programmable controller system 1 is configured by the above circuits.

The abnormality handling processing executed in such a configuration will be described with reference to FIGS. 1 and 2. FIG. 2 shows an interrupt program stored in advance in the built-in program memory 4, which is activated by a time-up signal from the monitoring timer 6.

While the CPU 3 is operating normally, the CPU
Due to the reset processing of 3, the monitoring timer 6 does not time up. When the program read address of the CPU 3 changes due to the influence of noise, short circuit or opening of the printed board, the CPU 3 starts so-called runaway. As a result, as in the conventional case, the monitoring timer 6 times up, and a time-up interrupt signal 7 is generated. By this interrupt input, the CPU 3 shifts the current program read address (undefined state) to the head storage address of the interrupt program. Therefore, the CPU 3 starts the control procedure of FIG. That is, the CPU 3 selects the input / output port 8 and sends an off signal to the output circuit 11 via the input / output port 8. When the level for setting the controlled device to the safe side is ON, the output signal level is naturally set to ON (S10). The CPU 3 executes other processing for coping with the abnormality and stops (S20).

In addition to this embodiment, the following modifications can be implemented.

1) The external external monitoring timer 18 can be used for other purposes by partially using the existing circuit of the conventional example shown in FIG. The circuit configuration in this case is shown in FIG. In this example, one of the output signals of the input / output port 8 is connected to the reset input of the external input / output port 16, and all the signals output from the external input / output port 16 are turned off. In this example, the number of signals set by the CPU 3 in the interrupt processing of FIG. 2 is one of the reset signals, which is advantageous in that high-speed processing is possible. This example corresponds to the invention of claim 2.

2) Further, in FIG. 4, the reset of the external external monitoring timer 18 is interrupt-input to the microcomputer 2 and the output signal to the output circuit 11 is turned off via the bus expansion buffer 10 by the interrupt processing of the CPU 3. You can

3) Any microcomputer having an interrupt function may be used as the microcomputer used in the present embodiment. In particular, if a microcomputer that cannot mask the interrupt signal is used, the abnormality handling processing is more effective. Be certain.

[0021]

As described above, according to the present invention,
Since a reset signal line and an externally attached timer, which are conventionally required, can be eliminated, it is possible to contribute to downsizing of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the contents of processing executed by a CPU 3 in FIG.

FIG. 3 is a block diagram showing another circuit configuration of the embodiment of the present invention.

FIG. 4 is a block diagram showing a circuit configuration of a conventional example.

[Explanation of symbols] 1 programmable controller system 2 microcomputer 3 CPU 4 built-in program memory 5 built-in RAM 6 watchdog timer 7 time-up interrupt signal 8 input / output port 9 internal bus 10 bus expansion buffer 11 output circuit 12 Input circuit 13 Extended program memory 14 External bus 15 Output (control) signal 16 External I / O port 17 Port output signal (reset signal) 18 External monitoring (watchdog) timer 19 Time-up signal (reset) signal

Claims (2)

[Claims] 1. When the operation of the controlled device is controlled by an output signal output from the output circuit of the programmable controller to the controlled device and the content of the output signal is determined by an arithmetic processor of the programmable controller, the arithmetic operation is performed. In a programmable controller erroneous output prevention method for preventing erroneous output of the output signal to the controlled device when the processor runs out of control, a watchdog timer detects runaway of the arithmetic processor, and outputs a detection signal to the arithmetic processor. Erroneous output of a programmable controller characterized in that the arithmetic processor determines the output signal to a level on the safe side in accordance with the interrupt input, and supplies the determined output signal to the output circuit. Prevention method. 2. The operation when the operation of the controlled device is controlled by an output signal output from the output circuit of the programmable controller to the controlled device and the content of the output signal is determined by an arithmetic processor of the programmable controller. In a programmable controller erroneous output prevention method for preventing erroneous output of the output signal to the controlled device when the processor runs out of control, a watchdog timer detects runaway of the arithmetic processor, and outputs a detection signal to the arithmetic processor. To the erroneous output prevention method of a programmable controller, characterized in that the arithmetic processor supplies a reset signal to the output circuit in response to the interrupt input to set the output signal to a safe level. .