JPH0251748A - Microcomputer - Google Patents

Abstract

PURPOSE:To actuate a system toward the safety side even at an abnormal action by outputting the overflow output signal of a watchdog timer, i.e., the output latch data decided previously and simultaneously with detection of the CPU abnormality to an output port. CONSTITUTION:At a normal action an output selector 11 selects B and therefore outputs the write data received from an internal bus 6 to the port output 13 via the output latch B7. A watchdog timer 1 is cleared by the clear instructions produced for each module and therefore produces no overflow signal 3. At the same time, a data latch circuit 5 is kept in an unoutput state. Then the signal 3 (watchdog timer output) is outputted by an abnormal action of a CPU. Thus a signal is outputted to the selector 11 from the circuit 5, and the selector 11 selects an output latch A9 to output the prescribed data (a high or low level) to the output 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and more particularly to a kill microcomputer by outputting predetermined output latch data to a port using an output signal of a watchdog timer.

[Conventional technology]

Conventionally, in this type of microcomputer, the output of the watchdog timer is used as an output to detect program runaway or system abnormality, and the output port is normally used to connect the output latch and accumulator with a transfer command during normal operation. Data was exchanged between them, and the output latch data was output to the port.

[Problem to be solved by the invention]

The conventional microcomputer technology described above uses the watchdog timer as a function to prevent program runaway and deadlock, and inserts an instruction to clear the tydog timer in each module of the program to generate the watchdog timer output. It is used to confirm that a program or system is working properly by not checking the system. On the other hand, if an overflow output is output from the watchdog timer, the microcomputer is already in abnormal operation state 8 at this point, and the output latch may be rewritten. The overflow output is processed as a non-maskable interrupt request, the microcomputer is reset again, the program is restarted from the beginning, and normal port output is restored.

Therefore, after the watchdog timer overflow is output, the value of each output port will be temporarily in an undefined state until the program restarts and returns to normal operation.
In devices that require high reliability using microcomputers, such as robot control, NC control, and automobile electrical equipment control, when a program runs out of control as described above, a fixed output cannot be obtained from the output port, resulting in unpredictable operation. It has the disadvantage that it does.

[Means to solve the problem]

The microcomputer of the present invention includes a circuit that latches the overflow output of a watchdog timer, a selector circuit that selects two inputs using this signal, an output latch circuit for normal operation input to the selector circuit, and an output for abnormal operation. It also has a child circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The watchdog timer 1 is a timer operated by the input signal of the internal clock fcL2 and outputs an overflow signal 3 as the watchdog timer output when a predetermined time has been counted. This watchdog timer 1 can be cleared by a clear signal 4, and when the clear signal 4 is input, it starts counting from the beginning. The overflow signal 3 is output as a watchdog timer output and is also latched by the data latch circuit 5.

When the data latch circuit 5 receives an overflow signal, it latches the data and outputs the data to the next stage (output selector 11), but when the clear signal 4 is input, the output is stopped.

The output latch B7 is a circuit that latches output data (high or low level) from the internal bus 6 in response to the port write signal B8, and is used during normal operation. Output latch A9
C is a circuit that latches data (high or low level) from the internal bus 6 using the port write signal AIO.
Write the data you want to output when the PU malfunctions.

Latch data of each output latch A, B is input to an output selector 11. This output selector 11 is a circuit that selects two types of input data, and selects A when the output signal of the data latch circuit 5 is input to SEL, and selects B otherwise.0 selection. The output signal is sent to port output 1 by output buffer 12.
It has a structure that is output to 3.

During normal operation, the output selector selects B, so write data from the internal bus is output through output latch B to the port output. Furthermore, since the watchdog timer is cleared by a clear command entered for each module of the program, no overflow signal is generated and the data latch circuit is also in a non-output state.

When an overflow signal (watchdog timer output) is output due to abnormal operation of the CPU, a signal is output from the data latch circuit to the output selector, and the output selector circuit selects output latch A and outputs predetermined data (high or low level). output to the port output.

〔Effect of the invention〕

As explained above, the present invention can output the predetermined output latch data to the output port at the same time as the overflow output signal of the watchdog timer, that is, the abnormality detection of the CPU. This allows the system to be designed to operate safely even when the microcomputer malfunctions, and has the effect of minimizing unpredictable operations due to system runaway.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the microcomputer of the present invention. ■・・・Watchdog timer, 2・・・・・・
Internal clock fcLx, 3... Overflow signal (watchdog timer output), 4... Clear signal, 5... Data controller, child circuit, 6...
... Internal bus, 7... Output latch B, 8...
...Port write signal B, 9...Output latch A, IO...Port write signal A, 11
...Output selector, 12...Output buffer, 13...Port output. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] It has a watchdog timer function, and as an output port function, data can be exchanged between the output latch and the accumulator using transfer commands, and data once written to the output latch is stored until the next command to operate the port is executed. What is claimed is: 1. A microcomputer having a latched output port, the microcomputer being capable of outputting predetermined output latch data based on an output signal of a watchdog timer.