JPS6362776B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a computer device equipped with a fault diagnosis for monitoring the operation of a computer. Conventional computer equipment often uses multi-chip systems in which the program storage device, temporary data storage device, central processing unit, input/output device, etc. are configured with independent LSIs (Large-Scale Integrated Circuits) for each function. However, recently there has been an increasing trend toward single-chip microcomputers (hereinafter referred to as computers) that incorporate the above functions into a single LSI. Some single-chip computers, such as the 6801 in the 6800 series, can operate in multi-chip mode in addition to single-chip mode. Many computer systems, both single-chip and multi-chip, are equipped with a fault diagnosis system commonly called a watchdog. The conventional device will be explained below with reference to the drawings. Figure 1 shows a single-chip computer.
This is a block diagram showing the internal configuration when using MC6801. In the figure, 1 indicates a single-chip computer (MC6801), 2 indicates a central processing unit (hereinafter referred to as CPU), and 3 indicates a reset signal (RESET). 4 is the input/output port 2, 5 is the timer, 6 is the serial I/O, 7 is the input/output port 1, and 8 is the data bus and address register. A multiplexer 9 that synthesizes sequentially transmits the output of the multiplexer 8 to the outside depending on the mode,
Ports 3 and 10, which operate as input/output ports, are address ports, or ports 4 and 11, which operate as input/output ports, are temporary data storage devices (hereinafter referred to as RAM).
), and 12 is a storage device (hereinafter referred to as ROM) containing a program that defines the operating specifications of the computer 1. As shown in Table 1 below, the computer 1 of the MC6801 can perform eight types of operations depending on the state of the mode set bits Pc ₀ to Pc ₂ of the mode register 3, and the data in the mode register 3 can be reset and released. It matches the data of port 24 at the time.

[Table] Furthermore, FIG. 2 shows a conventional computer device equipped with a fault diagnosis function in which the computer 1 is used in a single-chip mode (mode 7). In the figure, 20 indicates a computer device equipped with a fault diagnosis function, 21 indicates an input processing circuit,
22 is an output processing circuit; 23 to 25 are pull-up resistors; 26 is a reset circuit (also called a reset signal generation circuit) that generates a reset signal when the power is turned on;
27 is an abnormality detection device which determines that the computer is abnormal and outputs a reset pulse when the frequency of the pulse signal output from the output terminal _P10 of the computer 1 falls below a certain value, and 28 receives the reset pulse as input. It is an OR circuit. Next, the operation of the above-mentioned conventional device will be explained. When a power source (not shown) is applied to the computer device 20, a predetermined voltage is applied to each circuit, and at the same time a reset pulse is generated for a certain period of time from the reset circuit 26, and a reset signal is sent to the computer 1 through the OR circuit 28. At the same time that the reset pulse is applied, the reset pulse of the abnormality detection device 27 is prohibited, and is maintained for a predetermined time even after the reset pulse is released. In the reset state, all ports are in input mode, so the _P20 to _P22 terminals of port 24 are connected to pull-up resistors 23 to 24.
25 becomes a High (hereinafter referred to as "H") state. When the reset signal goes from LOW (hereinafter referred to as "L") to "H" and the logic level of the _P20 to _P22 terminals when the reset is released is read into the mode register 3, the operating mode of the computer 1 is set. is determined, mode register 3 contains
"H" data of each of the Pc ₀ to Pc ₂ terminals is accumulated, and the operation mode becomes the single chip mode according to Table 1 above. In the single chip mode, instructions are read from the ROM 12 shown in FIG. 1, input signals _P40 to _P4o are processed according to the contents, and outputted to output terminals _P30 to _P3o . FIG. 3 shows a flowchart of an example of arithmetic processing by the CPU 2. The example in FIG. 3 shows calculation processing of an automobile engine control device, including ignition timing control processing 100 and fuel injection amount control processing 10.
1. After executing the exhaust gas control process 102, the inversion process 103 of the P ₀ output of the port 17 is performed, and the process returns to the ignition timing control 100. Therefore, when the device is operating normally, a pulse with a period determined by the calculation cycle is output to the _P10 output of the port 17, so that the abnormality detection device 27 does not output a reset pulse. Next, computer 1 malfunctions due to external noise, etc., and P ₁₀ output inversion processing 103 of port 17 occurs.
When is no longer executed, no pulses are output from the _P10 output terminal. The abnormality detection device 27 detects that the frequency of the input pulse has fallen below a certain value and outputs a reset pulse, so the computer 1 is reset through the OR circuit 28 and starts all processing again from the beginning. Return to normal state. Incidentally, when the contents of the operating mode register 3 change due to external noise or the like and the single chip mode (mode 7) becomes mode 5 or mode 6, data and address bus are output from the port 39. In this case, computer 1 has internal ROM 12
Since the control related to port 17 is executed normally, a pulse corresponding to the calculation cycle is output from the _P10 output terminal, and a reset pulse is not output from the abnormality detection device 27, indicating normal operation. It becomes impossible to return to the normal state. In view of the above points, the present invention has been made in order to eliminate such conventional drawbacks, and it is possible to reliably detect a failure even if the data of the mode register changes,
It is an object of the present invention to provide a computer device equipped with a fault diagnosis that returns to normal by outputting a reset pulse from an abnormality detection device. In order to achieve this purpose, this invention
A readable register that stores computer operation mode data in synchronization with a computer reset signal, a storage section that stores data corresponding to the operation mode, and a comparator that compares the data in this storage section with the data in the register. and an output terminal that outputs an abnormal signal to the outside when these data do not match, and a reset circuit that applies a reset signal to the computer based on the abnormal signal from this output terminal, and detects a mode change of the computer and resets the computer. It is designed to apply . Hereinafter, one embodiment of the computer device according to the present invention will be described with reference to the flowchart shown in FIG. Here, the same reference numerals as in FIGS. 1 to 3 indicate the same or corresponding parts, and as in the conventional example described above, when the reset signal changes from "L" to "H", the operating mode of the computer 1 is changed to the mode register 3. is loaded into single-chip mode, and internal ROM1
Processing is started in response to command 2. And the fourth
As shown in the flowchart of the figure, after executing the ignition timing control process 100, the fuel injection amount control process 101, and the exhaust gas control process 102, the data of the operation mode register 3 is read, and the single data stored in a part of the ROM 12 is read. Compare with data according to chip mode. At this time, if normal, port 17
After executing the _P10 output reversal process 103, the process returns to the ignition timing control process 100. As a result, when the data in the mode register 3 is normal, the operation is exactly the same as in the conventional example described above. Next, due to external noise etc., the mode register 3
When the data changes, it is detected as an abnormality because it does not match the data in the ROM 12, and the ignition timing control process 1 is executed without going through the _P10 output reversal process 103 of the port 17.
Return to 00. Therefore, a pulse is no longer output from the _P10 output terminal, and a reset pulse is output from the abnormality detection device 27 to reset the computer 1. Then, by executing mode reading again, the contents of the mode register 3 become normal, so that the operation returns to normal. In the above embodiment, the case of the MC6801 as a single-chip computer has been explained, but it is clear that a similar effect can be achieved with a computer such as the 8048. Further, regarding the abnormality detection means, although it is determined that the frequency is below a certain level as an abnormality, it is clear that the same effect can be obtained even if the frequency is outside a predetermined frequency range as an abnormality. As described above, according to the present invention, the operating mode of the computer is stored in the ROM, compared with the contents of the mode register, and if they do not match, the mode register is reset, so that malfunctions due to external noise etc. can be avoided. However, it has the effect of being able to return to normal in a short period of time.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the internal configuration of a single chip computer (MC6801), Figure 2
The figure is a block diagram showing a computer device, FIG. 3 is a flowchart showing the operation of the conventional device, and FIG.
The figure is a flowchart showing one embodiment of the present invention. 1...Single chip computer (MC6801), 2...Central processing unit (CPU), 3
...Mode register, 4...Port 2, 11...
Temporary data storage device (RAM), 12...program storage device (ROM), 21...input processing circuit,
22...Output processing circuit, 26...Reset circuit,
27... Abnormality detection device, 28... OR circuit.

Claims (1)

[Claims] 1 Program storage device, temporary data storage device,
A computer device equipped with a central processing unit and an input/output device includes a readable register that stores computer operating mode data in synchronization with a computer reset signal, and a storage unit that stores data corresponding to the operating mode. , a comparator that compares the data in the storage section and the data in the register, an output terminal that outputs an abnormal signal to the outside when the respective data do not match, and a reset signal applied to the computer by the abnormal signal from the output terminal. A computer device comprising a reset circuit.