JPH02278342A - Microcomputer - Google Patents

Microcomputer

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Publication number
JPH02278342A
JPH02278342A JP1100403A JP10040389A JPH02278342A JP H02278342 A JPH02278342 A JP H02278342A JP 1100403 A JP1100403 A JP 1100403A JP 10040389 A JP10040389 A JP 10040389A JP H02278342 A JPH02278342 A JP H02278342A
Authority
JP
Japan
Prior art keywords
circuit
data
parity
parity generation
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1100403A
Other languages
Japanese (ja)
Other versions
JP2847741B2 (en
Inventor
Toru Henmi
逸見 亨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1100403A priority Critical patent/JP2847741B2/en
Publication of JPH02278342A publication Critical patent/JPH02278342A/en
Application granted granted Critical
Publication of JP2847741B2 publication Critical patent/JP2847741B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To prevent the abnormal action of a system by outputting an interruption request signal from a comparison circuit, permitting an interruption control circuit to generate interruption and taking measures to a runaway with the program of an interruption processing when data of an output circuit changes. CONSTITUTION:When a micro computer executes a write instruction, eights bits data are written into output latches 1-8 from internal part data buses 17-24, and the parity of eight bits data is simultaneously generated in a parity generation circuit 27. At that time, a write signal 25 is inverted in an invertor circuit 31 and a parity generation circuit 28 comes to be non-selective. When the write instruction is not executed on the other hand, the parity generation circuit 28 is selected, and the parity of eight bits data of the output latches 1-8 is generated. Data on the parity generation circuits 27 and 28 are inputted to a the comparison circuit 29, and the interruption request signal 32 is outputted to the interruption control circuit 30 when data are different. Thus, the runaway of the system can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマイクロコンピュータ、特に、システムの暴走
を防ぐ機能を有するマイクロコンピュタに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to a microcomputer having a function to prevent a system from running out of control.

〔従来の技術〕[Conventional technology]

従来のマイクロコンピュータについて図面を参照して詳
細に説明する。
A conventional microcomputer will be described in detail with reference to the drawings.

第2図は従来のマイクロコンピュータの一例を示すブロ
ック図である。
FIG. 2 is a block diagram showing an example of a conventional microcomputer.

第2図に示すマイクロコンピュータは、プログラム(以
下、書き込み命令という)により出力回路26にデータ
を書き込むと、出力回路26は次の書き込み命令が実行
されるまで、同じデータを出力端子9〜16に出力しつ
づける。
In the microcomputer shown in FIG. 2, when data is written to the output circuit 26 by a program (hereinafter referred to as a write command), the output circuit 26 outputs the same data to output terminals 9 to 16 until the next write command is executed. Continue outputting.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のマイクロコンピュータは、出力端子が外
来のノイズ、ザージなどの影響を受けて、出力回路のデ
ータが変化しても、その状!ぷを検出することができな
いため、システムの正常な動作を妨げるという欠点があ
った。
The conventional microcomputer described above does not change the state even if the output terminal is affected by external noise, surge, etc. and the data in the output circuit changes. This has the disadvantage that it prevents the normal operation of the system because it cannot detect the

本発明の目的は、出力回路のデータが書き込み命令とは
独立して変化した場合に、その状態を検出してシステム
の暴走を防ぐ機能を有するマイクロコンピュータと提供
することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer that has a function to prevent a system from running out of control when data in an output circuit changes independently of a write command.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のマイクロコンピュータは、プログラムの実行に
よりデータを書き込み、そのnビットデータ(nは正の
整数)をパラレルに外部に出力する出力回路を有するマ
イクロコンピュータにおいて、 (A)前記出力回路に書き込まれたnビットデータのパ
リティを生成する第1と第2のパリティ生成回路、 〈8)前記第1と第2のパリティ生成回路を比較すし、
比較信号を出力する比較回路、 (C)前記比較信号にもとづいて動作する割り込み制御
回路、 とを含んで構成される。
The microcomputer of the present invention is a microcomputer having an output circuit that writes data by executing a program and outputs the n-bit data (n is a positive integer) to the outside in parallel. first and second parity generation circuits that generate parity for n-bit data; (8) comparing the first and second parity generation circuits;
A comparison circuit that outputs a comparison signal; and (C) an interrupt control circuit that operates based on the comparison signal.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

第1図に示すマイクロコンピュータは、書き込み命令を
実行しると、書き込み信号25が有効となり、内部デー
タバス17〜24より出力ラッチ1〜8に8ビツトデー
タが書き込まれる。
When the microcomputer shown in FIG. 1 executes a write command, the write signal 25 becomes valid and 8-bit data is written into the output latches 1-8 from the internal data buses 17-24.

同時に、8とットデータのパリティがパリティ生成回路
27で生成される。この時、パリティ生成回路28は書
き込み信号25がインバータ回路31で反転されて非選
択となる。
At the same time, parity of 8 bit data is generated by the parity generation circuit 27. At this time, the write signal 25 of the parity generation circuit 28 is inverted by the inverter circuit 31 and becomes non-selected.

一方、書き込み命令が実行されない時は、パリティ生成
回路28が選択されて、出力ラッチ1〜8の8ビツトデ
ータのパリティを生成する。
On the other hand, when a write command is not executed, the parity generation circuit 28 is selected and generates parity for the 8-bit data of output latches 1-8.

パリティ生成回路27とパリティ生成回路28のデータ
は、比較回路29に入力される。
The data of the parity generation circuit 27 and the parity generation circuit 28 are input to the comparison circuit 29.

比較された結果、パリティ生成回路27とパリティ生成
回路28のデータが異っていると、割り込み制御回路3
0に割り込み要求信号32を出力する。
As a result of the comparison, if the data in the parity generation circuit 27 and the parity generation circuit 28 are different, the interrupt control circuit 3
The interrupt request signal 32 is output to 0.

〔発明の効果〕〔Effect of the invention〕

本発明のマイクロコンピュータは、外来のノイズ、サー
ジなどの影響を受けて、出力回路のデータが変化した場
合、比較回路より割り込み要求信号が出力され、割り込
み制御回路により割り込みが発生するので、割り込み処
理のプログラムで暴走対策を行なうことにより、システ
ムの異常動作を防止できるという効果がある。
In the microcomputer of the present invention, when the data of the output circuit changes due to the influence of external noise or surge, the comparator circuit outputs an interrupt request signal, and the interrupt control circuit generates an interrupt. By taking measures against runaway in the program, it is possible to prevent abnormal system operation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
従来の一例を示すブロック図である。 1〜8・・・・・・出力ラッチ、9〜16・・・・・・
出力端子、17〜24・・・・・・内部データバス、2
5・・・・・・書き込み信号、26・・・・・・出力回
路、27.28・・・・・・パリティ生成回路、2つ・
・・・・・比較回路、30・・・・・・割り込み制御回
路、31・・・・・・インバータ回路、32・・・・・
・割り込み要求信号。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1 to 8...Output latch, 9 to 16...
Output terminals, 17-24...Internal data bus, 2
5...Write signal, 26...Output circuit, 27.28...Parity generation circuit, two...
... Comparison circuit, 30 ... Interrupt control circuit, 31 ... Inverter circuit, 32 ...
-Interrupt request signal.

Claims (1)

【特許請求の範囲】 プログラムの実行によりデータを書き込み、そのnビッ
トデータ(nは正の整数)をパラレルに外部に出力する
出力回路を有するマイクロコンピュータにおいて、 (A)前記出力回路に書き込まれたnビットデータのパ
リテイを生成する第1と第2のパリテイ生成回路、 (B)前記第1と第2のパリテイ生成回路を比較すし、
比較信号を出力する比較回路、 (C)前記比較信号にもとづいて動作する割り込み制御
回路、 とを含むことを特徴とするマイクロコンピュータ。
[Scope of Claims] A microcomputer having an output circuit that writes data by executing a program and outputs the n-bit data (n is a positive integer) to the outside in parallel, comprising: (A) data written to the output circuit; first and second parity generation circuits that generate parity of n-bit data; (B) comparing the first and second parity generation circuits;
A microcomputer comprising: a comparison circuit that outputs a comparison signal; (C) an interrupt control circuit that operates based on the comparison signal.
JP1100403A 1989-04-19 1989-04-19 Microcomputer Expired - Lifetime JP2847741B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1100403A JP2847741B2 (en) 1989-04-19 1989-04-19 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1100403A JP2847741B2 (en) 1989-04-19 1989-04-19 Microcomputer

Publications (2)

Publication Number Publication Date
JPH02278342A true JPH02278342A (en) 1990-11-14
JP2847741B2 JP2847741B2 (en) 1999-01-20

Family

ID=14273016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1100403A Expired - Lifetime JP2847741B2 (en) 1989-04-19 1989-04-19 Microcomputer

Country Status (1)

Country Link
JP (1) JP2847741B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62209628A (en) * 1986-03-11 1987-09-14 Nec Corp Parity check circuit for processor bus
JPS62293438A (en) * 1986-06-12 1987-12-21 Fujitsu Ltd Computer applied device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62209628A (en) * 1986-03-11 1987-09-14 Nec Corp Parity check circuit for processor bus
JPS62293438A (en) * 1986-06-12 1987-12-21 Fujitsu Ltd Computer applied device

Also Published As

Publication number Publication date
JP2847741B2 (en) 1999-01-20

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