JPS6029849A - Prevention system against malfunction of detecting circuit for processor malfunction - Google Patents

Prevention system against malfunction of detecting circuit for processor malfunction

Info

Publication number
JPS6029849A
JPS6029849A JP58127363A JP12736383A JPS6029849A JP S6029849 A JPS6029849 A JP S6029849A JP 58127363 A JP58127363 A JP 58127363A JP 12736383 A JP12736383 A JP 12736383A JP S6029849 A JPS6029849 A JP S6029849A
Authority
JP
Japan
Prior art keywords
processor
circuit
abnormality detection
monitor
abnormality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58127363A
Other languages
Japanese (ja)
Inventor
Yutaka Moriyama
裕 盛山
Shigeru Oe
大江　茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58127363A priority Critical patent/JPS6029849A/en
Publication of JPS6029849A publication Critical patent/JPS6029849A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Abstract

PURPOSE:To prevent malfunction even in case of wrong access to an undefined address and to continue normal data processing by stopping the output operation of an abnormality detecting circuit when the monitor function of a processor is operated externally. CONSTITUTION:While a data processor is in operation, ''0'' is set in a register 5 and an AND circuit 4 is on; when a processor 2 accesses an undefined address, abnormality is detected 3 and the AND circuit 4 outputs abnormality to stop the processor 2. Now, when a monitor command is inputted on a keyboard 1 so as to monitor the operation state of the processor through external operation, the processor 2 sends 1 to the register 5 to turn off the AND circuit 4. Even if access to the undefined address is attained by mistake in said state and abnormality is detected 3, the abnormality signal is cut off by the AND circuit 4. When a monitor program ends, the register 5 is reset. Consequently, malfunction in monitoring operation is prevented.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、外部からのモニタ機能を有するプロセッサに
おいて、オペレータ等の誤操作で、正常動作の場合には
アクセスすることのない未定Ｍ　７ドレスをアクセスし
たときに異常検出回路を動作させることがないようにし
たプロセッサ異常検出回路誤動作防止方式に関する。Detailed Description of the Invention [Technical Field of the Invention] The present invention provides a method for accessing an undetermined M7 address that would not be accessed during normal operation due to an operator's error in a processor having an external monitoring function. The present invention relates to a method for preventing malfunction of a processor abnormality detection circuit, which prevents the abnormality detection circuit from operating when the abnormality detection circuit is activated.

〔従来技術と問題点〕[Prior art and problems]

例えばマイクロ・コンピュータでは、メモリのアドレス
領域が６４にバイトあっても実際に使用する領域は限定
されている。したがってマイクロコンピュータが正常に
動作しているときではアクセスすることがない領域をも
しアクセスした場合には異に状態であるので、異常検出
回路でアクセス先アドレスを監視し９例えば上記の如き
異常状態力ｆ発生したときにこれを検出して、異常検Ｌ
１４信号を出力してこれを報知することが行われている
。For example, in a microcomputer, even if the memory address area is 64 bytes, the area that is actually used is limited. Therefore, if an area that is never accessed when the microcomputer is operating normally is accessed, it will be in an abnormal state, so the abnormality detection circuit monitors the access destination address. Detect this when it occurs and perform abnormality detection L
This is reported by outputting 14 signals.

ところがこのようなコンピュータにおいて、モニタ機能
を利用して、特定の部分の動作状態をチ”ニックするた
めオペレータがキーボードを操作してコマンド等を入力
し九とき、誤ったデータを入力して上記未定義領域をア
クセスすることがある。However, in such a computer, when an operator inputs a command etc. using the keyboard to check the operating status of a specific part using the monitor function, he may input incorrect data and cause the above-mentioned error to occur. The definition area may be accessed.

このような誤操作が行われたとき、異常検出回路が動作
してプロセッサを止めたり、リセットするなどデータ処
理装置の動作に大きな悪影響を与えるという問題が存在
した。When such an erroneous operation is performed, there is a problem in that the abnormality detection circuit operates and causes a large adverse effect on the operation of the data processing apparatus, such as stopping or resetting the processor.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、このような問題を改善するため、プロ
セッサのモニタ機能を外部から利用するとき、異常検出
回路を出力停止状態に制御して。SUMMARY OF THE INVENTION In order to solve this problem, an object of the present invention is to control an abnormality detection circuit to stop outputting when the monitor function of a processor is used from the outside.

誤操作によりメモリの未定義アドレスをアクセスして異
常検出回路が動作してもデータ処理装置に重大な悪影響
を及ばずことを防止したプロセッサ異常検出回路誤動作
防止方式を提供するものである。An object of the present invention is to provide a processor abnormality detection circuit malfunction prevention method that prevents a data processing device from being seriously adversely affected even if the abnormality detection circuit is activated by accessing an undefined address in a memory due to an erroneous operation.

〔発明の構成〕 この目的を達成するために本発明のプロセッサ異常検出
回路誤動作防止方式では、未定義アドレスのアクセスに
よりプロセッサの異常を検出するようにした異常検出手
段と、外部よりメモリやレジスタ等を参照できるモニタ
手段を備えたデータ処理装置において、異常検出手段の
出力回路に設けたゲート手段と、オペレータが入力した
コマンドを識別するコマンド識別手段と、上記ゲート手
段をオン・オフ制御するオン・オフ制御手段を設け、外
部よりモニタプログラム実行コマンドを入力−シたとき
上記オン・オフ制御手段により上記ゲート手段をオフ状
態に制御して上記異常検出手段の出力信号を阻止し、モ
ニタのプログラム実行時に誤操作により異常検出回路が
動作してもその出力信号を抑制するようにしたことを特
徴とする。[Structure of the Invention] In order to achieve this object, the processor abnormality detection circuit malfunction prevention method of the present invention includes an abnormality detection means that detects abnormality in the processor by accessing an undefined address, and an externally accessed memory, register, etc. In the data processing apparatus, the data processing apparatus includes a gate means provided in the output circuit of the abnormality detection means, a command identification means for identifying a command input by an operator, and an on/off control for controlling the gate means on and off. An off control means is provided, and when a monitor program execution command is input from the outside, the on/off control means controls the gate means to an off state to block the output signal of the abnormality detection means, and the monitor program is executed. The present invention is characterized in that even if the abnormality detection circuit operates due to an erroneous operation, its output signal is suppressed.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第１１１及び第２図にもとづき説明
する。An embodiment of the present invention will be described based on FIG. 111 and FIG.

第１図は本発明の一実施例構成を示し、第２図はそのプ
日セッサ部分の詳細図である。FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 is a detailed view of the processor portion thereof.

図中、１はキーボード、２はプロセッサ、３は異常検出
回路、４はアンド回路、５はレジスタ。In the figure, 1 is a keyboard, 2 is a processor, 3 is an abnormality detection circuit, 4 is an AND circuit, and 5 is a register.

１０は入力解析部、１１はコマンド識別部、１２はコマ
ンド実行部、１３はレジスタ・セット・リセット部であ
る。10 is an input analysis section, 11 is a command identification section, 12 is a command execution section, and 13 is a register set/reset section.

８常検ＩＢｎ路３は、メモリへのアドレスを監視してそ
の未定義アドレスをアクセスした場合にこれを異常発生
状態として検出し、異常検出信号を出力する。The 8 regular detection IBn path 3 monitors the address to the memory, and when the undefined address is accessed, it detects this as an abnormal state and outputs an abnormality detection signal.

アンド回路４は異常検出回路３の出力信号をオン・オフ
制御するものであり、レジスタ５に「０」がセットされ
たときオンとなり、「１」がセットされたときオフとな
る。The AND circuit 4 controls on/off the output signal of the abnormality detection circuit 3, and is turned on when the register 5 is set to "0" and turned off when the register 5 is set to "1".

レジスタ５はアンド回路４をオン・オフ制御するデータ
がセットされるものであり９通常は「０」がセットされ
てアンド回路４をオン状態にする。The register 5 is set with data for controlling the on/off of the AND circuit 4, and is normally set to "0" to turn the AND circuit 4 on.

しかし外部゛よりモニタ動作を実行させるとき、このレ
ジスタ５に「１」を記入してアンド回路４をオフにする
。このようにアンド回路４がオフになれば、外部からの
操作ミスによりメそりの未定義アドレスをアクセスした
ときでも異常検出回路３の出力信号は抑制される。However, when a monitor operation is to be executed externally, "1" is written in this register 5 to turn off the AND circuit 4. When the AND circuit 4 is turned off in this manner, the output signal of the abnormality detection circuit 3 is suppressed even when an undefined address in the memory is accessed due to an external operation error.

入力解析部１０はキーボード１より入力された信号を解
析し、これがコマンドの場合にはコマンド識別部１１に
出力する。The input analysis section 10 analyzes the signal input from the keyboard 1, and if the signal is a command, outputs it to the command identification section 11.

コマンド識別部１１は伝達されたコマンドを識別し、モ
ニタ機能プログラム実行コマンドの場合には、レジスタ
・セット・リセット部１３にセット信号を送出して、レ
ジスタ５にｒｌＪを出力させ、クロックＯＬＫによりレ
ジスタ５に「１」をセットさせ、このモニタ機能プログ
ラムが終了したときコマンド実行部１２がリセット信号
を出力してレジスタ５を「０」にリセットさせる。The command identification unit 11 identifies the transmitted command, and in the case of a monitor function program execution command, sends a set signal to the register set/reset unit 13, causes the register 5 to output rlJ, and registers by the clock OLK. 5 is set to "1", and when this monitor function program is completed, the command execution unit 12 outputs a reset signal to reset the register 5 to "0".

次に本発明の動作について説明する。Next, the operation of the present invention will be explained.

（リ　第１図において、データ処理装置が動作している
ときレジスタ５には「０」がセットされ、ア　。(In FIG. 1, when the data processing device is operating, "0" is set in register 5.

ンド回路４がオン状態にある。したがってプロセッサ２
に異常が発生し、未定義アドレスをアクセスしたとき、
異常検出回路３がこれを検出して異常検出信号を出力す
る。このとき上記の如くアンド回路４はオン状態のため
この異常検出信号がアンド回路４を経由して出力され、
異常状態にあることが認識され１例えばプロセッサ２が
停止する。The command circuit 4 is in the on state. Therefore processor 2
When an error occurs and an undefined address is accessed,
The abnormality detection circuit 3 detects this and outputs an abnormality detection signal. At this time, as mentioned above, since the AND circuit 4 is in the ON state, this abnormality detection signal is outputted via the AND circuit 4.
An abnormal state is recognized and the processor 2, for example, stops.

（２）いま、オペレータが外部がら操作できるプロセッ
サノモニタ機能を利用してその動作状態をチェックする
ため、メモリやレジスタ等の状態を参照したいとき、ま
ずキーボード１を操作し、モニタ機能操作コマンドを入
力する。このコマンドがコマンド識別部１１にて識別さ
れ、レジスタ・セット・リセット部１３がレジスタ５に
「１」を送出し、このレジスタ５を「１」にセットする
。これによりアンド回路４はオフとなる。また上記コマ
ンドによりコマンド実行部１２が動作してモニタ機能プ
ログラムを実行する。このとき、オペレータがキーボー
ド１より誤って未定義アドレスをアクセスするように操
作ミスを行ったとき、異常検出回路３は異常検出信号を
出力するものの、アンド回路４がオフのえめ、これがさ
らに出力されることはなく１例えばプロセッサが停止し
たり。(2) Now, when an operator wants to refer to the status of memory, registers, etc. in order to check the operating status of a processor by using the processor monitor function that can be operated externally, he first operates keyboard 1 and issues a monitor function operation command. input. This command is identified by the command identification section 11, and the register set/reset section 13 sends "1" to the register 5, setting the register 5 to "1". This turns off the AND circuit 4. Further, the command execution unit 12 operates according to the above command to execute the monitor function program. At this time, when the operator makes a mistake in accessing an undefined address from the keyboard 1, the abnormality detection circuit 3 outputs an abnormality detection signal, but the AND circuit 4 is turned off and this signal is not further output. For example, the processor may stop.

リセットするようなことはない。そして上記モニタ機能
プログラムが終了すれば、レジスタ５はリセットされ、
再びアンド回路４はオン状態になる。There is no such thing as resetting. When the monitor function program is finished, register 5 is reset.
The AND circuit 4 is turned on again.

なお、上記説明では、モニタ機能を使用するときレジス
タ５に「１」をセットしてインバート端子付のアンド回
路４をオフにする例について説明したが、このようなイ
ンバート端子付きのアンド回路を使用せず、モニタ機能
を使用するときアンド回路の一方の入力端子に「０」を
出力してこれをオフにしてもよい。In addition, in the above explanation, when using the monitor function, an example was explained in which "1" is set in the register 5 and the AND circuit 4 with an invert terminal is turned off. Instead, when using the monitor function, "0" may be output to one input terminal of the AND circuit to turn it off.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、外部からプロセッサのモニタ機能を利
用するとき、異常検出回路の出力を強制的に抑制するこ
とができるので、誤操作により未定義アドレスをアクセ
スしても、この誤操作による影響を防止することができ
、正常なデータ処理を継続させることができる。According to the present invention, when using the processor monitor function from the outside, it is possible to forcibly suppress the output of the abnormality detection circuit, so even if an undefined address is accessed due to an erroneous operation, the effects of this erroneous operation can be prevented. This allows normal data processing to continue.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例構成を示し、第２図はそのプ
ロセラ？部分の詳細図である。 図中、１はキーボード、２はプロセッサ、３は異常検出
回路、４はアンド回路、５はレジスタ。 １０は入力解析部、１１はコマンド識別部、１２ハコマ
ント実行部、ｉａはレジスタ・セット・リセット部であ
る。 特許出願人　富士通株式会社 代理人弁理士　山　谷　晧　榮 ″’ＦｌｆｆｉFig. 1 shows the configuration of an embodiment of the present invention, and Fig. 2 shows its processor configuration. It is a detailed view of a part. In the figure, 1 is a keyboard, 2 is a processor, 3 is an abnormality detection circuit, 4 is an AND circuit, and 5 is a register. 10 is an input analysis section, 11 is a command identification section, 12 is a command execution section, and ia is a register set/reset section. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Yamatani'''Flffi

Claims (1)

【特許請求の範囲】 未定義アドレスのアクセスによりプロセッサの異常を検
出するようにした異常検出手段と、外部よりメモリやレ
ジスタ等を参照できるモニタ手段を備えたデータ処理装
置において、異常検出手段の出力回路に設けたゲート手
段と、オペレータが入力したコマンドを識別するコマン
ド識別手段と。 上記ゲート手段をオン・オフ制御するオン・オフ制御手
段を設け、各部よりモニタプログラム実行コマンドを入
力したとき上記オン・オフ制御手段により上記ゲート手
段をオフ状態に制御して上記異常検出手段の出力信号を
阻止し、モニタのプログラム実行時に誤操作により異常
検出回路が動作してもその出力信号を制御するようにし
たことを特徴とするプロセッサ異常検出回路誤動作防止
方式。[Scope of Claims] In a data processing device comprising an abnormality detection means configured to detect an abnormality in a processor by accessing an undefined address, and a monitor means capable of referencing memory, registers, etc. from the outside, an output of the abnormality detection means is provided. A gate means provided in the circuit, and a command identification means for identifying a command input by an operator. An on/off control means for controlling the gate means on and off is provided, and when a monitor program execution command is input from each part, the on/off control means controls the gate means to an off state and outputs from the abnormality detection means. A system for preventing malfunction of a processor abnormality detection circuit, characterized in that the signal is blocked and the output signal of the abnormality detection circuit is controlled even if the abnormality detection circuit operates due to an erroneous operation during execution of a program on a monitor.
JP58127363A 1983-07-13 1983-07-13 Prevention system against malfunction of detecting circuit for processor malfunction Pending JPS6029849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58127363A JPS6029849A (en) 1983-07-13 1983-07-13 Prevention system against malfunction of detecting circuit for processor malfunction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58127363A JPS6029849A (en) 1983-07-13 1983-07-13 Prevention system against malfunction of detecting circuit for processor malfunction

Publications (1)

Publication Number Publication Date
JPS6029849A true JPS6029849A (en) 1985-02-15

Family

ID=14958104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58127363A Pending JPS6029849A (en) 1983-07-13 1983-07-13 Prevention system against malfunction of detecting circuit for processor malfunction

Country Status (1)

Country Link
JP (1) JPS6029849A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5086952A (en) * 1973-12-03 1975-07-12
JPS55159256A (en) * 1979-05-30 1980-12-11 Hitachi Ltd Address error processing system for microprogram

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5086952A (en) * 1973-12-03 1975-07-12
JPS55159256A (en) * 1979-05-30 1980-12-11 Hitachi Ltd Address error processing system for microprogram

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